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YTE - Department of Electrical and Electronics Engineering

EE342 - Digital System Design - Project Topics - Spring 2012 1

EE342 - Digital System Design

Project Topics All projects will be done by groups of two students. Project topics will be

distributed on a first-come, first-served basis. Send an e-mail [email protected] indicating the group members and the selectedproject topic.

Deadline for submission of Verilog source code and simulation test results forthe first stage of the project is Friday, 10 May 2013 . Deadline for completion of theentire project including the " Next Step " requirements is Friday, 31 May 2013 (end offinals).

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2. UART Transmitter You get:1. 76800 Hz clock input .

2. 8-bit data in parallel.3. An active-high pulse of 1 s-duration that indicates " data ready " at the parallelinputs.

Requirements:1. Store data when data ready pulse is received.2. Serial data output is high when it is idle.3. Serial output data rate is 9600 baud.4. Send data sequence is as follows:

1) One active-low start bit2) Eight data bits3) One active-high stop bit

Specific problems:1. The 1- s data ready pulse is too short compared to 76800 Hz clock period.2. Determine the duration of each bit sent out.3. Arrange the sequence of bits at the output.

Next step: Add the following programmable options:1. Baud rate selectable between 2400, 4800, 9600, and 19200.2. Even/odd parity or no parity bit.3. One or two stop bits. These options are entered through the same parallel data input used for data. A control input selects the parallel input type ( 0=> data to be transmitted,

1=> transmitter options) during the data ready pulse.

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3. UART Receiver You get:1. 76800 Hz clock input.

2. Serial data received as follows:1) One active-low start bit2) Eight data bits3) One active-high stop bit

Requirements:1. Serial data input is high when it is idle.2. Serial input data rate is 9600 baud.3. Store received data in a shift register. Stored data will be available as 8 parallelbits to be read by a microprocessor.

4. Generate an output pulse after receiving eight data bits and the stop bit.Specific problems:1. How will you determine the read timing to store the bits received at the input?2. Describe a method to decide when to stop reading serial data.

Next Step: Add the following programmable options:1. Baud rate selectable between 2400, 4800, 9600, and 19200.2. Even/odd parity or no parity bit. Generate an output signal indicating the parityerrors when parity check is enabled.3. One or two stop bits. Generate an output signal indicating error conditions whenstop bit(s) is not received (data input is low where it is supposed to be high). These options are entered through the same parallel data input used for data. An active-high pulse of 1 s-duration at the write enable input indicates that the

receiver options are being written.

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4. Arithmetic and Logic Unit (ALU) You get:1. 10 MHz clock input

2. A 16-bit operand input3. 4-bit operation code input4. A one-cycle active-high pulse indicating inputs are ready

Requirements:1. A 16-bit accumulator store the result of operations.2. Accumulator is the first operand in binary operations.3. Arithmetic operations use signed 2's complement representation.4. A carry output is generated and stored at the end of an operation when applicable.

5. List of operation codes are given below:Unary Operation Codes: Binary Operation Codes:(no operand is required) (operand is required)0000 Reset accumulator 1000 Load (copy operand to Acc)0001 Reset flag(s) 1001 Bitwise AND operation0010 1's complement 1010 Bitwise OR operation0011 2's complement 1011 Bitwise XOR operation0100 Shift left, Acc[0]

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5. PWM Controller You get:1. 10 MHz clock

2. An 8-bit data interface to set the PWM period and ON time (duty cycle).3. Necessary addressing and control inputs to get the PWM parameters.

Requirements:1. 16-bit count limit to set PWM period.2. 16-bit count limit to set ON time (duty cycle).3. Generate PWM waveform.

Specific problems:1. Design the PWM circuitry including the counter and the necessary storage

registers for storing PWM period and duty cycle settings.2. Determine the conditions to obtain 0 % (always low) and 100 % (always high) dutycycle at the PWM output.3. Make the interface with the microprocessor to get the PWM parameters.

Next step:1. Improve your design to make sure that changing PWM period and duty cyclesettings will not cause unwanted changes at the PWM output.2. Implement a method to obtain a better PWM time resolution that is equal to half ofthe clock period available at the input.

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6. Transition Detector You get:1. 10 MHz clock ( ClkIn )

2. A 1-bit signal inputRequirements:Generate two outputs as specified below:HCstable: Set to 1 if there are no transitions during high cycle of ClkIn for fourconsecutive clock cycles.LCstable: Set to 1 if there are no transitions during low cycle of ClkIn for fourconsecutive clock cycles.

Specific problems:1. Detect asynchronous transitions at the input.2. Make sure that all clock cycles are checked for transitions.3. Keep a history of transitions.

Next step:1. Extend the circuit to detect the transitions at eight parallel signal inputs during thehigh and low cycle of ClkIn .2. Generate a clock output according to the following conditions: ClkOut = ClkIn if the signal inputs are stable during low cycle of ClkIn . ClkOut = ~ClkIn if the signal inputs are stable during high cycle of ClkIn .

ClkOut = 0 if the signal inputs are not stable during high and low cycles of ClkIn .

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7. Interrupt ControllerThe interrupt mechanism of a computer allows temporary redirection of program

execution initiated by devices outside the processor. These are the steps involved in

serving an interrupt:1. An interrupt source requests service from the processor activating one of theinterrupt inputs of the interrupt controller.2. Interrupt controller sends an interrupt pulse to the processor when it is appropriateaccording to the previously determined controller options.3. Processor temporarily stops the regular program and executes an interruptservice routine (ISR) to serve the interrupt source.4. Processor clears the interrupt flag at the end of ISR to indicate that the interruptservice is completed and returns back to the regular program.

Interrupt controller utilizes flags to keep track of interrupt status. An interruptstatus flag is set high when the corresponding interrupt input is activated, and itremains high until it is cleared by the processor at the end of ISR. Level-sensitiveinterrupt flags should behave in a different way under the following conditions:1. If the interrupt input becomes inactive before the processor is invoked, then theflag is set back to 0 (processor skips the interrupt). However, if an output pulse hasalready been sent to the processor, then the status flag should remain high until it iscleared by the processor.2. If the interrupt input is still active when the interrupt flag is cleared, then anotherpulse is sent to invoke the processor again. Level-sensitive inputs can be driven bymultiple interrupt sources, and more than one source may request an interruptservice at the same time.

You get:1. Two interrupt inputs, Int0 and Int1 2. 10 MHz clock3. An 8-bit data input to get the interrupt controller options:

Bit-7,6: Int1En, Int0En: Enable interrupts at the input. Interrupt inputs are ignoredwhen these bits are 0.Bit-5,4: Int1Sns, Int0Sns: Select interrupt sensitivity type. 0=>level-sensitive,1=>edge-sensitive.Bit-3,2: Int1Pri, Int0Pri: Select interrupt priority. 0=>low, 1=>high.Bit-1,0: Int1Clr, Int0Clr: Setting these bits to 1 clears the corresponding interruptflag.

4. A one-cycle, active-high write enable pulse that indicates valid controller data atthe 8-bit data port.

Requirements: A one-cycle (100 ns) pulse is sent to the microprocessor at the correspondinginterrupt output when it is necessary to serve an interrupt. Generate two interruptoutputs Int0up and Int1up according to the following rules:1. A one-cycle (100 ns) pulse is generated at the corresponding interrupt output

according to the priority settings after an interrupt input is activated.

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2. If an interrupt is received while the other interrupt flag is still active, then the newinterrupt is served only if it has higher priority. Otherwise, the interrupt that arrivedlater will be ignored.

Specific problems:

1. Describe the circuitry to select interrupt sensitivity type.2. Describe the circuitry to generate two interrupt outputs, Int0up and Int1up , basedon the priority settings. Proper generation of interrupt outputs require makingdecisions instantaneously whenever an interrupt input is activated.

Next step:1. Add the necessary circuitry to make the Int1Clr and Int0Clr control bits "self-resetting" or "self-clearing" (microprocessor should not write to the control registertwice to set and reset Int1Clr or Int0Clr ).2. Correct the decision logic to handle the interrupts waiting to be served: If there isa pending interrupt, then the corresponding interrupt pulse is sent after the otherinterrupt flag is cleared. Decisions for interrupt outputs should be made whenever aninterrupt input is activated AND whenever an interrupt flag is cleared.3. Change the function of interrupt enable control bits, Int1En and Int0En as follows:Interrupt controller holds the interrupt outputs to the microprocessor while the enablecontrol bits are 0. If there are any pending interrupts, then they are sent to theprocessor after the interrupts are enabled.

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EE342 13 Projects