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EE3102 LAB REPORT EXP#1 FEB 2007 _______________________________________________________________________ Feedback Amplifiers Matt xxxxx Student ID : xxxxxxx 1/16/07 – 2/26/07 Abstract: Experiment one dealt with feedback amplifiers and the four negative feedback topologies associated with them. We investigated the -1-

EE3102 Experiment 1

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Formal Lab Report for University of Minnesota EE3102 Experiment 1

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Page 1: EE3102 Experiment 1

EE3102 LAB REPORT EXP#1 FEB 2007 _______________________________________________________________________

Feedback Amplifiers

Matt xxxxx Student ID : xxxxxxx

1/16/07 – 2/26/07

Abstract:

Experiment one dealt with feedback amplifiers and the four negative feedback topologies associated with them. We investigated the frequency response of the amplifiers using these feedback topologies and addressed the issues associated with feedback stability. Then additionally, positive feedback was employed to create a sinusoidal oscillator.

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Page 2: EE3102 Experiment 1

EE3102 LAB REPORT EXP#1 FEB 2007 _______________________________________________________________________

Introduction:

Feedback in circuit analysis is one of the most important concepts in electrical engineering, whether positive or negative. It can be used to create a wide variety of circuits, from amplifiers to oscillators. In this experiment we used the concept of feedback to investigate the frequency response of the four negative feedback topologies, as well as a positive feedback application, the Wein Bridge. We observed for each topology, the behavior of the circuit as it relates to various frequency and load changes. Additionally, we used many circuit concepts to study each topology in detail and to observe its effects given external changes.

Experiment

Open Loop Voltage Gain

The first section of the experiment asked us to determine and record the open loop voltage gain for three different 741 Op Amps. To do so we constructed the circuit shown in Figure 1.1.1 using the specified values.

-

+

U 2

LM741

3

26

7 14 5

R 12K

R 2

10K

R 3

10K

R 410

R 510K

0

V 115V dc 0

0

V 215V dc

V1Input

Vo

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EE3102 LAB REPORT EXP#1 FEB 2007 _______________________________________________________________________

Fig 1.1.1

Since the input voltage of the Op Amp is obtained by a simple voltage division we had to choose as accurate resistance values as possible. As it turns out these resistance values were provided to us so everyone would obtain as consistent of data as possible.

The procedure of finding the DC open loop voltage gain is identical for all three Op Amps. To do so we set

our input voltage to some arbitrary value, then proceeded to measure and . With these values

recorded we then changed the input voltage to a different voltage level and proceeded to find and

. Using these values we were then able to able to calculate the DC open loop voltage gain using the

following formula.

The collected values and calculations for the three Op Amps using the procedure outlined above are shown below.

For Op Amp 1:

For

For

For Op Amp 2:

For

For

For Op Amp 3:

For

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Page 4: EE3102 Experiment 1

EE3102 LAB REPORT EXP#1 FEB 2007 _______________________________________________________________________

For

From the analysis of the DC open loop voltage gain we are able to see that the gains for the three different Op Amps were 126000, 235000, and 165000 respectively.

The Four Topologies

Section 1.2 Series/Shunt

The second section of the experiment asked us to design for a no-load voltage gain of 15 for the respective Series/Shunt feedback circuit shown in figure 1.2.1. We were then to measure the midband voltage gain for various resistive loads. With this completed we determined the low frequency small-signal input resistance and found the dominant pole for the sinusoidal steady state response. Finally we determined the location of the dominant pole in the open loop response of the Op Amp itself.

-

+

U 1

U A 741

3

26

7 14 5

R 114K

R 21K

R 3

R

R 4Load

0

00

V 215V dc

V 315V dc

0

0

V2V1Vo

V 41V ac0V dc

Fig 1.2.1

In order to determine the necessary values of the resistors to achieve a gain of 15 we used the following two port network equivalent shown in figure 1.2.2.

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Page 5: EE3102 Experiment 1

EE3102 LAB REPORT EXP#1 FEB 2007 _______________________________________________________________________

R 1R

R 2

R++

- -

V1

I2I1

V2

Fig 1.2.2

Proceeding we know the gain for a series/shunt amplifier is:

Here we assumed

Therefore ,

Where

Solving for beta yields:

Now using H parameters for our two port circuit we were able to determine the resistor values as follows.

Choosing arbitrarily and solving for yielded .

With the circuit design completed and the circuit built we were able to determine the voltage gain as a function of various resistive loads.

Gain vs Load resistance

Load vi(V) Vo(V) Gain0 0.505 7.69 15.16810 0.502 0.2 0.40950 0.499 1.036 2.076100 0.498 2.06 4.37500 0.487 7.45 15.291000 0.494 7.58 15.3510000 0.488 7.46 15.413100000 0.488 7.46 15.4151000000 0.494 7.56 15.3

Fig 1.2.3

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Page 6: EE3102 Experiment 1

EE3102 LAB REPORT EXP#1 FEB 2007 _______________________________________________________________________

A plot of Gain vs. Load Resistance is shown below.

Fig 1.2.4

Next we found the low frequency small signal input resistance and the location of the dominant pole of the sinusoidal steady state response.

To determine this we placed a 100k ohm resister between the input and V+ so we could determine the current flowing into the terminal as shown in figure 1.2.5.

-

+

U 1

U A 741

3

26

7 14 5

R 114K

R 21K

R 3

100k

0

0

V 215V dc

V 315V dc

0

0

V2V1

V 41V ac0V dc

Vo

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Page 7: EE3102 Experiment 1

EE3102 LAB REPORT EXP#1 FEB 2007 _______________________________________________________________________

Fig 1.2.5

In order to determine the current flowing into V+ we measured the voltage values at V1, V2 and then used Ohm’s Law to compute the current.

Then using Ohm’s Law.

With this current found we could then calculate .

To determine the dominant pole we needed to find the closed loop gain for the circuit. We accomplished this by collecting following data:

Gain vs Frequency

Freq (Hz) Vi (V) Vo (V) Gain500 0.5 6.94 13.881000 0.5 7 14.122000 0.5 7.7 15.35000 0.5 8 1610000 0.5 7.8 15.615000 0.5 7.8 15.620000 0.5 7.7 15.425000 0.48 7.3 15.230000 0.48 7 14.5840000 0.48 6.6 13.7550000 0.48 5.8 12.0857000 0.48 5 10.3560000 0.48 4.5 10.4170000 0.48 5.5 9.375

Fig 1.2.6

A plot of Gain vs. Frequency is shown below.

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Page 8: EE3102 Experiment 1

EE3102 LAB REPORT EXP#1 FEB 2007 _______________________________________________________________________

Fig 1.2.7

Using this data we are able to see that our midband gain is about 15.3V/V. Using this we could then calculate our closed loop gain.

This can be seen to occur at about 57 KHz.

Thus

With this information we were than able to calculate our dominant pole location.

Since Op Amp 1 was used for this experiment, was equal to 126000.

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Page 9: EE3102 Experiment 1

EE3102 LAB REPORT EXP#1 FEB 2007 _______________________________________________________________________

Section 1.3 Shunt/Series

The third section of the experiment asked us to design for a midband short circuit gain of 100 for the respective Series/Shunt feedback circuit shown in figure 1.3.1. Using this circuit we were to measure the midband gain for various resistive loads.

-

+

U 1

U A 741

3

26

7 14 5

R 1Load

R 2101

0

0

V 215V dc

V 315V dc

0

0

VAV2

V 41V ac0V dc

0

R 1

10K

V2V1

VB

R 4

1M

Fig 1.3.1

In this circuit we approximated the necessary current source as a voltage source in series with a large resistor. We used a 1M ohm resistor that was chosen arbitrarily.

Once again we used two port circuit analyses to determine the necessary resistor values to obtain a midband short circuit gain of 100 (See figure 1.3.1 for the two port network.).

R 2R

R 1

R++

- -

V1 V2

I2I1

Fig 1.3.2

Proceeding we know the gain for a Shunt/Series amplifier is:

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Page 10: EE3102 Experiment 1

EE3102 LAB REPORT EXP#1 FEB 2007 _______________________________________________________________________

Here we assumed

Therefore ,

Where

Solving for beta yields:

Now using G parameters for our two port circuit we were able to determine the resistor values as follows.

Choosing arbitrarily and solving for yielded .

With the circuit design completed and the circuit built we were able to determine the current gain as a function of various resistive loads as follows:

Gain vs Load resistance

V1 (V) V2(mV) Va (mV) V (mV) Rl (Ohms) I (uA) Io (uA) Gain2.31 300 300 300m 0 1.827 0 02.31 300 300 340m 220 1.827 181.8 99.52.31 300 300 410m 500 1.827 220 120.42.31 280 280 530m 1000 1.845 250 135.52.31 270 270 780m 2000 1.855 255 137.52.31 250 250 1.45 5100 1.872 235 125.62.31 250 250 2.52 10000 1.872 227 121.22.31 250 250 4.69 20000 1.872 222 1182.5 220 220 19.1 100000 2.072 188.8 91.08

Fig 1.3.3

A plot of Current Gain vs. Load Resistance is shown below.

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Page 11: EE3102 Experiment 1

EE3102 LAB REPORT EXP#1 FEB 2007 _______________________________________________________________________

Fig 1.3.4

Viewing the table and graph we are able to see that the gain is slightly lower for very low and high frequency values. This is acceptable and follows closely with what is expected in circuit theory.

Section 1.4 Series/Series

The fourth section of the experiment asked us to design for a midband short circuit transconductance of 1ma/V for the respective Series/Series feedback circuit shown in figure 1.4.1 and to measure the midband transconductance for various resistive loads.

-

+

U 1

U A 741

3

26

7 14 5

R 1Load

R 21K

R 3

R

0

0

V 215V dc

V 315V dc

0

0

VoV2V1

V 41V ac0V dc

Vl

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Page 12: EE3102 Experiment 1

EE3102 LAB REPORT EXP#1 FEB 2007 _______________________________________________________________________

Fig 1.4.1

Once again we used two port circuit analysis to determine the necessary resistor values to obtain a midband short circuit transconductance of 1mA/V (See figure 1.4.2 for two port network.).

R 1R

++

--

V1

I2I1

V2

Fig 1.4.2

Proceeding we know the gain for a shunt/series amplifier is:

Solving for Is

Now using Z parameters for our two port circuit we were able to determine the resistor values as follows.

,

With the circuit design completed and circuit built we were able to determine the transconductance as a function load resistance as follows:

Transconductance vs Load

Vs (V) Vl (V) Vo (V) Rl (Ohms) Io (mA)Gmf (mA/V)

1 1.11 1.11 0 0 01 1.11 1.34 220 1.04 0.962

1.03 1.11 1.61 500 1 0.9711 1.11 2.1 1000 0.99 0.99

1.02 1.11 3.1 2000 0.995 0.975

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EE3102 LAB REPORT EXP#1 FEB 2007 _______________________________________________________________________

1.02 1.11 6.07 5100 0.973 0.9541 1.11 11.3 10000 1.019 1.02

1.02 1.1 20.6 20000 9.75 0.9520.3 0.325 22.2 100000 0.219 0.731

Fig 1.4.3

To determine Io and gmf we used the following.

These values can be seen in figure 1.4.3.

A plot of Transconductance vs. Load Resistance is shown below.

Fig 1.4.4

Form the table and graph we are able to see that the gmf remained relatively constant until became

very large. .

Section 1.5 Shunt/Shunt

The fifth section of the experiment asked us to design for a midband open circuit gain of 100K for the respective Shunt/Shunt feedback circuit shown in figure 1.5.1 and then to measure the midband transresistance for various resistive loads.

In this circuit we once again approximated the necessary current source as a voltage source in series with a large resistor. We used a 1M ohm resistor that was chosen arbitrarily.

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Page 14: EE3102 Experiment 1

EE3102 LAB REPORT EXP#1 FEB 2007 _______________________________________________________________________

-

+

U 1

U A 741

3

26

7 14 5

R 1Load

0 0

V 215V dc

V 315V dc

0

0

VoV2

V 41V ac0V dc

0

R 3

100K

VnV1

R 4

1M

Fig 1.5.1

We then proceeded to determine the necessary value of .

With the circuit design completed and the circuit built we were able to determine the transresistance as a function of various resistive loads as follows:

Transresistance vs Load

V1 (V) Vn (V) Vo (V) Is (A) Rl (Ohms) Rf (Ohms)2.25 9m 0.2171 2u 0 96876.42.207 8.2m 0.2171 2u 10 98690.22.201 5m 0.2172 2u 50 98907.12.201 5m 0.2174 2u 100 98998.22.203 4m 0.2174 2u 1000 98863.12.2 2.1m 0.2174 2u 10000 98912.62.2 4m 0.2176 2u 100000 99089.3

Fig 1.5.2

Here we calculated and using the following. Where .

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Page 15: EE3102 Experiment 1

EE3102 LAB REPORT EXP#1 FEB 2007 _______________________________________________________________________

These values are then displayed in figure 1.5.2

A plot of Transresistance vs., Load Resistance is shown below.

Fig 1.5.3

From the table and graph we are able to see that the transresistance vs. load remains relatively constant and is indeed consistent with results form circuit theory.

Section 1.6 Frequency Response

The sixth section of the experiment asked us to take two Series/Shunt amplifiers and cascade to provide an overall feedback to make the overall voltage gain about 15 at the midband. See figure 1.6.1.

This was very similar to the design process of section two only here we cascaded two Series/Shunt amplifiers together. Here the specified gain of the individual amplifiers was to be 15. This meant that the same resistance values we used for the Series/Shunt amplifier in part two could be used here as well.

Additionally, the overall gain was to also be 15. This meant that the same resistor values could be used for the overall gain control as the individual stages. Thus, each stage of this amplifier was to have the same gain.

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Page 16: EE3102 Experiment 1

EE3102 LAB REPORT EXP#1 FEB 2007 _______________________________________________________________________

-

+

U 1

U A 741

3

26

7 14 5

-

+

U 2

U A 741

3

26

7 14 5

R 11K

R 514K

R 61K

R 4

1K

R 2

14K

0

0

R 3

14K

V 115V dc

V 215V dc

V 315V dc V 4

15V dc0 0

00

Vo

Vi

Fig 1.6.1

Once we had the circuit constructed we could then investigate the voltage gain vs. frequency relationship.

Gain vs Frequency

Frequency (Hz) Vi (V) Vo (V) Gain1000 0.0455 0.72 15.825000 0.0461 0.732 15.8710000 0.0461 0.73 15.8325000 0.0471 0.729 15.4750000 0.0477 0.745 15.62100000 0.0488 0.837 17.15125000 0.0495 0.89 17.98125000 0.0498 0.904 18.15140000 0.0499 0.981 19.66160000 0.0512 1.09 21.29170000 0.0518 1.189 22.99180000 0.0518 1.308 25.25190000 0.0527 1.423 27.6200000 0.0533 1.428 26.79210000 0.0535 1.376 25.72220000 0.0539 1.31 24.3240000 0.0529 1.17 22.12

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EE3102 LAB REPORT EXP#1 FEB 2007 _______________________________________________________________________

260000 0.0525 1.029 19.6280000 0.0504 0.91 18.05300000 0.0492 0.8 16.26320000 0.0482 0.705 14.62340000 0.0471 0.613 13.01400000 0.0445 0.415 9.33500000 0.0425 0.239 5.63

Fig 1.6.2

A plot of Voltage Gain vs. Frequency is shown below.

Fig 1.6.3

In addition to investigating the overall feedback of the amplifier we were also to determine the quality factor for the circuit. This was done by determining the bandwidth and resonance frequencies and then solving for Q.

The final part of this section asked us to observe the output, given a square wave input, as a function of frequency. This was quite simple and the results were as expected. We observed that as frequency increased the output transformed from a square wave into a sine wave.

Stability

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Page 18: EE3102 Experiment 1

EE3102 LAB REPORT EXP#1 FEB 2007 _______________________________________________________________________

The seventh section of the experiment asked us to place three Series/Shunt amplifiers in series and then to provide an overall feedback to generate an overall midband voltage gain variable from 10 to 100. We were to then investigate the stability of the amplifier as a function of the gain.

To accomplish this we had to make calculations similar to those in part seven of the experiment, only now we had three amplifiers in series instead of two.

Here, once again, the gains of the individual stages remained the same as two.

We were told to design for a midband variable voltage gain from 10 to 100. To accomplish this we placed a potentiometer in place of resistor R9 so we could adjust the feedback of the circuit and thus the gain. The calculations for this were actually quite simple.

Letting and solving for the necessary sized potentiometer yielded

The resultant circuit design can be seen in figure 1.7.1.-

+

U 1

U A 741

3

26

7 14 5 -

+

U 2

U A 741

3

26

7 14 5

R 11K

R 41K

R 2

14K

00

R 3

14K

V 115V dc

V 215V dc

V 315V dc

V 415V dc 0

0

0 0

Vi

-

+

U 3

U A 741

3

26

7 14 5

V 515V dc

V 615V dc

R 7R

R 8100K

R 91K

R 10

14K

00

0

Vo

Fig 1.7.1

The goal of this part of the experiment was to ultimately investigate the stability of the cascaded amplifiers. When a square wave was inputted to the circuit the output was clearly unstable. It could be seen that the output was not a perfect square wave and that continuous ringing was occurring. This instability was indeed a problem and needed to be eliminated in order for the circuit to have any practical use.

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Page 19: EE3102 Experiment 1

EE3102 LAB REPORT EXP#1 FEB 2007 _______________________________________________________________________

Compensation

The eighth section of the experiment dealt with dominant pole compensation and asked us to design the circuit to be stabile with a phase margin between 45 and 90 degrees.

Here we needed to determine where to place the dominant pole. To accomplish this we determined the following values at resonance.

34 KHz, Av=29,

Next we found the 45 degree phase margin and determined the same information as previous.124.83 KHz, Av 7.9,

Now using this information we could plug into the following equation and solve for the dominant pole .

Plugging in the appropriate values and solving for yields.

With the dominant pole found we could then calculate our capacitor and resistor values necessary to give us our dominant pole compensation.

Choosing arbitrarily we can then solve for R.

With the appropriate values determined we were then able to insert the new pole between Op Amps two and three as shown in figure 1.8.1.

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Page 20: EE3102 Experiment 1

EE3102 LAB REPORT EXP#1 FEB 2007 _______________________________________________________________________

Fig 1.8.1

With the dominant pole compensation completed and inserted into the circuit we were able to determine the bandwidth of our new compensated amplifier.

Gain & Phase vs Frequency

Frequency (Hz) Vi (mV) Vo (V) GainPhase (degrees)

1 256 25.3 98.8 010 256 25.3 98.8 1100 256 25.3 98.8 2500 256 25.3 98.8 31000 256 25.3 98.8 62000 256 25.3 98.8 183000 256 25.3 98.8 225000 256 25.3 95.8 3510000 256 22.1 86.31 5815000 250 14.4 56.25 10030000 250 8 31 133

Fig 1.8.2

Plots of Frequency vs. Gain and Phase Shift are shown below.

-

+

U1

UA741

3

26

7 14 5 -

+

U2

UA741

3

26

7 14 5

R11K

R41K

R2

14K

00

R3

14K

V115Vdc

V215Vdc

V315Vdc

V415Vdc

0

0

0

0

Vi

-

+

U3

UA741

3

26

7 14 5

V515Vdc

V615Vdc

R7R

R8100K

R91K

R10

14K

0

0

0

VoR11

11 C14.7uF

0

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Page 21: EE3102 Experiment 1

EE3102 LAB REPORT EXP#1 FEB 2007 _______________________________________________________________________

Fig 1.8.3

Fig 1.8.4

Viewing the graphs we can easily see that the amplifier with compensation was indeed stable while maintaining good bandwidth.

Oscillators

The final circuit was to design and construct a 500 Hz Sinusoidal oscillator (see Figure 1.9.1). This was to be powered by 15 volt supplies and have an output of 5V. With these design criteria in mind we designed and built the following circuit:

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Page 22: EE3102 Experiment 1

EE3102 LAB REPORT EXP#1 FEB 2007 _______________________________________________________________________

Fig 1.9.1

To design for 500 Hz we made the following calculations.

Choosing C=10nF

Therefore the values used were as follows.

To provide the stabilization we added the two diodes in parallel with a 10K resistor. The last requirement was to have an output amplitude of 5 V. This was achieved by placing a 10K potentiometer in the circuit as shown in figure 1.9.1 to control the feedback and therefore the gain of the circuit. The potentiometer was then adjusted until the circuit was operating at the desired 5 V.

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-

+

U1

UA741

3

26

7 14 5

10KPOT

D1

D2

C1

10nF

C2

10nF

R2 10K

R3

32KR4

32K

Vo

0

0

V115Vdc

V215Vdc

0

0

Page 23: EE3102 Experiment 1

EE3102 LAB REPORT EXP#1 FEB 2007 _______________________________________________________________________

The actual frequency of the Wein Bridge was not exactly 500 Hz, but rather 522 Hz. This was due largely to the tolerances of the parts used and the inherent mismatches that resulted. This was the only flaw with the Wein Bridge the circuit performed as expected producing a near perfect sine wave.

Conclusion: Throughout this experiment we investigated various forms of feedback and its effects. We observed, that all forms of negative feedback, were relatively unaffected by changes in load resistance. In other words the gains for the different amplifiers remained constant. This can be seen through the various plots of Gain vs. Load Resistance. Next we studied cascaded amplifiers. Here we observed gain peaking in a double cascaded Series/Shunt amplifier and demonstrated that it has a very low quality factor of 1.2. Next we studied the stability of triple cascaded Series/Shunt amplifiers. Here we observed that the amplifier was highly unstable, thus requiring dominant pole compensation to stabilize the amplifier. Finally, we designed and constructed a Wein Bridge sinusoidal oscillator. This was an application of positive feedback where as all of the previous implementations had been negative feedback. Overall the concept of feedback for differential amplifiers is crucial in designing many of today’s electronics. Without it many designs would not be possible or would require far more complicated and expensive circuitry. Thus, this experiment hereby demonstrated the functionality and effectiveness of the feedback network in circuit design.

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