EE3032 Introduction to VLSI Design

EE3032 Introduction to VLSI Design

Jin-Fu Li

Department of Electrical Engineering National Central University

Jhongli, Taiwan

a b c d z

A

B

C

C=AxB

Outline

Chapter 1: Introduction to CMOS Circuits

Chapter 2: MOS Transistor Theory

Chapter 3: Fabrication of CMOS Integrated Circuits

Chapter 4: Electrical Characteristics of CMOS Circuits

Chapter 5: Elements of Physical Design

Chapter 6: Combinational Circuit Design

Chapter 7: Sequential Circuit Design

Chapter 8: Introduction to 3D Integration using TSV

Appendix

Homeworks

1

Chapter 1 Chapter 1 Introduction to CMOS Circuit Introduction to CMOS Circuit

DesignDesigngg

Jin-Fu LiAdvanced Reliable Systems (ARES) Lab.y m ( E ) L .

Department of Electrical EngineeringNational Central University

Jhongli, Taiwan

IntroductionMOS Transistor SwitchesCMOS Logic

Outline

CMOS LogicCircuit and System Representation

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2

2

Binary Counter

Present state Next state A

a

b

a b A B0 0 0 10 1 1 01 0 1 11 1 0 0

B


A = a’b + ab’B = a’b’ + ab’

CKCLR

Source: Prof. V. D. Agrawal

1-bit Multiplier

A

B

C


B

C=AxB

3

Switch: MOSFETMOSFETs are basic electronic devices used to direct and control logic signals in IC design

MOSFET: Metal-Oxide-Semiconductor Field-Effect TransistorN-type MOS (NMOS) and P-type MOS (PMOS) Voltage-controlled switches

A MOSFET has four terminals: gate, source, drain, and substrate (body)

l


Complementary MOS (CMOS)Using two types of MOSFETs to create logic networksNMOS & PMOS

Silicon Lattice and Dopant AtomsPure silicon consists of a 3D lattice of atoms

Silicon is a Group IV element and it forms covalent bonds with four adjacent atomsIt i d t

Si SiSi Si SiSi - Si SiSi+

It is a poor conductorN-type (P-type) semiconductor

By introducing small amounts of Group V-As (Group III-B) into the silicon lattice


Si SiSi

Si SiSi

+As SiSi

Si SiSi

-B SiSi

Si SiSi

+

Lattice of pure Silicon

Lattice of N-type Semiconductor

Lattice of P-type Semiconductor

4

P-N JunctionsA junction between p-type and n-type semiconductor forms a diode.Current flows only in one directiony

p-type n-type

anode cathode


NMOS TransistorFour terminals: gate, source, drain, bodyGate–oxide–body stack looks like a capacitor

Gate and body are conductorsSiO2 (oxide) is a very good insulatorCalled metal–oxide–semiconductor (MOS) capacitorEven though gate is no longer made of metal

GateSource Drain

SiO2

Polysilicon


n+

p bulk Si

n+

5

NMOS OperationsBody is commonly tied to ground (0 V)When the gate is at a low voltage:

P-type body is at low voltageyp y gSource-body and drain-body diodes are OFFNo current flows, transistor is OFF

GateSource Drain

SiO2

Polysilicon


n+

p bulk Si

n+D

0

S

NMOS Operations (Cont.)When the gate is at a high voltage:

Positive charge on gate of MOS capacitorNegative charge attracted to bodyInverts a channel under gate to n-typeNow current can flow through n-type silicon from source through channel to drain, transistor is ON

GateSource Drain

SiO

Polysilicon


n+

p bulk Si

SiO2

n+D

1

S

6

PMOS OperationsSimilar, but doping and voltages reversed

Body tied to high voltage (VDD)Gate low: transistor ONGate high: transistor OFFBubble indicates inverted behavior

SiO2

GateSource DrainPolysilicon


n bulk Si

p+ p+

Threshold VoltageEvery MOS transistor has a characterizing parameter called the threshold voltage VT

The specific value of VT is established during p T gthe manufacturing process Threshold voltage of an NMOS and a PMOS

VDD

VADrainVDD

VA

NMOS PMOS

VGSp

Source+ VDD


VA=1Mn On

VA=0 Mn Off

VTn

0

Logic translation

VA

VGSn

Mn

Source

Gate-source voltage

Gate+

-

VA=1Mp Off

VA=0 Mp On

VDD-|VTp|

0

Logic translation

VA

Drain

Mp

Gate-source voltage

Gate-

7

MOS Transistor is Like a Tap…


Source: Prof. Banerjee, ECE, UCSB

MOS SwitchesNMOS symbol and characteristics

5v

05v

05v-Vth

Vth

PMOS symbol and characteristics0v

0v5v

0v 0v th

Vth

Vth

5v


8

CMOS SwitchA complementary CMOS switch

Transmission gate

C

5

a

s

b a

s

b a

s

b

-s -s

50v

Symbols


5v

0v

5v0v

5v

Characteristics

CMOS Logic-InverterThe NOT or INVERT function is often considered the simplest Boolean operation

F(x)=NOT(x)=x’ Vdd

Vin Vout Vin Vout

Vdd Vdd Vdd


0 1 1 0 Vdd/2 Indeterminatelogic level

9

Combinational LogicSerial structure

S1

S1=0S2=0

S1=0S2=1

S1=1S2=0

S1=1S2=1a

S10 1

S1

S2

S1=0S2=0

S1=0S2=1

S1=1S2=0

S1=1S2=1

b

a

S20

1

S10 1

a!=b a!=b

a!=b a=b


S1

S2

b

S20

1

0 1

a=b a!=b

a!=b a!=b

Combinational LogicParallel structure

S1=0S2=0

S1=0S2=1

S1=1S2=0

S1=1S2=1a S1

S1 S2

S1=0S2=0

S1=0S2=1

S1=1S2=0

S1=1S2=1

b

a

S20

1

0 1

S10 1

a!=b a=b

a=b a=b


S1 S2

b

S20

1

a=b a=b

a=b a!=b

10

NAND Gate

A

B

Output A

B1

0

10

1 1

1 0


AB

Output

NOR Gate

A

B

Output

A

B1

0

10

1 0

0 0


AB

Output

11

Compound Gate))()(( CDABF +=

A B

A

FF

C D

C

AB

CD


B D

Structured Logic DesignCMOS logic gates are intrinsically inverting

The output always produces a NOT operation acting on the input variables

For example, the inverter shown below illustrates this property

VDD

f 01

1


f=0a=1

0

12

Structured Logic DesignThe inverting nature of CMOS logic circuits allows us to construct logic circuits for AOI and OAI expressions using a structured approachAOI logic function

Implements the operations in the order AND then OR then NOTE.g.,

l fdcbadcbag ..),,,( +=


OAI logic functionImplements the operations in the order OR then AND then NOTE.g., )()(),,,( dcbadcbag +⋅+=

Structured Logic DesignBehaviors of nMOS and pMOS groups

Parallel-connected nMOS OR-NOT operations

Parallel-connected pMOSAND-NOT operations

Series-connected nMOSAND-NOT operations

Series-connected pMOS OR-NOT operations


p

Consequently, wired groups of nMOS and pMOS are logical duals of another

13

Dual PropertyIf an NMOS group yields a function of the form

)( cbag +⋅=

then an identically wired PMOS array gives the dual function

where the AND and OR operations have been

)( cbaG ⋅+=


pinterchangedThis is an interesting property of NMOS-PMOS logic that can be exploited in some CMOS designs

An Example of Structured Design)( dcbaX +⋅+=

VDD

a

b

Xb

d

c

Group 1 Group 2

Group 3


adc

14

An Example of XOR GateBoolean equation of the two input XOR gate

, this is not in AOI formBut, , this is in AOI form

bababa ⋅+⋅=⊕bababa ⋅+⋅=⊕

Therefore, babababa ⋅+⋅=⊕=⊕ )(

VDDa

b

b

aba ⊕

VDDa

b a

b

ba ⊕

• •

• •

••

••


a

b

a

b

a

b b

a

XOR Gate XNOR Gate

Multiplexer

AB

Y10

11100100

ABCD

Y

A

B

Y

B

S

-SS

0

Y

A

B

C

S1 S0


-S D

S1 -S1 S0 -S0

15

Static CMOS SummaryIn static circuits at every point in time (except when switching), the output is connected to either Vdd or Gnd through a low resistance path

F i f ( i t ) i 2 ( N t d PFan-in of n (or n inputs) requires 2n (n N-type and n P-type) devices

Non-ratioed logic: gates operate independent of PMOS or NMOS sizesNo path ever exists between Vdd and Gnd: low static power


pFully-restored logic (NMOS passes “0” only and PMOS passes “1” onlyGates must be inverting

Circuit and System RepresentationsBehavioral representation

Functional, high levelFor documentation, simulation, verification

Structural representationSystem level – CPU, RAM, I/OFunctional level – ALU, Multiplier, AdderGate level – AND, OR, XORCircuit level – Transistors, R, L, C


For design & simulationPhysical representation

For fabrication

16

Behavior RepresentationA one-bit full adder (Verilog)

module fadder(sum,cout,a,b,ci);output sum cout;output sum, cout;input a, b, ci;reg sum, cout;

always @(a or b or ci) beginsum = a^b^ci;

ci

a b

cout

sum

fadder


cout = (a&b)|(b&ci)|(ci&a); endendmodule

Structure RepresentationA four-bit full adder (Verilog)

module adder4(s,c4,a,b,ci);output[3:0] sum;output c4;

a b

output c4;input[3:0] a, b;input ci;reg[3:0] s;reg c4;wire[2:0] co;

fadder a0(s[0],co[0],a[0],b[0],ci);fadder a1(s[1] co[1] a[1] b[1] co[0]);

ci

a[0] b[0]

s[0]

a0 a3a1 a2

a[1] b[1] a[2] b[2] a[3] b[3]

s[1] s[2] s3]

co[0] co[1] co[2]

s adder4


fadder a1(s[1],co[1],a[1],b[1],co[0]);fadder a2(s[2],co[2],a[2],b[2],co[1]);fadder a3(s[3],c4,a[3],b[3],co[2]);

endmodule

17

Physical RepresentationLayout of a 4-bit NAND gate

Vdd Vdd

in1 in2 in3 in4

in1

in2

in3

Out

Out


in4

in1 in2 in3 in4

Gnd

Design Flow for a VLSI Chip

Specification

Function

Behavioral Design

Structural Design

Function

Function

FunctionTiming


Physical Design

TimingPower

1

Chapter 2 Chapter 2 MOS Transistor TheoryMOS Transistor Theoryyy

Jin-Fu LiAd d R li bl S t (ARES) L bAdvanced Reliable Systems (ARES) Lab.


Jhongli, Taiwan

IntroductionI-V Characteristics of MOS TransistorsNonideal I-V Effects

Outline

Nonideal I V EffectsPass TransistorSummary


2

MOS TransistorMOS transistors conduct electrical current by using an applied voltage to move charge from the sourceside to the drain side of the deviceAn MOS transistor is a majority-carrier device m j yIn an n-type MOS transistor, the majority carriers are electronsIn a p-type MOS transistor, the majority carriers are holesThreshold voltage

It is defined as the voltage at which an MOS device begins


It is defined as the voltage at which an MOS device begins to conduct (“turn on”)

MOS transistor symbols

NMOS PMOS

MOS TransistorSo far, we have treated transistors as ideal switchesAn ON transistor passes a finite amount of current

Depends on terminal voltagesD i t lt (I V) l ti shi sDerive current-voltage (I-V) relationships

Transistor gate, source, drain all have capacitanceI = C (ΔV/Δt) -> Δt = (C/I) ΔVCapacitance and current determine speed

The structure of a MOS transistor is symmetricTerminals of source and drain of a MOS can be exchanged


3

Vg & Channel for P-Type Body

Vg<0

Accumulation mode Polysilicon GateSilicon Dioxide InsulatorP-type Body

0<Vg<Vt

Depletion modeDepletion Region


Vg>Vt

Inversion modeInversion RegionDepletion Region

NMOS Transistor in Cutoff Mode

Vgs=0 Vgd

s dg

n+n+

p-type body

Cutoff regionThe source and drain have free electrons


he source and dra n have free electronsThe body has free holes but no free electronsThe junction between the body and the source or

drain are reverse-biased, so almost zero current flows

4

NMOS Transistor in Linear ModeVgs>Vt Vgd=Vgs

s dg

s dg

n+n+n+n+

Vgs>Vgd>VtVgs>Vt

Ids

p-type body p-type body

n+n+n+n+

Vds=0 0<Vds<Vgs-Vt

Linear regionA.k.a. resistive, nonsaturated, or unsaturated regionIf Vgd=Vgs, then Vds=Vgs-Vgd=0 and there is no electrical field


g g g g

tending to push current from drain to sourceIf Vgs>Vgd>Vt, then 0<Vds<Vgs-Vt and there is a small positive

potential Vds is applied to the drain , current Ids flows through the channel from drain to source

The current increases with both the drain and gate voltage

NMOS Transistor in Saturation Mode

s dg

n+n+

Vgd<VtVgs>Vt

Ids

p-type body

nn

Vds>Vgs-Vt

Saturation regionThe Vds becomes sufficiently large that Vgd<Vt, the channel is no longer

inverted near the drain and becomes pinched offHowever conduction is still brought about by the drift of electrons


However, conduction is still brought about by the drift of electrons under the influence of the positive drain voltage

As electrons reach the end of the channel, they are injected into the depletion region near the drain and accelerated toward the drain

The current Ids is controlled by the gate voltage and ceases to be influenced by the drain

5

NMOS TransistorIn summary, the NMOS transistor has three modes of operations

If Vgs<Vt, the transistor is cutoff and no current gflowsIf Vgs>Vt and Vds is small, the transistor acts as a linear resistor in which the current flow is proportional to Vds

If Vgs>Vt and Vds is large, the transistor acts as a current source in which the current flow becomes


independent of Vds

The PMOS transistor operates in just the opposite fashion

I-V Characteristics of MOS In linear and saturation regions, the gate attracts carriers to form a channelThe carriers drift from source to drain at a rate proportional to the electric field between these proportional to the electric field between these regionsMOS structure looks like parallel plate capacitor while operating in inversion

Gate–oxide–channel Vg


N+ N+

6

Channel ChargeVg

C

Vs Vd

Qchannel=Cg(Vgc-Vt) , where Cg is the capacitance of the gate to the channel and Vgc-Vt is the amount of voltage

n+ n+

Cg

Vc


g

attracting charge to the channel beyond the minimal required to invert from p to n

Vc=(Vs+Vd)/2=Vs+Vds/2Therefore, Vgc=(Vgs+Vgd)/2=Vgs-Vds/2

Gate Capacitance (Cg)Transistor dimensions

W

tOX

Gate

The gate capacitance is

N+ N+

L

Gate

WLC ε


oxoxg t

C ε=

7

Carrier VelocityCharge is carried by e-Carrier velocity v proportional to lateral E-field between source and drainv = μE, where μ is called mobilityE = Vds/LTime for carrier to cross channel:

t = L / v


NMOS Linear I-VNow we know

How much charge Qchannel is in the channelHow much time t each carrier takes to cross

channel

ox 2

2

ds

dsgs t ds

dsgs t ds

QIt

W VC V V VL

VV V V

μ

β

=

⎛ ⎞= − −⎜ ⎟⎝ ⎠

⎛ ⎞= − −⎜ ⎟⎝ ⎠


Where

2gs t dsβ ⎜ ⎟⎝ ⎠

ox = WCL

β μ

8

NMOS Saturation I-VIf Vgd<Vt, channel pinches off near drain

When Vds>Vdsat = Vgs–Vt

Now drain voltage no longer increases current

( )2

2

2

dsatds gs t dsat

gs t

VI V V V

V V

β

β

⎛ ⎞= − −⎜ ⎟⎝ ⎠

= −


Summary of NMOS I-V Characteristics

cutoff

linear

0

2

gs t

dsds gs t ds ds dsat

V VVI V V V V Vβ

⎧⎪ <⎪⎪ ⎛ ⎞= − − <⎜ ⎟⎨ ⎝ ⎠⎪

( )2saturatio

2ngs t ds dsatV V V Vβ

⎪⎪

− >⎪⎩

1.5

2

2.5

mA)

Vgs = 5

Vgs = 4

Vds=Vgs-Vt

Linear Saturation


0 1 2 3 4 50

0.5

1

Vds

I ds (m

Vgs = 3

Vgs = 2Vgs = 1

9

ExampleAssume that the parameters of a technology are as follows

tox = 100 Åμ = 350 cm2/V*s

2

2.5Vgs = 5

μ 350 cm /V sVt = 0.7 V

Plot Ids vs. VdsVgs = 0, 1, 2, 3, 4, 5Use W/L = 4/2 λ

0 1 2 3 4 50

0.5

1

1.5

VdsI ds

(mA) Vgs = 4

Vgs = 3

Vgs = 2Vgs = 1


( )14

28

3.9 8.85 10350 120 /100 10ox

W W WC A VL L L

β μ μ−

−

⎛ ⎞• ⋅ ⎛ ⎞= = =⎜ ⎟⎜ ⎟⋅ ⎝ ⎠⎝ ⎠

Nonideal I-V EffectsNonideal I-V effects

Velocity saturation, mobility degradation, channel length modulation, subthreshold conduction, body effect, etc.

The saturation current increases less than quadratically i h i i V Thi i d b ffwith increasing Vgs. This is caused by two effects:

Velocity saturationMobility degradation

Velocity saturationAt high lateral field strengths (Vds/L), carrier velocity ceases to increase linearly with field strengthR lt i l I th t d t hi h V


Result in lower Ids than expected at high Vds

Mobility degradationAt high vertical field strengths (Vgs/tox), the carriers scatter more oftenAlso lead to less current than expected at high Vgs

10

Ideally, Ids is independent of Vds for a transistor in saturation, making the transistor a perfect current source

Channel Length Modulation

2)(21

tgsoxds VVCL

WI −= μ

Actually, the width Ld of the depletion region between the channel and drain is increased with Vdb. To avoid introducing the body voltage into our calculations, assume the source voltage is close to the body voltage so Vdb~Vds

Thus the effective channel length is shorten to Leff=L-Ld

2 L


Therefore, the Ids can be expressed as

Assume that , then LLVVC

LWVVC

LWI

dtgsoxtgsox

effds

−−=−=

1

1)(21)(

21 22 μμ

2 21 1( ) (1 ) ( ) (1 )2 2

dds ox gs t ox gs t ds

LW WI C V V C V V VL L L

μ μ λ= − + = − +

1<<LL d

The parameter is an empirical channel length modulation factor As channel length gets shorter, the effect of the channel length modulation becomes relatively more

Channel Length Modulationλ

channel length modulation becomes relatively more important

Hence is inversely dependent on channel lengthThis channel length modulation model is a gross oversimplification of nonlinear behavior and is more useful for conceptual understanding than for accurate device modeling

λ


device modelingChannel length modulation is very important to analog designers because it reduces the gain of amplifiers. It is generally unimportant for qualitatively understanding the behavior of digital circuits

11

Body EffectBody effect

Vt is a function of voltage between source and substrate

0 9

0.6

0.65

0.7

0.75

0.8

0.85

0.9

VT (V

)


-2.5 -2 -1.5 -1 -0.5 00.4

0.45

0.5

0.55

VBS

(V)

DegreeLow High

Mobility VariationMobility

It describes the ease with which carriers drift in the substrate materialIt i d fi d b

μ

It is defined by=(average carrier drift velocity, v)/(electrical field, E)

Mobility varies according to the type of charge carrier

Electrons have a higher mobility than holesThus NMOS has higher current-producing capability than

μ


Thus NMOS has higher current producing capability than the corresponding PMOS

Mobility decreases with increasing doping-concentration and increasing temperature

12

Drain Punchthrough & Hot ElectronsDrain punchthrough

When the drain voltage is high enough, the depletion region around the drain may extend to

Th i t t fl i ti source. Thus, causing current to flow irrespective of the gate voltage

Hot electronsWhen the source-drain electric field is too large, the electron speed will be high enough to break the electron-hole pair. Moreover, the electrons


p ,will penetrate the gate oxide, causing a gate current

Subthreshold ConductionSubthreshold region

The cutoff region is also referred to as the subthreshold region, where Ids increases exponentially with Vds and Vgs

Observe in the following figure that at Vgs<Vt, the current Observe in the following figure that at Vgs Vt, the current drops off exponentially rather than abruptly becoming zero

1 mA100 uA10 uA1 uA

100 nA

Vds=1.8Subthreshold

region

Saturationregion

Ids


10 nA1 nA

100 pA10 pA

0 0.3 0.6 0.9 1.2 1.5 1.8Vgs

Vt

Subthreshold slope

13

Junction LeakageThe p-n junctions between diffusion and the substrate or well form diodesThe p-type and n-type substrates are tied to GND or Vdd to ensure these diodes remain reverse-biasedHowever, reverse-biased diodes still conduct a small amount of current IL

, VD: diode voltage; vT: thermal voltage (about 26mv at room temperature)

In modern transistors with low threshold voltages, subthreshold conduction far exceeds junction leakage

)1( −= T

DvV

SL eII


N+ N+

Temperature DependenceThe magnitude of the threshold voltage decreases nearly linearly with temperature Carrier mobility decreases with temperatureJunction leakage increases with temperature because Junction leakage increases with temperature because Is is strongly temperature dependentThe following figure shows how the current Idsatdecreases with temperature

250

240


230

220

210

0 20 40 60 80 100 120

Idsat (uA)

Temperature (C)

14

Geometry DependenceThe layout designer draws transistors with width and length Wdraw and Ldraw. The actual gate dimensions may differ by some factors XW and XL

E.g., the manufacturer may create masks with narrower polysilicon or may overetch the polysilicon to provide shorter channels (negative XL)

Moreover, the source and drain tend to diffuse laterally under the gate by LD, producing a shorter effective channel length that the carriers must traverse between source and drain. Similarly, diffusion of the bulk by WD decreases the effective channel width


decreases the effective channel widthTherefore, the actually effective channel length and width can be expressed as

Leff=Ldraw+XL-2LD

Weff=Wdraw+XW-2WD

MOS Small Signal Model

Gate DrainCgd

Cgs+Cgb CdbgmVgsgds

(Vsb=0)

Source

Linear region Saturation region

2)(21

tgsoxds VVCL

WI −= μ]21)[( 2

dsdstgsoxds VVVVCL

WI −−= μ


)(2 tgsoxds Lμ2gL

])[( dstgsoxds

dsds VVVC

LW

dVdIg −−== μ

dsoxdsgs

dsm VC

LWconstV

dVdIg μ=== .)(| )( tgsoxm VVC

LWg −= μ

0=dsg

15

NMOS pass transistorCload is initially discharged, i.e., Vout=Vss

If Vin=Vdd and VS=Vdd, the Vout=Vdd-Vtn

If Vin=Vss and VS=Vdd, the Vout=Vss

Pass Transistor

PMOS pass transistorIf Vin=Vdd and V-S=Vss, the Vout=Vdd

If Vin=Vss and V S=Vss the Vout=Vtp

Cload

Vin

S

Vout


If Vin Vss and V-S Vss, the Vout Vtp

Cload

Vin

-S

Vout

Pass Transistor Circuits

VVDD VDD VDDVDD

VDD Vs = VDD-Vtn

Vs = |Vtp|

VDD

VDD-Vtn VDD-VtnVDD-Vtn

VDD

VDD

VDD-Vtn

VDD-2V


VSS

DD VDD 2Vtn

16

By combining behavior of the NMOS and PMOS, we can construct a transmission gate

The transmission gate can transmit both logic one and logic zero without degradation

Transmission Gate

g

The transmission gate is a fundamental and ubiquitous component in MOS logic

Cload

Vin

S

Vout

-S


p gA multiplexer elementA logic structure,A latch element, etc.

Consider the case where the control input changes rapidly, the Vin is Vdd, and the capacitor on the transmission gate output is discharged (Vss)

The transmission gate acts as a resistor

Voltage-Controlled Resistor

he transm ss on gate acts as a res stor

CVDD

Vout

-SIdn+Idp

Id

mA

Vss

Vdd

Id


CloadS

1 2 3 4 5Vout

Idp

Idn

17

Threshold dropsPass transistors suffer a threshold drop when passing the wrong value: NMOS transistors only pull up to VDD-Vtn, while PMOS transistors only pull down to |Vtp|

Summary

The magnitude of the threshold drop is increased by the body effectFully complementary transmission gates should be used where both 0’s and 1’s must be passed well

VDDVelocity saturation and mobility degradation result in less current than expected at high voltage


current than expected at high voltageThis means that there is no point in trying to use a high VDDto achieve high fast transistors, so VDD has been decreasing with process generation to reduce power consumptionMoreover, the very short channels and thin gate oxide would be damaged by high VDD

Leakage currentReal gates draw some leakage currentThe most important source at this time is subthreshold leakage between source and drain of a transistor that should be cut offThe subthreshold current of a OFF transistor decreases by an

Summary

The subthreshold current of a OFF transistor decreases by an order of magnitude for every 60-100mV that Vgs is below Vt. Threshold voltages have been decreasing, so subthreshold leakage has been increasing dramaticallySome processes offer multiple choices of Vt; low-Vt devices are used for high performance, while high-Vt devices are used for low leakage elsewhereLeakage current causes CMOS gates to consume power when idle


Leakage current causes CMOS gates to consume power when idle. It also limits the amount of time that data is retained in dynamic logic, latches, and memory cellsIn modern processes, dynamic logic and latches require some sort of feedback to prevent data loss from leakageLeakage increases at high temperature

1

Chapter 3 Chapter 3 Fabrication of CMOS Fabrication of CMOS Integrated CircuitsIntegrated CircuitsIntegrated CircuitsIntegrated Circuits

Jin-Fu LiD f El i l E i iDepartment of Electrical Engineering

National Central UniversityJungli, Taiwan

BackgroundThe CMOS Process FlowDesign Rules

Outline

Design RulesLatchupAntenna Rules & Layer Density RulesCMOS Process EnhancementsSummar


Summary3D Integration Technology Using TSV

2

An integrated circuit is created by stacking layers of various materials in a pre-specified sequence

Introduction

Both the electrical properties of the material and the geometrical patterns of the layer are important in establishing the characteristics of devices and networksMost layers are created first, and then

tt d i lith hi


patterned using lithographic sequenceDoped silicon layers are the exception to this rule

Silicon Dioxide (SiO2)It is an excellent electrical insulatorIt can be grown on a silicon wafer or deposited on t f th f

Material Growth and Deposition

top of the waferThermal oxide

Si+O2 SiO2 (dry oxidation), using heat as a catalystGrowth rate is lower

Si+2H2O SiO2+2H2 (wet oxidation)Growth rate is faster

The surface of the silicon is recessed from its original


The surface of the silicon is recessed from its original location

CVD oxideSiH4(gas)+2O2(gas) SiO2(solid)+2H2O(gas)Chemical vapor deposition (CVD)

3

Silicon Nitride (Si3N4)A.k.a. nitride3SiH4(gas)+4NH3(gas) Si3N4(solid)+12H2(gas)


Nitrides act as strong barriers to most atoms, this makes them ideal for use as an overglass layer

Polycrystal SiliconCalled polysilicon or just poly for shortIt is used as the gate material in MOSFETsSiH Si 2H


SiH4 Si+2H2

It adheres well to silicon dioxide

MetalsAluminum (Al) is the most common metal used for interconnect wiring in ICs

It is pr ne t electr mi rati n


It is prone to electromigrationJ=I/A; A=wt is the cross-section areaLayout engineers cannot alter the thickness t of the layerElectromigration is thus controlled by specifying the minimum width w to keep J below a max. value

Copper (Cu) has recently been introduced as a


pp ( ) yreplacement to aluminum

Its resistivity is about one-half the value of AlStandard patterning techniques cannot be used on copper layers; specialized techniques had to be developed

4

Material Growth and DepositionDoped Silicon Layers

Silicon wafer is the starting point of the CMOS fabrication processA doped silicon layer is a patterned n- or p-type section of p y p p ypthe wafer surfaceThis is accomplished by a technique called ion implantation

Basic section of an ion implanter

Ion source

Accelerator

Magnetic Mass Separator


Ion beam

wafer

Material Growth and DepositionThe process of deposition causes that the top surface has hillocks

If we continue to add layers (e.g., metal layers), the surface will get increasing rough and may lead to breaks in fine line g g g yfeatures and other problemsSurface planarization is required

Chemical-Mechanical Polishing (CMP)It uses a combination of chemical etching and mechanical sanding to produce planar surfaces on silicon wafers

Surface planarization


poly

substrate substrate

5

One of the most critical problems in CMOS fabrication is the technique used to create a pattern

l

Lithography

PhotolithographyThe photolithographic process starts with the desired pattern definition for the layerA mask is a piece of glass that has the pattern defined using a metal such as h i


chromium

The process for transferring the mask pattern to the surface of a silicon region

Coat photoresist

Transfer a Mask to Silicon Surface

Coat photoresistExposure stepEtching

Coat photoresistLiquid photoresist is sprayed onto a spinning wafer

Exposure


Exposure Photoresist is sensitive to light, such as ultraviolet (UV)

6

The figure shown as below depicts the main idea

Transfer a Mask to Silicon Surface

UV

maskHardened resist layer

The hardened resist layer is used to protect underlying regions from the etching process

E hi

wafer

a

photoresistwafer

resist layer


EtchingThe chemicals are chosen to attack and remove the material layer not shielded by the hardened photoresist

The figure shows the etching process

Dopping

Hardened resist layer Patterned

oxide layer

Creation of doped silicon

SubstrateOxide layer

Substrate

Arsenic ions


Substrate SubstrateN+ N+

Lateral dopping

7

DoppingThe conductive characteristics of intrinsic silicon can be changed by introducing impurity atoms into the silicon crystal latticeImpurity elements that use (provide) electrons are called as acceptor (donor)Silicon that contains a majority of donors (acceptor) is known as n-type (p-type)When n-type and p-type materials are merged


together, the region where the silicon changes from n-type to p-type is called junction

MOS TransistorBasic structure of a NMOS transistor


8

Fabrication Steps for an NMOS

p-substrate

PatterningSiO2 Layer

p-substrate

n+ n+Implant orDiffusion Implant ofp p-substrate

p-substrate p-substrate

n+ n+Gate Oxidation

Contact Cuts

Thin Oxide

Polysilicon

Impurities

SiO2 bydeposition

Al contacts


p-substrate p-substrate

n+ n+PatterningPolysilicon

PatterningAl layer

Four dominant CMOS technologiesN-well processP-well process

Basic CMOS Technology

Twin-tub processSilicon on insulator (SOI)

N-well (P-well) processStarts with a lightly doped p-type (n-type) substrate (wafer), create the n-type (p-type) well f th h l ( h l) d i d b ild


for the p-channel (n-channel) devices, and build the n-channel (p-channel) transistor in the native p-substrate (n-substrate)

9

N-Well CMOS Process

n-well mask

Mask (top view)Cross Section of Physical Structure

n-wellp-substrate

n-well

active mask


p-substrate

nitrideoxide

Active

n-well

N-Well CMOS Process

channel stop mask

ResistImplant (Boron)

p-channelstop

p-substrateChannel stop

n-well


p-substrate

n-well

10

N-Well CMOS Process

polysilicon mask

p-substrate

n-well

n+ mask

polysilicon


p-substrate

n-welln+ n+

n+ mask

N-Well CMOS Process

Light implant heavier implant

oxidepoly poly

n- n-n+ n+n- n-

Shadow drain implant LDD (lightly doped drain) structure

poly

p+ mask


p-substrate

n-welln+ n+ p+ p+

p+ mask

11

N-Well CMOS Process

contact mask

p-substrate

n-welln+ n+ p+ p+

metal mask

contact mask


p-substrate

n-welln+ n+ p+ p+

metal mask

CMOS Inverter in N-Well Process

in

Vdd Vssout

in


Vdd Vss

out

12

CMOS Inverter in N-Well Process

n+ n+p+ p+

p-substrate

n-well

n+ n+p p

field oxidegate oxidemetalpolysilicon contact cut


p-substrate

n-well

n+ n+p+ p+

A Sample of Multi-Layer Metal


13

Design rules (layout rules)Provide a necessary communication link between circuit designers and process engineers during

f t i h

Design Rules

manufacturing phaseThe goal of design rules is to achieve the optimum yield of a circuit with the smallest area cost

Design rules specify to the designer certain geometric constraints on the layout artwork so that the patterns on the processed wafer


so that the patterns on the processed wafer will preserve the topology and geometry of the designs

The design rules primarily address two issuesThe geometrical reproduction of features that can be reproduced by the mask-making and lith hi l

Design Rules

lithographical processThe interactions between different layers

Lambda-based rulesBased on a single parameter, lambda, which characterizes the linear feature – the resolution of the complete wafer implementation process


of the complete wafer implementation process

14

Examples of Design Rules

90

W ll

Different PotentialSame Potential

10

Well

Active3

3

Polysilicon

2

2

3

or6


Metal13

32

Contactor Via 2Hole

Transistor Layout

or

1

23

Tra

nsisto


5

15

Design Rules for Vias & Contacts

1Via

1

2

4

1

2

1Metal to

Poly ContactMetal toActive Contact

15

3 2

2


2

Design Rule Checker


16

Latchup is defined as the generation of a low-impedance path in CMOS chips between power supply rail and the ground rail due to

Latchup

interaction of parasitic pnp and npn bipolar transistors These BJTs form a silicon-controlled rectifier (SCR) with positive feedback and virtually short circuit the power rail to ground, th i i t fl d


thus causing excessive current flows and even permanent device damage

Latchup of a CMOS Inverter

p+ p+ p+n+ n+ n+

RwellNPN PNP

Vdd

N-well

Rsubstrate

well

Rwell2.0mA

I

P-substrate


Rsubstrate

Holding Voltage

Trigger point

Iramp

Iramp

0 1 2 3 4-1

Vne

Vne

17

Latchup TriggeringLatchup can be triggered by transient current or voltages that may occur internally to a chip during power-up or externally due to voltages

t b d l ti or currents beyond normal operating rangesTwo possible triggering mechanisms

Lateral triggering & vertical triggeringEx: the static trigger point of lateral triggering is


wellnpn

onpnpntrigger R

VI

α−≈

Reducing the value of resistors and reducing the gain of the parasitic transistors are the basis for eliminating latchup

Latchup Prevention

Latchup can be prevented in two basic methods

Latchup resistant CMOS processLayout techniques

I/O latchup prevention


p pReducing the gain of parasitic transistors is achieved through the use of guard rings

18

Guard RingsGuard rings are that p+ diffusions in the p-substrate and n+ diffusions in the n-well to collect injected minority carriers

p+

l

emitter

Vdd


N-well

n+

p-plus

n-plus

n-plus

basecollector

(substrate)

A p+ guard ring is shown below for an n+ source/drain

I/O Latchup Prevention

p++

p+n+

Vss

A n+ guard ring is shown below for a p+ source/drain

N-well+ +

+hole current

P+ collects hole current thereby shielding n+ source/drain

n+ collects electron current th b hi ldi +

Vdd


p+

N-well--

-electron current

n+

thereby shielding p+ source/drain

dd

n+

19

When a metal wire contacted to a transistor gate is plasma-etched, it can charge up to a voltage sufficient to break down thin gate oxideThe metal can be contacted to diffusion to provide a

Antenna Rules

The metal can be contacted to diffusion to provide a path for the charge to bleed awayAntenna rules specify the maximum area of metal that can be connected to a gate without a source or drain to act as a discharge elementThe design rule normally defines the maximum ratio f t l t t h th t h th


of metal area to gate area such that charge on the metal will not damage the gate

The ratios can vary from 100:1 to 5000:1 depending on the thickness of the gate oxide (and hence breakdown voltage) of the transistor in question

Antenna Rule Violation and Fix

L2Length L2 exceeds allowed limit

Wire attracts charge during plasma processing and builds up voltage V=Q/C

Any source/drain can act as adischarge elementdischarge element

Gate may be connected to source/drain at any metal layer in an auto routing situation

metal 4


Added link solves problem-L1 satisfies design rule

metal 1metal 2

metal 3

L1

20

Antenna Diode AdditionAn alternative method is to attach source/drain diodes to problem nets as shown below

These diodes can be simple junctions of n-diffusion to p-substrate rather than transistor source/drain regions

Antenna diode may be added

L2


Layer Density RulesFor advanced processes, a minimum and maximum density of a particular layer within a specific area should be specified

Layer density rulesLayer density rules are required as a result of the CMP process and the desire to achieve uniform etch ratesFor example, a metal layer might have to have 30% minimum and 70% maximum fill within a 1mm by 1mm areaFor digital circuits layer density levels are normally


For digital circuits, layer density levels are normally reached with normal routingAnalog & RF circuits are almost sparse

Gate and metal layers may have to be added manually or by a fill program after design has been completed

21

CMOS Process Enhancements Multiple threshold voltages

Low-Vt → more on current, but greater subthreshold leakageHigh-Vt → less current, but smaller subthreshold leakageUser low-Vt devices on critical paths and higher-Vt devices t p g telsewhere to limit leakage powerMultiple masks and implantation steps are used to set the various thresholds

Silicon on insulator (SOI) processThe transistors are fabricated on an insulatorTwo major insulators are used, SiOs and sapphireT j d t li i ti f th it b t


Two major advantages: elimination of the capacitance between the source/drain regions and body, leading to higher-speed devices; lower subthreshold leakage

CMOS Process Enhancements High-k gate dielectrics

MOS needs high gate capacitance to attract charge to channel→very thin SiO2 gate dieletrics

Scaling trends indicate the gate leakage will be Scaling trends indicate the gate leakage will be unacceptably large in such thin gates

Gates could use thicker dielectrics and hence leak less if a material with a higher dielectric constant were available


22

Some of more common CMOS technologies have been coveredA representative set of n-well process has

Summary

p pbeen introducedConcepts of design rules have been presentedThe important condition known as latchup has been introduced with necessary design rules to avoid this condition in CMOS chips


pAntenna rules & layer density rules should be considered in modern manufacturing process

3D integration approaches3D packaging technology3D integration using through silicon via (TSV)

3D k i h l

3D Integration Technology

3D packaging technology


Source: Proceedings of IEEE, Jan. 2009

23

3D integration using TSVVia-last technologyVia-first technology

Vi Fi


Via-First(1) Before CMOS

(2) After CMOS & BEOL

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 45Source: Yole, 2007.


Via-Last


(1) After BEOL & before bonding

(2) After bonding


Source: Yole, 2007.

24



Source: ASP-DAC 2009.

Fabrication Flow



25

Design Example



Benefits of 3D integration over 2D integration

High functionalityH h f

Benefits of 3D Integration

High performanceSmall form factorLow power

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 50Source: Proceedings of IEEE, Jan. 2009

26

Road Map of 3D Integration with TSVs

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 51Source: Proceedings of IEEE, Jan. 2009

1

Chapter 4 Chapter 4 Electrical Characteristics Electrical Characteristics

of CMOSof CMOSof CMOSof CMOS

Jin-Fu LiDepartment of Electrical EngineeringDepartment of Electrical Engineering


Resistance & Capacitance EstimationDC ResponseLogic Level and Noise Margins

Outline

Transient Response Delay EstimationTransistor SizingPower AnalysisScaling Theory


2

Resistance , where is (resistivity,

thickness, conductor length, conductor width) Sh i

Resistance Estimation

)/)(/( WLtR ρ= ),,,( WLtρ

Sheet resistance□

Thus )/( WLRR s=

W

W

W

L

t

/Ω=sR

1 rectangular block)/( WLRR s=


W L

LL

t

4 rectangular block)/()2/2( WLRWLRR ss ==

A simplified linear model of MOS is useful at the logic level design

RC model of an NMOS

Drain-Source MOS Resistance

RG

The drain-source resistance at any point on the current curve as shown below

DS

CDCs

Rn

DS

G


Vds

Ids

ab

c

3

Drain-Source Resistance

The resistance at point aThe current is approximated by

dstgsnds VVVI )( −≈ βThus the resistance is

The resistance at point bThe full non-saturated current must be used so that

)(/1 tgsnn VVR −≈ β

g

])(2[1 2ddd VVVVI −−= β


Thus the resistance is ])(2[/2 dstgsnn VVVR −−= β

])(2[2 dsdstgsnds VVVVI β

Drain-Source Resistance The resistance at point c

The current is

Thus the resistance is 2)(

21

tgsnds VVI −≈ β

Thus the resistance is

Rn is a function of both Vgs and Vds

These equations show that it is not possible to define a constant value for RnHowever R is inversely proportion to in all

2)(/2 tgsndsn VVVR −= β

β


However, Rn is inversely proportion to in all cases, i.e.,

, W/L is called aspect rationnR β/1∝

)/( LWkn =β

nβ

4

Capacitance EstimationThe switching speed of MOS circuits are heavily affected by the parasitic capacitances associated with the MOS device and i t ti itinterconnection capacitancesThe total load capacitance on the output of a CMOS gate is the sum of

Gate capacitanceDiffusion capacitanceR ti it


Routing capacitanceUnderstanding the source of parasitic loads and their variations is essential in the design process

MOS-Capacitor CharacteristicsThe capacitance of an MOS is varied with the applied voltagesCapacitance can be calculated byp y

is dielectric constantis permittivity of free space

Depend on the gate voltage, the state of the MOS surface may be in

Ad

C xεε 0=

xε

0ε


yAccumulation DepletionInversion

5

MOS Capacitor CharacteristicsWhen Vg<0, an accumulation layer is formed

The negative charge on the gate attracts holes toward the silicon surfaceTh MOS t t b h lik ll l l t The MOS structure behaves like a parallel-plate capacitor

gate gate

Cotox

Vg<0

AC SiO 20εε


P-substrate

o At

Cox

SiO 200 =

MOS Capacitor CharacteristicsWhen a small positive voltage is applied to the gate, a depletion layer is formed

The positive gate voltage repels holes, leaving a ti l h d i d l t d f inegatively charged region depleted of carriers

gate gate

Co

CDepletion layer

tox

Vg~0

d

Ad

C Sidep

εε 0=


P-substrate

Cdep

dep

depgb CC

CCC

+=

0

0

6

MOS Capacitor Characteristics When the gate voltage is further increased, an n-type channel (inversion layer) is created

If the MOS is operated at high frequency, the f h i t bl t t k f t i surface charge is not able to track fast moving

gate voltagesgate gate

Co

C Depletion layer

tox

Vg>0

Channel

0CC gb =Low frequency

Hi h f


P-substrate

CdepDepletion layer

min0

0 CCC

CCC

dep

depgb =

+=

High frequency

MOS Capacitor Characteristics Consequently, the dynamic gate capacitance as a function of gate voltage, as shown below

Accumulation Depletion Inversion

VgsV0

1.0

C/Co

Accumulation Depletion Inversion

Low freq.

High freq.


The minimum capacitance depends on the depth of the depletion region, which depends on the substrate doping density

VgsVt0

7

MOS Device CapacitancesThe parasitic capacitances of an MOS transistor are shown as below

Cgs, Cgd: gate-to-channel capacitances, which are l d t th d th d i i f th lumped at the source and the drain regions of the channel, respectivelyCsb, Cdb: source and drain-diffusion capacitances to bulkCgb: gate-to-bulk capacitance

gateCdbCgd


Csb Cdb

CgdCgbCgs

depletion layer

substrate

source drain

Cg=Cgb+Cgs+Cgd

channel

CsbCgbCgs

Variation of Gate CapacitanceThe behavior of the gate capacitance in the three regions of operation is summarized as below

Off region (Vgs<Vt): Cgs=Cgd=0; Cg=Cgb

Non-saturated region (Vgs-Vt>Vds): Cgs and Cgdbecome significant. These capacitances are dependent on gate voltage. Their value can be estimated as

ACC SiOd

201 εε==


Saturated region (Vgs-Vt<Vds): The drain region is pinched off, causing Cgd to be zero. Cgs increases to approximately

At

CCox

gsgd 2

At

Cox

SiOogs

2

32 εε

=

8

Approximation of the Cg

The Cg can be further approximated with , where

The gate capacitance is determined by the ox

SiOoox t

C 2εε

=ACC oxg =

gate area, since the thickness of oxide is associated with process of fabrication For example, assume that the thickness of silicon oxide of the given process is . Calculate the capacitance of the MOS shown b l

mμ810150 −×

λ2


below

pFpFC g 005.01025.25210150

10854.89.3 48

14

≈××=××

××= −

−

−

λ2mμλ 5.0=

λ5

λ4

Diffusion CapacitanceDiffusion capacitance Cd is proportional to the diffusion-to-substrate junction area

Substrateb

aSourceDiffusion Area

DrainDiffusion Area ba

Xc (a finite depth)

Cjp


Cja

)22()( baCabCC jpjad +×+×=Cja=junction capacitance per micron squareCjp=periphery capacitance per micron

9

Junction CapacitanceSemiconductor physics reveals that a PN junction automatically exhibits capacitance due to the opposite polarity charges involved. This is called junction or depletionThis is called junction or depletioncapacitance and is found at every drain or source region of a MOS The junction capacitance is varies with the junction voltage, it can be estimate as

V


=junction voltage (negative for reverse bias)=zero bias junction capacitance ( )=built-in junction voltagebV

m

b

jjj V

VCC −−= )1(0

0jCjC

V6.0~

0=jV

Single Wire CapacitanceRouting capacitance between metal and substrate can be approximated using a parallel-plate model

W L

T

Fringing fields

H

substrate Insulator (Oxide)


In addition, a conductor can exhibit capacitance to an adjacent conductor on the same layer

substrate ( )

10

Multiple Conductor CapacitancesModern CMOS processes have multiple routing layers

The capacitance interactions between layers can become quite complex

Multilevel-layer capacitance can be modeled as below

Layer 3

Layer 2C23 C22Multi-layer

d t


Layer 2

Layer 1C21

C2=C21+C23+C22

conductor

A Process Cross SectionInterlayer capacitances of a two-level-metal process

B CA D F GEB CA D F GE

m2m2

m2m2

m2m2

m1

m1m1

C

C

CC

C

polypoly


CC C

C CThin-oxide/diffusion

Substrate

polypoly

11

For bond wire inductance

Inductor

)4ln(2 d

hLπμ

= hd

wFor on-chip metal wires

The inductance produces Ldi/dt noise especially for ground bouncing noise. Note

)4

8ln(2 h

wwhL +=

πμ

h

w


that when CMOS circuit are clocked, the current flow changes greatly

dtdiLV =

Distributed RC EffectsThe propagation delay of a signal along a wire mainly depends on the distributed resistance and capacitance of the wireA long wire can be represented in terms of several RC sessions, as shown below

Vj-1 Vj Vj+1

Ij-1 IjR

C

R

C

R

C

R

C

R

C


The response at node Vj with respect to time is then given by

RVV

RVV

IIdt

dVCIdtCdV jjjj

jjj )()(

)( 111

+−−

−−

−=−=⇒=

12

Distributed RC EffectsAs the number of sections in the network becomes large (and the sections become small), the above expression reduces to the diff ti l fdifferential form

Alternatively, a discrete analysis of the ci cuit sh n in th p vi us p i lds n

22

2

kxtdx

VddtdVrc x =⇒=

cr : resistance per unit length

: capacitance per unit length


circuit shown in the previous page yields an approximate signal delay of

, where n=number of sections 2)1(7.0 +

×=nRCntn

27.0

2

1rclt =

Wire Segmentation with BuffersTo optimize speed of a long wire, one effective method is to segment the wire into several sections and insert buffers within th tithese sectionsConsider a poly bus of length 2mm that has been divided into two 1mm sections.

Assume thatWith buffer

215104 xtx−×=

215215 10001041000104 ××++××= −−bufp tt

b fb f tnsnstns +=++= 844


Without buffer By keeping the buffer delay small, significant gain can be obtained with buffer insertion

bufbuf tnsnstns +++ 844

nst p 162000104 215 =××= −

13

CrosstalkA capacitor does not like to change its voltage instantaneously.A wire has high capacitance to its neighbor.

When the neighbor switches from 1-> 0 or 0->1, the wire tends to switch too.Called capacitive coupling or crosstalk.

Crosstalk effectsNoise on nonswitching wires

d d l h


Increased delay on switching wires

Crosstalk DelayAssume layers above and below on average are quiet

Second terminal of capacitor can be ignoredModel as Cgnd = Ctop + Cbot

Effective Cadj depends on behavior of neighbors

Miller effect

A BB ΔV Ceff(A) MCF


A BCadjCgnd Cgnd

Constant VDD Cgnd + Cadj 1

Switching with A 0 Cgnd 0

Switching opposite A 2VDD Cgnd + 2 Cadj 2

14

Crosstalk NoiseCrosstalk causes noise on nonswitching wiresIf victim is floating:

model as capacitive voltage divider

Aggressor

adjvictim aggressor

gnd v adj

CV V

C C−

Δ = Δ+


Cadj

Cgnd-v

Victim

ΔVaggressor

ΔVvictim

Driven VictimUsually victim is driven by a gate that fights noise

Noise depends on relative resistancesVictim driver is in linear region, agg. in saturationIf sizes are same, Raggressor = 2-4 x Rvictim

11

adjvictim aggressor

gnd v adj

CV V

C C k−

Δ = Δ+ +

Cadj

Aggressor

ΔVaggressor

Raggressor

Cgnd-a


( )( )

aggressor gnd a adjaggressor

victim victim gnd v adj

R C Ck

R C Cττ

−

−

+= =

+

adj

Cgnd-v

VictimΔVvictim

Rvictim

15

Simulation WaveformsSimulated coupling for Cadj = Cvictim

Aggressor1.8

Victim (undriven): 50%

Victim (half size driver): 16%0.6

0.9

1.2

1.5


Victim (equal size driver): 8%Victim (double size driver): 4%

t (ps)0 200 400 600 800 1000 1200 1400 1800 2000

0

0.3

DC ResponseDC Response: Vout vs. Vin for a gateEx: Inverter

When Vin = 0 Vout=VDDin out DD

When Vin = VDD Vout=0In between, Vout depends ontransistor size and currentBy KCL, must settle such thatIdsn = |Idsp|

Idsn

Idsp Vout

VDD

Vin


p

We could solve equationsBut graphical solution gives more insight

16

Transistor OperationCurrent depends on region of transistor behaviorFor what Vin and Vout are NMOS and PMOSFor what Vin and Vout are NMOS and MOSin

Cutoff?Linear?Saturation?


NMOS Operation

Cutoff Linear SaturatedVgsn < Vtn Vgsn > Vtn Vgsn > Vtn

Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn

I

VDD


Idsn

Idsp VoutVinVgsn = Vin

Vdsn = Vout

17

NMOS Operation

Cutoff Linear SaturatedVgsn < Vtn

Vi < Vt

Vgsn > Vtn

Vi > Vt

Vgsn > Vtn

Vi > VtVin < Vtn Vin > Vtn

Vdsn < Vgsn – Vtn

Vout < Vin - Vtn

Vin > Vtn

Vdsn > Vgsn – Vtn

Vout > Vin - Vtn

I

VDD

V V


Idsn

Idsp VoutVin

Vgsn = Vin

Vdsn = Vout

PMOS Operation

Cutoff Linear SaturatedVgsp > Vtp Vgsp < Vtp Vgsp < Vtp

Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp

Idsp V

VDD

VV = V V V < 0


Idsn

dsp VoutVinVgsp = Vin - VDD

Vdsp = Vout - VDD

Vtp < 0

18

PMOS Operation

Cutoff Linear SaturatedVgsp > Vtp

Vin > VDD + Vtp

Vgsp < Vtp

Vin < VDD + Vtp

Vgsp < Vtp

Vin < VDD + Vtp

Vdsp > Vgsp – Vtp

Vout > Vin - Vtp

Vdsp < Vgsp – Vtp

Vout < Vin - Vtp

I

VDD

V = V V V < 0


Idsn

Idsp VoutVin

Vgsp = Vin - VDD

Vdsp = Vout - VDD

Vtp < 0

I-V CharacteristicsMake pMOS is wider than nMOS such that βn= βp

Vgsn5

Vgsn4

Vgsn3

Vgsn2Vgsn1

V

Vgsp2

Vgsp1VDD

-VDD

V

-Vdsp

Idsn

0


Vgsp5

Vgsp4

Vgsp3Vdsn

-Idsp

19

Current & Vout, Vin

Vin5Vin1

Vin4

Vin3

Vin2

Vin2

Vin3

Vin4

Idsn, |Idsp|


in2Vin1

in4Vin5

VoutVDD

Load Line AnalysisFor a given Vin:

Plot Idsn, Idsp vs. Vout

Vout must be where |currents| are equal in

Idsp V

VDD

V

Vin5

Vin4

V

Vin1

Vin2

V

Idsn, |Idsp|


Idsn

VoutVinVin3

Vin2Vin1

Vin3

Vin4Vin5

VoutVDD

20

DC Transfer CurveTranscribe points onto Vin vs. Vout plot

Vin5

Vin4

Vin1

Vin2

VDD

A B

Vin3

Vin2Vin1

Vin3

Vin4Vin5

VoutVDD


CVout

0

Vin

VDD

DE

Vtn VDD/2 VDD+Vtp

Operation RegionsRevisit transistor operating regions

CVout

VDD

A B

D

Region nMOS pMOSA Cutoff LinearB Saturation LinearC Saturation SaturationD Linear Saturation


0

Vin

VDD

DE

Vtn VDD/2 VDD+Vtp

E Linear Cutoff

21

Beta RatioIf βp / βn ≠ 1, switching point will move from VDD/2Called skewed gateOther gates: collapse into equivalent inverter

Vout

VDD

12

10p

n

ββ

=


0

Vin

VDD

0.50.1p

n

ββ

=

Noise MarginHow much noise can a gate input see before it does not recognize the input?

IndeterminateRegion

NMH

Input CharacteristicsOutput Characteristics

VOH

VDD

VIH

V

Logical HighInput Range

Logical HighOutput Range


Region

NMLVOL

GND

VIL

Logical LowInput RangeLogical Low

Output Range

22

Transient AnalysisDC analysis tells us Vout if Vin is constantTransient analysis tells us Vout(t) if Vin(t) changesg


Switching CharacteristicsSwitching characteristics for CMOS inverter

V (t) V (t)Vin(t) Vout(t)

Vin(t)

VDD

CL

Ids

Vds=Vgs-Vt


Vout(t)

tdf tdr90%

50%

10%tf tr

VDD

t

t

Vout(t) VDD

23

Switching CharacteristicsRise time (tr)

The time for a waveform to rise from 10% to 90% of its steady-state value

Fall time (t )Fall time (tf)The time for a waveform to fall from 90% to 10% steady-state value

Delay time (td)The time difference between input transition (50%) and the 50% output level (This is the time


(50%) and the 50% output level. (This is the time taken for a logic transition to pass from input to outputHigh-to-low delay (tdf)Low-to-high delay (tdr)

Fall Time of the InverterEquivalent circuit for fall-time analysis

PMOS PMOS

The fall time consists of two intervalst i d d i hi h th it lt V

IdsnNMOS NMOS

Saturated Vout>=VDD-Vtn Nonsaturated 0<Vout<=VDD-Vtn

Vout(t) Vout(t)

Rcn CLCL

Input rising


tf1=period during which the capacitor voltage, Vout, drops from 0.9VDD to (VDD-Vtn)tf2=period during which the capacitor voltage, Vout, drops from (VDD-Vtn) to 0.1VDD

24

Timing Calculationtf1 can be calculated with the current-voltage equation as shown below, while in saturation

0)(2

2 =−+ tnDDnout

L VVdt

dVC β

tf2 also can be obtained by the same wayFinally, the fall time can be estimated with

Similarly, the rise time can be estimated with

2dt

DDn

Lf V

Cktβ

×≈

DDp

Lr V

Cktβ

×≈


Thus the propagation delay is )11(

pnDD

Lp V

Cktββ

+×≈

p

Design Challenges= , rise time=fall timeThis implies Wp=2-3Wn

Reduce CL

nβ pβ

LCareful layout can help to reduce the diffusion and interconnect capacitance

Increase andIncrease the transistor sizes also increases the diffusion capacitance as well as the gate capacitance. The latter will increase the fan out factor of the

nβ pβ


The latter will increase the fan-out factor of the driving gate and adversely affect its speed

Increase VDDDesigners don’t have too much control over this

25

Gate DelaysConsider a 3-input NAND gate as shown below

IN 3

P3 P2 P1

Nout

When pull-down path is conducting

IN-3

IN-2

IN-1

N3

N2

N1

)/1()/1()/1(1

321 nnnneff βββ

β++

=


For When the pull-down path is conducting

Only one p-transistor has to turn on to raise the output. Thus

3321n

neffnnnβββββ =⇒==

ppeff ββ =

Graphical illustration of the effect of series transistors

Gate Delays

In n l th f ll tim t is mt (t /m) f m n

L

L

L

3L

ww


In general, the fall time tf is mtf (tf/m) for m n-transistors in series (parallel). Similarly the rise time tr for k p-transistors in series (parallel) is ktr (tr/k)

26

Switch-Level RC ModelRC modeling

Transistors are regarded as a resistance discharging or charging a capacitance

Simple RC modelingLumped RCs

Elmore RC modelingDistributed RCs

Rp

Rn

C

∑∑ −×= pathpulldownpulldowndf CRt


ii

id CRt ∑=

ExampleConsider a 4-input NAND as shown below

Simple RC model∑∑ −×= pathpulldownpulldowndf CRt

Elmore RC model

P4 P3 P2 P1

N4

N3

A

BCab

C

Cout

out

∑∑ pppf

)()( 4321 cdbcaboutNNNN CCCCRRRR +++×+++=

outpdr CRt ×= 4

ii

id CRt ∑=


N2

N1

C

D

Cbc

Ccd])[(])[()(

321

211

abNNN

bcNNcdNdf

CRRRCRRCRt

×+++

×++×=

])[( 4321 outNNNN CRRRR ×++++

27

Cascaded CMOS InverterAs discussed above, if we want to have approximately the same rise and fall times for an inverter, for current CMOS process, we must m kmake

Wp =2-3Wn

Increase layout area and dynamic power dissipation

In some cascaded structures it is possible to use minimum or equal-size devices without


minimum or equal size devices without compromising the switching response In the following, we illustrate two examples to explain why it is possible

Cascaded CMOS InverterExample 1:

I h

tinv-pair

4/1

risefallpairinv

CRCR

ttt

323

+=−

Example 2:

Icharge

Idischarge3Ceq

Wp=2Wn

3Ceq

4/1

2/1

RR eqeq CCR 32

23 +=

eqeq RCRC 33 +=

eqRC6=

tinv-pair


Icharge

Idischarge2Ceq

Wp=Wn

2Ceq

inv pair

2/1

2/1

2R Reqeq

risefallpairinv

CRCRttt

222 +=

+=−

eqRC6=

28

Stage RatioTo drive large capacitances such as long buses, I/O buffers, etc.

Using a chain of inverters where each successive inverter is made larger than the previous one until inverter is made larger than the previous one until the last inverter in the chain can drive the large load in the time requiredThe ratio by which each stage is increased in size is called stage ratio

Consider the circuit shown below


It consists of n-cascaded inverters with stage-ratio a driving a capacitance CL

1 a a2 a3

CLn(4) stages

Stage RatioThe delay through each stage is atd, where td is the average delay of a minimum-sized inverter driving another minimum-sized inverterH th d l th h st s is tHence the delay through n stages is natd

If the ratio of the load capacitance to the capacitance of a minimum inverter, CL/Cg, is R, then an=R

Hence ln(R)=nln(a)Thus the total delay is ln(R)(a/ln(a))td


Thus the total delay is ln(R)(a/ln(a))td

The optimal stage ratio may be determined from

where k is opt

opt

aak

opt ea+

=gate

drain

CC

29

Power DissipationInstantaneous power

The value of power consumed at any given instant

P k )()()( titvtP =

Peak powerThe highest power value at any given instant; peak power determines the component’s thermal and electrical limits and system packaging requirements

Average powerpeakpeak ViP =


Average powerThe total distribution of power over a time period; average power impacts the battery lifetime and heat dissipation

∫∫++

==Tt

t

Tt

tave dttiTVdttP

TP )()(1

Power Analysis for CMOS CircuitsTwo components of power consumption in a CMOS circuit

Static power dissipationd b h l k d h Caused by the leakage current and other static current

Dynamic power dissipationCaused by the total output capacitanceCaused by the short-circuit current

The total power consumption of a CMOS circuit is


Ps: static power (leakage power); Psw: switching power; Psc: short-circuit power

scswst PPPP ++=

30

Static PowerStatic dissipation is major contributed by

Reverse bias leakage between diffusion regions and the substrateSubthreshold conduction

KTqVeii / )1(=

PN junction reverse biasleakage current

VDD

Vin

Vout

Gnd

p+ p+p+ n+ n+ n+


ply

n

leakages

s

VIP

eii

sup1

0 )1(

×=

−=

∑p-substrate

n-well

n=number of devices

Dynamic Power DissipationSwitching power

Caused by charging and discharging the output capacitive load

C id i d i hi Consider an inverter operated at a switching frequency f=1/T

VinVout

VDD

ip

∫=T

oosw dttvtiT

P0

)()(1

dvCii

dtdvCii

o

oLop

==

==


Vin

CLin

io dtCii Lon −=−=

][10

0

∫ ∫−=DD

DD

V

V ooLooLsw dvvCdvvCT

P

22

DDLDDL

sw VfCTVCP ==

31

Power & EnergyEnergy consumption of an inverter (from )

The energy drawn from the power supply isDDV→0

2

The energy stored in the load capacitance is

The output fromThe Ecap is consumed by the pull-down NMOS

2

0 21

DDLoo

V

cap VCdvvCE DD == ∫

2DDLVCQVE ==

0→DDV


Low-energy design is more important than low-power design

Minimize the product of power and delay

Short-Circuit Power DissipationEven if there were no load capacitance on the output of the inverter and the parasitics are negligible, the gate still dissipate switching energyf h h l l b h h N d If the input changes slowly, both the NMOS and

PMOS transistors are ON, an excess power is dissipated due to the short-circuit currentWe are assuming that the rise time of the input is equal to the fall timeThe short circuit power is estimated as


The short-circuit power is estimated asDDmeansc VIP =

32

Short-Circuit Power DissipationImean can be estimated as follows

VDD

tr tf

T

VDD-|Vt |

Vin

Vin Vout

CL

isc

r fVDD |Vtp|

Vtn

Imax

Imean


t1 t2 t3

])([4

])()([12

2

1

2

1

3

2

∫

∫ ∫

=

+×=

t

tmean

t

t

t

tmean

dttiT

I

dttidttiT

I

Short-Circuit Power DissipationThe NMOS transistor is operating in saturation, hence the above equation becomes

dtVtVIt β 2 ]))(([4 2

∫

tt

tVVt

tt

VtV

dtVtVT

I

r

rDD

T

r

DDin

Tintmeanβ

2

1

2

)(

]))((2

[1

=

=

=

−= ∫


fVVP

t

TDDsc τβ 3

2

)2(12

2

−= )( τ== fr tt

33

Power Analysis for Complex GatesThe dynamic power for a complex gate cannot be estimated by the simple expression CLVDDfDynamic power dissipation in a complex gate

Internal cell powerCapacitive load power

Capacitive load power

Internal cell powerfVCP DDLL

2α=B C

VDD

C1Aout


pfVVCP DDii

n

ii∑

=

=1

int αC2

B

CA

Glitch Power DissipationIn a static logic gate, the output or internal nodes can switch before the correct logic value is being stable. This phenomenon results in spurious transitions called glitches

DAB

ABC

D

100 111


CZ

Z

Unit delay Spurious transition

34

Rules for Avoiding Glitch PowerBalance delay paths; particularly on highly loaded nodes

Insert, if possible, buffers to equalize the fast pathAvoid if possible the cascaded design


Avoid if possible the cascaded designRedesign the logic when the power due to the glitches is an important component

Principles for Power ReductionSwitching power dissipation

n

∑

fVCP DDLL2α=

Prime choice: reduce voltageRecent years have seen an acceleration in supply voltage reduction

fVVCP DDiii

i∑=

=1

int α


Design at very low voltage still open question (0.6V…0.9V by 2010)

Reduce switching activityReduce physical capacitance

35

Layout Guidelines for LP DesignsIdentify, in your circuit, the high switching nodesKeep the wires of high activity nodes shortUse low-capacitance layers (e.g., metal2, metal 3, etc ) for high capacitive nodes and bussesetc.) for high capacitive nodes and bussesAvoid, if possible, the use of dynamic logic design styleFor any logic design, reduce the switching activity, by logic reordering and balanced delays through gate tree to avoid glitch problemI iti l th i i i d i


In non-critical paths, use minimum size devices whenever it is possible without degrading the overall performance requirementsIf pass-transistor logic style is used, careful design should be considered

Sizing Routing ConductorsWhy do metal lines have to be sized?

ElectromigrationPower supply noise and integrity (i.e., satisfactory

d i l lt l l t d t power and signal voltage levels are presented to each gate)RC delay

Electromigration is affected byCurrent densityTemperature


TemperatureCrystal structure

For example, the limiting value for 1 um-thick aluminum is mmAJ Al μ/21→=

36

Power & Ground BounceAn example of ground bounce

Voltage

Vin

CurrentTime

Time

L

VDD Pad

VSS Pad

Vout

VinVout

II


VL=L(di/dt)Time

L

VSS PadVL

Ground bounce

Approaches for Coping with L(di/dt)Multiple power and ground pins

Restrict the number of I/O drivers connected to a single supply pins (reduce the di/dt per supply pin)

Careful selection of the position of the power and ground pins on the package

Avoid locating the power and ground pins at the corners of the package (reduce the L)

Increase the rise and fall timesReduce the di/dt


Reduce the di/dtAdding decoupling capacitances on the board

Separate the bonding-wire inductance from the inductance of the board interconnect

37

Contact ReplicationCurrent tends to concentrate around the perimeter in a contact hole

This effect, called current crowding, puts a ti l li it th i f th t tpractical upper limit on the size of the contact

When a contact or a via between different layers is necessary, make sure to maximize the contact perimeter (not area)


Charge SharingCharge Q=CVA bus example is illustrated to explain the charge sharing phenomenon

A bus can be modeled as a capacitor Cb

An element attached to the bus can be modeled as a capacitor Cs

Bus


Vb Cb Vs Cs)( bbb VCQ = )( sss VCQ =

ssbbT VCVCQ +=

sbT CCC +=

)/()( sbssbbT

TR CCVCVC

CQV ++==

38

Design MarginingThe operating condition of a chip is influenced by three major factors

Operating temperatureS l ltSupply voltageProcess variation

One must aim to design a circuit that will reliably operate over all extremes of these three variablesDesign corners


Design cornersSimulating circuits at all corners is needed

SSTTFF

Package IssuesPackaging requirements

Electrical: low parasiticsMechanical: reliable and robust

h l ff h lThermal: efficient heat removalEconomical: cheap

Bonding techniques

Substrate

Wire Bonding


Lead Frame

Substrate

Die

Pad

39

Yield Estimation

%100per wafer chips ofnumber Total

per wafer chips good of No.×=Y

tW fyield Dieper wafer Dies

costWafer cost Die×

=

( )area die2

diameterwafer area die

diameter/2wafer per wafer Dies2

××π

−×π

=


Die Cost

Single die

Wafer


Going up to 12” (30cm)

40

Scaling TheoryConsider a transistor that has a channel width W and a channel length LWe wish to find out how the main electrical h t i ti h h b th di i characteristics change when both dimensions

are reduced by a scaling factor S>1 such that the new transistor has sizes

Gate area of the scaled transistorS

WW =~SLL =~


The aspect ratio of the scaled transistor2

~SAA =

LW

LW

~~

=

Scaling TheoryThe oxide capacitance is given by

If the new transistor has a thinner oxide that is d d th th l d d i h

ox

oxox t

C ε=

t~decreased as , then the scaled device has

The transconductance is increased in the scaled device to

The resistance is reduced in the scaled device to

Stt ox

ox =~

oxox SCC =~

ββ S=~


The resistance is reduced in the scaled device to

Assume that the supply voltage is not altered

SR

VVSR

TDD

=−

=)(

1~β

41

Scaling TheoryOn the other hand, if we can scale the voltages in the scaled device to the new values of

The resistance of the scaled device would be S

VV DDDD =~

SVV T

T =~

The resistance of the scaled device would be unchanged with

The effects of scaling the voltage, consider a scaled MOS with reduced voltages of

The current of the scaled device is given by S

VV DSDS =

~

RR =~

SVV GS

GS =~


f g y

The power dissipation of the scaled device is SI

SV

SV

SVSI DDSTGS

D =−= ])[(2

~ β

22~~~

SP

SIVIVP DDS

DDS ===

Summary

We have presented models that allow us to estimate circuit timing performance, and power dissipationp pGuidelines for low-power design have also been presentedThe concepts of design margining were also introducedThe scaling theory has also introduced


The scaling theory has also introduced

1

Chapter 5 Chapter 5 Elements of Physical DesignElements of Physical Design

Jin-Fu LiAdvanced Reliable Systems (ARES) LabAdvanced Reliable Systems (ARES) Lab.


Jhongli, Taiwan

Basic ConceptsLayout of Basic StructuresC ll C ts

Outline

Cell ConceptsMOS SizingPhysical Design of Logic GatesDesign Hierarchies


2

Physical designThe actual process of creating circuits on siliconDuring this phase, schematic diagrams are carefully translated into sets of geometric patterns that are

d t d fi th hi h i l t t

Basic Concepts

used to define the on-chip physical structuresEvery layer in the CMOS fabrication sequence is defined by a distinct patternThe process of physical design is performed using a computer tool called a layout editor

A graphics program that allows the designer to specify


A graph cs program that allows the des gner to spec fy the shape, dimensions, and placement

Complexity issues are attacked by first designing simple gates and storing their descriptive files in a library subdirectory or folder

The gates constitute cells in the libraryLibrary cells are used as building blocks by creating copies of the basic cells to

Basic Concepts

g pconstruct a larger more complex circuit

This process is called instantiate of the cellA copy of a cell is called an instance

Much of the designer’s work is directed toward the goal of obtaining a fast circuit in


g gthe minimum amount of area

Small changes in the shapes or area of a polygon will affect the resulting electrical characteristics of the circuit

3

CAD ToolsetsPhysical design is based on the use of CAD tools

Simplify the procedure and aid in the verification process

Physical design toolsetsLayout editor Extraction routineLayout versus schematic (LVS)

l h k ( )


Design rule checker (DRC) Place and route routineElectrical rule checker (ERC)

Layout of Basic StructuresThe masking sequence of the P-substrate technology was established as

Start with P-type substratenWellActivePolypSelectnSelectActive ContactPoly contact


Poly contactMetal1ViaMetal2…

4

Layout of Basic StructuresIt is worth remembering that the features on every level have design rule specifications for the minimum width w of a line, and a minimum edge to edge spacing s between adjacent edge-to-edge spacing s between adjacent polygons

For example,

w


S

Layouts of PMOS & NMOSNMOS

L Poly

LPoly

PMOS

n+n+

P

n+ n+ W

L Poly

LPoly


p+p+

N-well

Poly

p+ p+ W

P N-well

5

A transistor-level CMOS inverter & the corresponding layout

The Layout of a CMOS Inverter

VVdd

VoutVin

Vin Vout

Vdd


Vss

Vss

Layouts of a 2-Input NAND Gate

VddVdd

az

a

z b


Vss

a

Vss

b

6

Layouts of a 2-Input NOR Gate

VddVdd

za

zb


a

Vss

b

Vss

Cell ConceptsThe basic building blocks in physical design are called cellsLogic gates as basic cells

Vdd Vdd

Vss Vss

in out

Vdd Vdd

Vss Vss

in1out

in2

Vdd Vdd

Vss Vss

in1out

in2

XNOT XNAND2 XNOR2


Note that power supply ports for Vdd and Vss are chosen to be at the same locations for every cellThe width of each cell depends on the transistor sizes and wiring used at the physical level

7

Cell Creation Using Primitive CellsCreate a new cell providing the function

f=a’bVdd

Vss

a f

b

2XNOT+XNAND2


Vdd

Vss

ab

f

NOT NAND2

Layout of CellsVdd & Vss power supply lines

Vdd

D : edge to edge distance between V and V

Vss

nWell PMOSs

NMOSsP-substrateDm1-m1 Pm1-m1


Dm1-m1: edge-to-edge distance between Vdd and Vss

Pm1-m1: distance between the middle of the Vdd and Vss linesPm1-m1=Dm1-m1+Wdd, where Wdd is the width of the power supply lines

8

Layout of CellsLayout styles of transistors

Vdd

WP

Wn

WP

Wn


Vss

Effect of Layout ShapesLarger spacing between Vdd and Vss

Vdd

Smaller spacing between Vdd and Vss

A B C D

Vss


A B C D

Vdd

Vss

9

Routing ChannelsInterconnection routing considerations are very important considerations for the Vss-Vdd spacing

In complex digital systems, the wiring is often more complicated than designing the transistor arraysp g g yThe general idea for routing

Metal1 Wiring

Vdd

Vss

Vdd

cell1 cell2 cell3 cell4 cell5

Routing Channel

Metal2

Metal3 Wiring


Metal1 Wiring

Vss

Vdd

Vss

cell6

cell10

cell7 cell8 cell9

cell13cell12cell11

Routing Channel

Metal2 Wiring

High-Density TechniquesAlternate Vdd and Vss power lines and share them with cells above and below

For example, V

Since no space is automatically reserved for routing

Vdd

Vss

Vdd

Vss

Logic cells

Inverted logic cells

Logic cells

Inverted logic cellsVdd


Since no space is automatically reserved for routing, this scheme allows for high-density of placement of cellsThe main drawback is that the connection between rows must be accomplished by using Metal2 or higher

10

High-Density TechniquesMOS transistor placement

VPMOS transistors

Vdd

Vss

nWell

P-substrate

P-substrate

PMOS transistors

NMOS transistors

NMOS transistors


Vdd

nWell

PMOS transistors

PMOS transistors

Port PlacementAn example of the port placement in a cell

Metal1 output

Metal1 input

Vdd


To routing channel

Vss

11

MOS Sizing in Physical DesignA minimum-size MOS transistor is the smallest transistor that can be created using the design rule setScaling of the unit transistor

L L

L

W 2W4W

X 2X 4X


W

L L

2WX 2X

Physical Designs of Complex Gates

C D Vdd

AZ

B

A B

C D

C

z

Vdd

Vss


Dss

A B C D

12

Physical Design of XNOR Gate (1)AB Z

Z’

z

Vdd

Z’Z’A

B

A B


Vss

A B

Z’

Physical Design of XNOR Gate (2)

AB

Z

z

VddVss

B


A

13

Automation of Physical Design

AB

ED C

E

A B EDC

Vdd

E

Vdd

Vss

A BED C A BED C

P


Vss

P

N

Standard-Cell Physical Design

WVdd

Wp

Dnp


Wn

WVssa b c zd

14

Standard-Cell Physical Design

Vdd Vdd


Vss Vss

a b c a b c zz

Gate-Array Physical Design

Vdd


Vss

15

Gate-Array Physical Design

Vdd

Gate array cells


Vss

Routing channels

Sea-of-Gate Physical Design

Vdd supply

well contacts

P-transistors

poly gates

P-transistors


Vss supply

substrate contacts

N-transistors

16

Sea-of-Gate Physical Design

a b c

za b c z


a b c

CMOS Layout GuidelinesRun VDD and VSS in metal at the top and bottom of the cellRun a vertical poly line for each gate inputp y g pOrder the poly gate signals to allow the maximal connection between transistors via abutting source-drain connectionPlace n-gate segments close to VSS and p-gate segments close to VDD


gm DD

Connection to complete the logic gate should be made in poly, metal, or, where appropriate, in diffusion

17

Guidelines for Improving Density

Better use of routing layers – routes can occurs over cellsMore “merged” source-drain connectionsMore merged source drain connectionsMore usage of “white” space in sparse gatesUse of optimum device sizes – the use of smaller devices leads to smaller layouts


Vary the size of the transistor according to the position in the structure

Layout Optimization

clkVdd

F

A<0>A<1>

A<2>A<3>

F

Vss


In submicron technologies, where the source/drain capacitances are less, such that this improvement is limited

A<0>A<1>A<2>A<3>clk

18

Layout Optimization

DB

A

D

BC

2

Z

A

C

Z

Vdd

Right Wrong

D

1


Z

A B C DVss

A B C D

Right g

Layouts of Transmission Gates


19

Routing to Transmission Gates


2-Input Multiplexer

a

b

c

z

c

-c a bz


c -c

20

Design Hierarchies

Layout level

cell1 cell2 celln Cell library

Module 1

SubsystemsModule m


Chips

Module 1

Module 2Module 3

Module 4

Module 5

Module 6

Summary

Basic physical design concepts have been introducedCell concepts have also presentedCell concepts have also presentedLayout optimization guidelines have been summarizedDesign hierarchy has been briefly introduced


1

Chapter 6 Chapter 6 Combinational CMOS Combinational CMOS

Circuit and Logic DesignCircuit and Logic DesignCircuit and Logic DesignCircuit and Logic Design

Jin-Fu LiAdvanced Reliable Systems (ARES) LaboratoryAdvanced Reliable Systems (ARES) Laboratory


Jhongli, Taiwan

Advanced CMOS Logic DesignI/O Structures

Outline


2

Pseudo-NMOS LogicA pseudo-NMOS inverter

DDV

Fβ p

The low output voltage can be calculated as

A

TimeLVβ n

for

2|)|(2

)( tpDDP

LtnDDn VVVVV −=−ββ

βttptn VVV =−=


Thus VL depends strongly on the ratio The logic is also called ratioed logic

)(2 TDD

n

PL VVV −=

ββ

np ββ /

An N-input pseudo-NMOS gatePseudo-NMOS Logic

Vout

Features of pseudo-NMOS logicAdvantages

Low area cost only N+1 transistors are needed for an N-

inputsNMOS

network


yinput gateLow input gate-load capacitance Cgn

DisadvantageNon-zero static power dissipation

3

An example of XOR gate realized with pseudo-NMOS logic

The XOR is defined by

Pseudo-NMOS XOR Gate

XY

21212121212121 XXXXXXXXXXXXXXY ++=+=+=⊕=

X


X1 X2

GoalsNoise marginPower consumptionSpeed

Choosing Transistor Sizes

SpeedNoise margin

It is affected by the low output voltage (VL)VL is determined by

SpeedThe larger the W/L of the load transistor the faster

np ββ /


The larger the W/L of the load transistor, the faster the gate will be, particularly when driving many other gates Unfortunately, this increases the power dissipation and the area of the driver network

4

Power dissipationA pseudo-NMOS logic gate having a “1” output has no static (DC) power dissipation. However a pseudo NMOS gate having a “0” output


However, a pseudo-NMOS gate having a 0 output has a static power dissipation

The static power dissipation is equal to the current of the PMOS load transistor multiplied by the power supply voltage. Thus, the power is given by

ddtpgsPoxp

dc VVVL

WCP 2)()(

2−=

μ


The large PMOS results in large power dissipationPower-reduction methods

Select an appropriate PMOSIncrease the bias voltage of PMOS

A simple procedure for choosing transistor sizes of pseudo-NMOS logic gates

The relative size (W/L) of the PMOS load transistor is chosen as a compromise between speed and size versus


mp m ppower dissipationOnce the size of the load transistor has been chosen, then a simple procedure can be used to choose the W/Ls of the NMOS transistors in the NMOS network

Let (W/L)eq be equal to one-half of the W/L of the PMOS load transistor


PMOS load transistorFor each transistor Qi, determine the maximum number of drive transistors it will be in series, for all possible inputs. Denote this number ni.Take (W/L)i=ni(W/L)eq

5

Choose appropriate sizes for the pseudo-NMOS logic gate shown below

(W/L)8 is 5 um/0.8 um(W/L) is (5/0 8)/2=3 125

An Example

(W/L)eq is (5/0.8)/2=3.125Gate lengths of drive transistors are taken at their minimum 0.8umThus we can obtain

X1 X2 X4

YQ1 Q2 Q4

Q8 5/0.8

Q1

Q2.5um/0.8um5 0um/0 8um

Transistor Size


X3 X6

X5

X7

Q3 Q6

Q5

Q7

Q2

Q4

Q3

Q6

Q5

Q7

5.0um/0.8um5.0um/0.8um10um/0.8um10um/0.8um

10um/0.8um10um/0.8um

To eliminate the static power dissipation of pseudo-NMOS logic

An alternative technique is to use dynamic prechargingcalled dynamic logic as shown below

Dynamic Logic

called dynamic logic as shown below

Vout

inputsNMOS

network

PR


Normally, during the time the output is being precharged, the NMOS network should not be conducting

This is usually not possible

6

Another dynamic logic technique

Dynamic Logic

Vout

inputsNMOS

network

CLK

Precharge

Evaluate

CLK


Two-phase operation: precharge & evaluateThis can fully eliminate static power dissipation

Two examples

Examples of Dynamic Logic

clk

A B

C Z=(A+B).C

clk

A

B

C

Y=ABC


clk clk

7

Two major problems of dynamic logicCharge sharing Simple single-phase dynamic logic can not be cascaded

Problems of Dynamic Logic

Charge sharing

C 1 C 1C 2

1

1

clk=1A

C

B C

A1 2( )DD ACV C C C V

C= + +


C 2

11

0

clk=1

C

charge sharing model

1 2A DD

CV VC C C

=+ +

E.g., if 1 2 0.5C C C= =then output voltage isVDD/2

Problems of Dynamic LogicSimple single-phase dynamic logic can not be cascaded

N1 N2

N1

Td1

N2

N LogicN Logic

clock

inputs

clock

Erroneous State


Td2

8

Domino logic can be cascadedThe basic structure of domino logic

CMOS Domino Logic

Vout

inputsNMOS

network

CLK


Some limitations of this structureEach gate must be bufferedOnly noninverting structures are possible

An example of cascaded domino logics

A Domino Cascade

Stage 1 Stage 2 Stage 3

Vout

CLK

NMOSnetwork

NMOSnetwork

NMOSnetwork


precharge evaluate

9

The domino cascade must have an evaluation interval that is long enough to allow every stage time to discharge

Charge-Keeper Circuits

allow every stage time to dischargeThis means that charge sharing and charge leakage processes that reduce the internal voltage may be limiting factors

Two types of modified domino logics can cope with this problem


cope with this problemStatic versionLatched version

Modified domino logics

Charge-Keeper Circuits

Weak PMOS Weak PMOS

N-logicBlock

Z

Inputs

Clk

N-logicBlock

Z

Inputs

Clk


The aspect ratio of the charge-keeper MOS must be small so that it does not interfere with discharge event

Static version

Clk

Latched version

Clk

10

In a complex domino gate, intermediate nodes have been provided with their own precharge transistor

Complex Domino Gate

N-logic

F

N-logic N-logic


CLK

N-logic

Multiple-output domino logic (MODL) allows two or more outputs from a single logic gateThe basic structure of MODL

Multiple-Output Domino Logic

A

F1

F2


BF2

CLK

11

A Multiple-Output Domino Logic Gate

DCBA ⊕⊕⊕F1D’D

BA⊕

F2

D’

F3

D

C’C CC

B B’ BB’

CBA ⊕⊕


A A’

CLK

A further refinement of the domino logic is shown below

The domino buffer is removed, while

NP Domino Logic

The domino buffer is removed, while cascaded logic blocks are alternately composed of P- and N-transistors

CLK -CLK CLK


N-logic P-logic N-logic

Other P blocks Other N blocks

12

NP domino logic with multiple fanouts

NP Domino Logic

Other P blocksOther N blocks

N-logic

CLK

P-logic

-CLK

N-logic

CLK


Other P blocks Other N blocks

Advanced CMOS Logic Design

Pass-Transistor Logic


13

Model for pass transistor logic

Pass-Transistor Logic

Control signalsPi

The product term

Pass signalsVi

Product term (F)


F=P1V1+P2V2+…+PnVn

The pass variables can take the values {0,1,Xi,-Xi,Z}, where Xi and –Xi are the true and complement of the ith input variable and Z is the high-impedance

Different types of pass-transistor logics for two-input XNOR gate implementation

Pass-Transistor Logics

A

-B

B

-A OUT

-B

B

A

-A

OUTB

A

OUT


A

Complementary Single-polarity Cross-coupled

14

Modifying NMOS pass-transistor logic so full-level swings are realized

Full-Swing Pass-Transistor Logic

B

A

Y


Adding the additional PMOS has another advantages

It adds hysteresis to the inverter, which makes it less likely to have glitches

Features of the differential logic designLogic inversions are trivially obtained by simply interchanging wires without incurring a time delayTh l d t k ill ft i t f t

Differential Logic Design

The load networks will often consist of two cross-coupled PMOS only. This minimizes both area and the number of series PMOS transistors

DisadvantageTwo wires must be used to represent every signal, the interconnect area can be significantly greater. In applications in which only a few close gates are being


applications in which only a few close gates are being driven, this disadvantage is often not as significant as the advantages

Thus differential logic circuits are often a preferable consideration

15

One simple and popular approach for realizing differential logic circuit is shown below

The inputs to the drive network come in pairs, a single-ended signal and its inverse

A Fully Differential Logic Circuit

ended signal and its inverseThe NMOS network can be divided into two separate networks, one between the inverting output and ground, and a complementary network between the noninverting output and ground


Fully DifferentialNMOS Network

Vout+Vout

-

V1

V1

Vn

Vn

+-

+-

Differential CMOS realizations of AND and OR functions

Examples

AB

BA

B

A

AB A+B

B

A

BA

A+B


B

16

Differential CMOS realization of the function Vout=(A+B’)C+A’E

Examples

A

CB

C

Vout Vout

E

BA

E

A


B

A

A A

Differential split-level (DSL) logicA variation of fully differential logicA compromise between a cross-coupled load with no d c power dissipation and a continuously on load with

Differential Split-Level Logic

d.c. power dissipation and a continuously-on load with d.c. power dissipation

Vout+Vout

-

V- V+

VrefVref


DifferentialNMOS Network

V1

V1

Vn

Vn

+-

+-

V V

17

Features of DSL logicThe loads have some of the features of both continuous loads and cross-coupled load

Both outputs begin to change immediately

Differential Split-Level Logic

Both outputs begin to change immediatelyThe loads do have d.c. power dissipation, but normally much less than pseudo-NMOS gates and dynamic power dissipation

The nodes V+, V-, and all internal nodes of the NMOS network have voltage changes between greater than 0V and Vref-Vtn


This reduced voltage swing increases the speed of the logic gates

The maximum drain-source voltage across the NMOS transistors is reduced by about one-half

This greatly minimizes the short-channel effects

It is not necessary to wait until one side goes to low before the other side goes high

Pass-transistor networks for most required logic functions exist in which both sides of the cross

Differential Pass-Transistor Logic

functions exist in which both sides of the cross-coupled loads are driven simultaneouslyThis minimizes the time from when the inputs changes to when the low-to-high transition occurs

V +


Pass-TransistorNetwork

Vout+Vout

-

V1

V1

VnVn

+-

+-

18

Other features of pass-transistor logicIt removes the ratio requirements on the logic and has guaranteed functionalityThe cross coupled loads restore signal levels to

Differential Pass-Transistor Logic

The cross-coupled loads restore signal levels to full Vdd levels, thereby eliminating the voltage drop

Examples:

AB A B A+B


ABAB A+B

B+

A- A+A+

B-

A-

B-

A+ A- A-

B+

A+

A+B

A differential Domino logic gate

Dynamic Differential Logic

CLK


Vout+Vout

-

V1

V1

Vn

+-

+

CLK


n

Vn-

CLK

19

Features of dynamic Domino logicIts d.c. power dissipation is very small, whereas its its speed still quite good


p q gBecause of the buffers at the output, its output drive capability is also very goodOne of major limitations of Domino logic, the difficulty in realizing inverting functions, is eliminated because of the


,differential nature of the circuits

When the fan-out is small, the inverters at the output can be eliminated and the inputs to the charge-keeper transistors can be taken from the opposite output


taken from the opposite output

Differential

Vout+Vout

-

V1

V1

+-

CLK



V1

Vn

Vn

+-

CLK

20

Structure of a C2MOS gateIdeally, clocks are non-overlappingCLK=1, f is validCLK=0 the output is in a high impedance state During

Clocked CMOS (C2MOS)

X CLK=0CLK

CLK=0, the output is in a high-impedance state. During this time interval, the output voltage is held on Cout

PMOS Network

CLK

f

…


NMOS Network

CLK

VoutCout

f

+

-…

Examples of C2MOS Logic Gates

B

CLK

CLK

Cout

AB

A

AB

CLK

CLK

C

A+B

A

B


B

Cout

AB

21

The problem of charge leakageCause that the output node cannot hold the charge on Vout very long

Th b i f h l k h

D w f M L gGates

The basics of charge leakage are shown below

ni

pi

CLK=0

CLK=1

VoutCout

+

-

VddV1

VX

tht

V(t)

0

outi


dtdVCiii outpnout −=−=

dtCidV

out

out−=⇒

Assume iout is a constant IL

tCIVtVdt

CIdV

out

Lt

out

LtV

V−=⇒−= ∫∫ 10

)()(

1

Xhout

Lh Vt

CIVtV =−= 1)(

)( 1 XL

outh VV

ICt −=⇒

I/O PadsTypes of pads

Vdd, Vss padInput pad (ESD)O t t d (d i )Output pad (driver)I/O pad (ESD+driver)

All pads need guard ring for latch-up protectionCore-limited pad & pad-limited pad

Core-limited pad Pad-limited pad


PAD PAD

I/O circuitry I/O circuitry

Core limited pad p

22

ESD ProtectionInput pad without electrostatic discharge(ESD) protection

Input pad with ESD protection

PADAssume I=10uA, Cg=0.03pF, and t=1usThe voltage that appears on the gate is about 330volts


PAD

Tristate & Bidirectional PadsTristate pad

OUTP

OEoutput-enableOUTPNOE D

0 X 0 1 Z

Bidirectional pad

PADN

Ddata

011

X01

010

110

01


PAD

23

Schmitt Trigger Circuit Voltage transfer curve of Schmitt circuit

Vout

VDD

VinVT- VT+ VDD


Hysteresis voltage VH=VT+-VT-

When the input is rising, it switches when Vin=VT+

When the input is falling, it switches when Vin=VT-

Schmitt Trigger Circuit Voltage waveform for slow input

Vout

VDD Vin

Schmitt trigger turns a signal with a very

Time

VT-

VT+


slow transition into a signal with a sharp transition

24

Schmitt Trigger Circuit A CMOS version of the Schmitt trigger circuit

VFP

VDDP1

P3

When the input is rising, the VGS of the transistor N2 is given by VVV −=

Vout

N1

Vin

VFN

N2

P2

N3

P3


byWhen , N2 enters in conduction mode which means

Then

FNinGS VVV =2

+= Tin VV

TnGS VV =2

TnTFN VVV −= +

Summary

The following topics have been introduced in this chapter

CMOS Logic Gate DesignCMOS Logic Gate DesignAdvanced CMOS Logic DesignClocking StrategiesI/O Structures


1

Chapter 7 Chapter 7 Sequential CircuitsSequential CircuitsSequential CircuitsSequential Circuits

Jin-Fu LiAdvanced Reliable Systems (ARES) Lab.y ( )


Jungli, Taiwan

Latches & RegistersSequencing Timing Diagram

Outline


2

Sequencing Combinational logic

Output depends on current inputsSequential logicq g

Output depends on current and previous inputsRequires separating previous, current, futureCalled state or tokensEx: FSM, pipeline

clk clk clk clk


CLin out

CL CL

PipelineFinite State Machine

Sequencing ElementsLatch: Level sensitive

A.k.a. transparent latch, D latchFlip-flop: edge triggered

A.k.a. master-slave flip-flop, D flip-flop, D register

Timing DiagramsTransparentOpaque

D

Flop

Latc

h

Q

clk clk

D Q

clk


Edge-triggerD

Q (latch)

Q (flop)

3

Latches Negative-level sensitive latch

DQ

clk0

Positive-level sensitive latch

1

clkQ

D

clk


DQ

0

1

clk

clk

Q

D

RegistersPositive-edge triggered register (single-phase clock)

clk

0

1Q

Sclk

0

1S

DQM

QM

D

clk


Q

master slave

4

Registers Operations of the positive-edge triggered register

clk=0


clk=1

Registers CMOS circuit implementation of the positive-edge triggered register

D

Q


clk clk

5

Single-Phase Latch Positive active-static latch

D Q

-clk

1 Low area costD Q

clk

1. Low area cost2. Driving capability of

D must override the feedback inverter

-clk


D Q

clkclk

-clk

Typical Latch Symbolic Layouts

Vdd

D Q-clk

clk

clk

-clkD

Q


clk-clk

Vss

6

CVSL (Differential) Style Register The following figure shows latches based on a CVSL structure

An N and a P version are shown that are cascaded to form a register

D-QQ


clk

Q

Double-Edge Triggered Register The following figure shows latches that may be used to clock data on both edges of the clock

clk Latch 1clk

Latch 2

D -D

Q1 -Q1D -D

Q2 -Q2


clk

Q1clk

clk

Q2clk

7

Double-Edge Triggered Register Double-edge triggered register can be implemented by combining Latch 1 & Latch 2 as follows

Latch 2

-Q

Q

Q2

-Q2

D

-Q1


Latch 1

Q1clk

clk Latch 1 enabled Latch 2 enabled

Q2=-Q2=low Q1=-Q1=high

Asynchronously RegisterAsynchronously resettable register

-clk -reset

Q

clk

-clk

clk

-clk

-clk

clk

clk

D

Q


clk

-reset

Q

8

Asynchronously RegisterAsynchronously resettable and settable register

-clk -reset

clk

-clk

clk

-clk

-clk

clk

clk

D

Q


clkclk

-set

Dynamic Latches & RegistersDynamic single clock latches

clk

clkclk

Dynamic single clock registers

clk-clk

DDD

-clk-clk

-Q

clk -clk


D

-clk

-Q

clk

Qclk-clk

D-clkclk

Q

9

Dynamic LatchesClock active high latch

D X

Xn QnDn CLK

0 H 1 0

Clock active high latch with buffer

CLK

D X

Q110

HLL

0

1

1Xn-1 Qn-1

Qn-1


CLK

D X

-Q

Dynamic LatchesClock active low latch

CLK

D Xn QnDn CLK

0 L 1 0

Clock active low latch with buffer

X Q110

LHH

00

1

Xn-1

Qn-1

Qn-1

D


CLK

D

X -Q

10

Dynamic LatchesClock active high and low latches without feedback

DD X

The problem of leakage currentAssume that the capacitance of node X is 0.002pF and the leakage current I is 1nA

CLK

X Q

CLK Q


and the leakage current I is 1nATherefore, T=CV/I=0.002pFx5V/1nA=100usThat is, the latch needs to be refreshed each 100us. Otherwise, the output Q will become high

Sequencing Methods Flip-flops2-Phase LatchesPulsed Latches

Flip-Flops

Flop

Flop

clk

clk clk

Combinational Logic

Tc

FLa

tch

F

φ1

φ2

Latc

h

Latc

h

φ1 φ1φ2

2-Phase Transparent Latches

CombinationalLogic

CombinationalLogic

Tc/2

tnonoverlap tnonoverlap

Half-Cycle 1 Half-Cycle 1


φp

φp φp

Pulsed Latches

Combinational Logic

Latc

h

Latc

h

tpw

Half Cycle 1 Half Cycle 1

11

Timing Diagrams

A

Y

tpdCombinational

LogicA Y

tcdtpd Logic Prop. Delay

t L i C t D l

Contamination and Propagation Delays

FlopD Q

clk clk

D

Q

clk clk

tsetup thold

tccq

tpcq

tccq

tsetup tholdtpcq

tcd Logic Cont. Delay

tpcq Latch/Flop Clk-Q Prop Delay

tccq Latch/Flop Clk-Q Cont. Delay

tpdq Latch D-Q Prop Delay

tpcq Latch D-Q Cont. Delay

tsetup Latch/Flop Setup Time

thold Latch/Flop Hold Time


Latc

hD Q D

Q

tpdqtcdq

Max-Delay: Flip-Flops

clk clk

( )setup

sequencing overhead

pd c pcqt T t t≤ − +

F1 F2

clk

Combinational Logic

Tc

Q1 D2

tsetuptpcq


Q1

D2

tpd

12

Max Delay: 2-Phase Latches

Q1

L1 L2 L3

φ1 φ1φ2

CombinationalLogic 1


Q2 Q3D1 D2 D3

( )1 2

sequencing overhead

2pd pd pd c pdqt t t T t= + ≤ −

Tc

φ1

φ2

Q1

D1

tpd1

tpdq1


D2

Q2

D3

tpd2

tpdq2

Max Delay: Pulsed Latches

Q1 Q2D1 D2

φp φp

C bi i l L i 2

( )setup

sequencing overhead

max ,pd c pdq pcq pwt T t t t t≤ − + −

Tc

Q1

D2

D1

Combinational LogicL1 L2

(a) tpw > tsetup tpd

tpdq


φp

tpw

Q1

D2

(b) tpw < tsetup

Tctpcq

tpd tsetup

13

Min-Delay: Flip-Flops

holdcd ccqt t t≥ −

CL1

clk

Q1CL

clk

FF2

clk

D2


Q1

D2

tcd

thold

tccq

Min-Delay: 2-Phase Latches

1, 2 hold nonoverlapcd cd ccqt t t t t≥ − −

CLQ1

φ1

L1

Hold time reduced by nono erlap

D2

L

φ2

L2

φ1

φ2

tnonoverlap

tccq

nonoverlap

Paradox: hold applies twice each cycle, vs. only once for flops.

But a flop is made of two latches!


Q1

D2

tcd

thold

14

Min-Delay: Pulsed Latches

holdcd ccq pwt t t t≥ − +

Q1

φpHold time increased by pulse width

CL

D2

φp tpw

L1

φp

L2


Q1

D2

pw

tcd

thold

tccq

Time BorrowingIn a flop-based system:

Data launches on one rising edgeMust setup before next rising edgeIf it arrives late, system failsIf it arrives early, time is wastedFlops have hard edges

In a latch-based systemData can pass through latch while transparent


Long cycle of logic can borrow time into nextAs long as each loop completes in one cycle

15

Time Borrowing Example

φ1

φ2La

tch

Latc

h

Latc

h

Combinational Logic CombinationalLogic

Borrowing time acrosshalf-cycle boundary

Borrowing time acrosspipeline stage boundary

(a)

φ1 φ1

φ1

φ2

φ2


(b) Latc

h

Latc

hCombinational Logic Combinational

Logic

Loops may borrow time internally but must complete within the cycle

1 2

How Much Borrowing?

Q1

L1 L2

φ1 φ2

Combinational Logic 1Q2D1 D2

( )T2-Phase Latches

φ1

φ2

D2

Tc

Tc/2 Nominal Half-Cycle 1 Delay

tborrow

tnonoverlap

tsetup

( )borrow setup nonoverlap2cTt t t≤ − +

borrow setuppwt t t≤ −

Pulsed Latches


16

Clock SkewWe have assumed zero clock skewClocks really have uncertainty in arrival time

Decreases maximum propagation delayIncreases minimum contamination delayDecreases time borrowing


Skew: Flip-Flops

F1 F2

clk

clk clk

Combinational Logic

Tc

Q1 D2

ttpcq

( )setup skew

sequencing overhead

hold skew

pd c pcq

cd ccq

t T t t t

t t t t

≤ − + +

≥ − +Q1

D2

tskew

CLF1

clk

Q1

2

clk

D2

tsetup

pcq

tpdq

hold skewcd ccq


Q1

D2

F2

D2

clk

tskew

tcd

thold

tccq

17

Skew: Latches

Q1

L1

φ

L2 L3

φ1 φ1φ2



Q2 Q3D1 D2 D3( )sequencing overhead

2pd c pdqt T t≤ −

2-Phase Latches

φ1

φ2

( )

1 2 hold nonoverlap skew

borrow setup nonoverlap skew

,

2

cd cd ccq

c

t t t t t t

Tt t t t

≥ − − +

≤ − + +

( )setup skew

sequencing overhead

max ,pd c pdq pcq pwt T t t t t t≤ − + − +Pulsed Latches


( )hold skew

borrow setup skew

cd pw ccq

pw

t t t t t

t t t t

≥ + − +

≤ − +

Two-Phase ClockingIf setup times are violated, reduce clock speedIf hold times are violated, chip fails at any speedIn this class, working chips are most important

No tools to analyze clock skewAn easy way to guarantee hold times is to use


y y g2-phase latches with big nonoverlap timesCall these clocks φ1, φ2 (ph1, ph2)

18

Safe Flip-FlopIn class, use flip-flop with nonoverlapping clocks

Very slow – nonoverlap adds to setup timeBut no hold times

In industry, use a better timing analyzerAdd buffers to slow signals if hold time is at risk

D

φ2

X

Q

Q

φ1


D Q

φ1

φ2 φ1φ1

φ2

φ2

Clock DistributionIn a large CMOS chip, clock distribution is a serious problem

For example,Vdd=5VCreg=2000pF (20K register bits @ 0.1pF)Tclk=10nsTrise/fall=1nsIpeak=C(dv/dt)=(2000p)x(5/1n)=10APd=C(Vdd)2f=2000px25x100=5W


Methods for reducing the values of Ipeakand Pd

Reduce CInterleaving the rise/fall time

19

Clock DistributionClocking is a floorplanning problem because clock delay varies with position on the chipWays to improve clock distribution

Physical designMake clock delays more evenAt least more predictable

Circuit designMinimizing delays using several stages of drivers

Two most common types of physical clocking


Two most common types of physical clocking networks

H-tree clock distributionBalanced-tree clock distribution

H-Tree Clock Distribution


clock

20

H-Tree Clock Distribution


Source: Prof. Irwin

Balanced-Tree Clock Distribution

clock


21

Reduce Clocking PowerTechniques used to reduce the high dynamic power dissipation

Use a low capacitance clock routing line such as metal3. This layer of metal can be, for example, dedicated to y f m , f mp ,clock distribution onlyUsing low-swing drivers at the top level of the tree or in intermediate levels

C1 C2CA

Vdd

clkp -clkp


C3 C4CB

Gnd

Clock

Vout

clkn -clkn

Power & Ground Distribution


Source: Prof. Irwin

1

Chapter 8 Chapter 8 Introduction to 3D Introduction to 3D

Integration Technology Integration Technology g gyg gyusing TSVusing TSV

Jin-Fu LiD f El i l E i iDepartment of Electrical Engineering


Why 3D Integration An Exemplary TSV Process FlowSt ki St t i

Outline

Stacking StrategiesConcept of 3D IC DesignSummary


2

IC Technology Evolution

Chip

Single-chip kpackage

Printed wiring board(PCB)

Package

RF

AnalogFlash

CPU

Other Sensors,Imagers

Chemical &Bio Sensors

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU

3D-SIP

3D-IC Energy/Power

Processor

Memory Stack

RFADCDAC

NanoDeviceMEMS

Why 3D IntegrationIntegrating more and more transistors in a single chip to support more and more powerful functionality is a trend

Usi 2D i t ti t h l t im l m t s h Using 2D integration technology to implement such complex chips is more and more expensive and difficult

Some alternative technologies attempting to cope with the bottlenecks of 2D integration technology have been proposed


gy p p3D integration technology using through silicon via (TSV) has been acknowledged as one of the future chip design technologies

3

3D Integration Technology Using TSV

3D integration technology using TSVMultiple dies are stacked and TSV is used for the inter-die interconnection

Die 1Die 2

Die 3

TSV


The fabrication flow of a 3D IC Die/wafer preparationDie/wafer assembly

What is TSVThrough Silicon Via (TSV):

A via that goes through the silicon substrate Used for dies stacking

Top Bump

CMOS

Top Bump

Diameter

Al wiring TSVWiring layer

50 um or less


Typical TSV technologiesVia-first, via-middle, and via-last technologies

Top Bump

SiO2 insulatorVia made by laser

4

Via-First TSV

Via-First TSV Technology

(1) Before CMOS



Source: Yole, 2007.

Via-Last TSV

Via-Last TSV Technology

(1) After BEOL & before bonding

(2) After bonding


Source: Yole, 2007.

5

Step 1: A wafer with CMOS circuits

An Exemplary Via-Last Process Flow (1/6)

… …

MOSFET

…Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9

MOSFET MOSFET

Substrate

Ref ：ITRI

Step 2: via etching


… … …Via machining(by etching or laser dilling)


MOSFET MOSFET

Substrate

Ref ：ITRI

6

Step 3: via filling


… … …

Via filling


MOSFET MOSFET

Substrate

Ref ：ITRI

Step 4: wafer thinning


… … …


Wafer thinning

50 ~ 100 μm

Ref ：ITRI

7

Step 5: micro bump forming


Micro Bump

… … …Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13

Ref ：ITRI

Step 6: stacking


… …

TSV

Micro (μ) Bump

ABF(Ajinomoto Built-in Film)

… … …


… … …

Ref ：ITRI

8

An Exemplary 3D IC using Via-Last TSV

P-Substrate 3rd Chip

BondingAdhesive

BondingAdhesive

N Well N Well N Well

P-Substrate 2nd Chip

TSVN+ N+ N+ N+ N+ N+ N+P+P+P+P+P+


N Well N Well N Well

P-Substrate 1st Chip

TSVN+ N+ N+ N+ N+ N+ N+P+P+P+P+P+

3-Tier 3D IC Cross-Section


Source: E. G. Friedman, University of Rochester.

9

Die/Wafer AssemblyBonding technologies for 3D ICs

Wafer-to-wafer (W2W), Die-to-Wafer (D2W), and Die-to-Die (D2D)

Comparison of different bonding technologies

D2D D2W W2W


YieldFlexibilityProduction Throughput

HighHighLow

HighGoodGood

LowPoorHigh

Stacking Strategies

μ Bump

TSV

μ Bump μ Bump

Metal

Active Si

Bulk Si

D2D Vias

Die2

Die1


Lewis, D.L. et al, “A ScanIsland Based Design Enabling Prebond Testability in DieStacked Microprocessors,” in proc. IEEE International Test Conference (ITC), 2007, pp. 1-8

Bulk Si

face-to-face back-to-back face-to-back

10

Fabrication Steps for Face-to-Face Stacking

Die2Die2

Die211 22 33 44 55

Metal

Active Si

Bulk Si

Di 1 Di 2

Metal

Active Si

Bulk Si

Di 1 Di 2

Metal

Active Si

Bulk Si

Metal

Active Si

Bulk Si

Metal

Active Si

Bulk Si


Die1 Die2 Die1Die1 Die2 Die1 Die1

Loh, Gabriel H. et al, “Processor Design in 3D Die-Stacking Technologies,” in IEEE Micro, vol.27, issue 3, pp. 31-48, 2007

Fabrication Steps for Face-to-Back Stacking

Die2 Die211 22 33 44 55

Metal

Active Si

Bulk Si

Die1 Die2

Metal

Active Si

Bulk Si

Die1 Die2

Metal

Active SiBulk Si

Die1 Die2

Metal

Active Si

Bulk Si

Di 1

Metal

Active Si

Bulk Si

Di 1

Handle wafer


Die1 Die2 Die1 Die2 Die1 Die2 Die1 Die1


11

Electrical Characteristics of TSV

Capacitance of TSVTop Bump

Al wiring TSVWiring layer

CMOSDiameterTSV Length

Dielectric Thickness

TSV Dia[um]

TSV DielThk [nm]

TSV Length[um]

Cap [fF]


[ ] [ ] [ ]5 50 20 239.5

5 100 20 135.2

10 50 20 496.4

10 100 20 288.3

Source: Proceedings of IEEE, pp. 101, Jan. 2009

RC Characteristics of TSV

Die1

Die2~ 0.35*RCviastacka

1 FO4 = 22 ps(BSIM 70nm)

… …

Die1

M2

M9

via9

via2RCviastack

D2D

via

1-mm top-level metal

4x minimum size

225 ps> 11 FO4


MOSFET

M1

via1 F2F D2D via8 ps

~ 1/3*FO4


12

Benefits of 3D integration over 2D integration

High functionalityH h f

Benefits of 3D Integration

High performanceSmall form factorLow energy



High Functionality

Heterogeneous integrationCombine disparate technologies Other

Sensors,

Chemical &Bio Sensors

DRAM, flash, RF, etc.Combine different technology nodes

E.g., 65nm technology and 45nm technology Memory Stack

RFADCDAC

NanoDeviceMEMS

Imagers


Energy/Power

Processor


13

High Performance

3D integration technology can reduce the length of the long interconnections using TSVFor example For example,

3 4

1 2

By

y

x x

y

1 2

B

x x

z


3 4

A

y y 3 4

A

L2D=x+2y L3D=x+y+z

High Bandwidth3D IC allows much more IO resources than 2D ICFor example, p ,

Stacking of processor and memory

Memory

CPU

Memory


CPU

Bandwidth is limited by IOs

CPU

Many TSVs are allowed for high bandwidth transportation

14

Low Energy

SOBEnergy

Package

RF

AnalogFlash

CPU

SIP

Analog

RF

3D-IC


CPU

Package

SRAM

Flash

Analog

Technology

3D IC Design Approaches

L2Multiple

CoresI$

D$tlb

robIdq

IFbpred

rfrs

CPUL2

L2

L2

aludec

stq

VDD

Function Unit Block (FUB)Entire Core


gndX

Y

Transistors (circuit) LevelLogic gates (FUB splitting)

15

2D RAM

k 0

Dec k 1

Dec k 2

Dec k 3

Dec

WordlinesBitlines

Blo

ck

WL

D

Mux & SA

Blo

c

WL

D

Mux & SA

Blo

c

WL

D

Mux & SA

Blo

c

WL

D

Mux & SAoc

k 4

L D

ec

Mux & SA

ock

4

L D

ecMux & SA

ock

4

L D

ec

Mux & SA

ock

4

L D

ec

Mux & SA

WL Pre-DecAddress input

Data output

WLs


Blo

WL

Blo

WL

Blo

WL

Blo

WL

128

256 BLsRAM Subarray

Y.-F. Tsai et al, “Design Space Exploration for 3-D Cache,” IEEE Transactions on Very Large Scale Integration (TVLSI), vol.16, issue 4, pp. 444-555, 2008

3D Wordline-Partitioned RAM

-2c -2c -2c 1cBlo

ck 0

-2

WL

Dec

Blo

ck 1

-2

WL

Dec

Blo

ck 2

-2

WL

Dec

Blo

ck 3

-2

WL

Dec

WLs

Blo

ck 0

-

WL

Dec

SA 0-2

WL Pre-Dec

Blo

ck 1

-

WL

Dec

SA 1-2

Blo

ck 2

-

WL

Dec

SA 2-2

Blo

ck 3

-

WL

Dec

SA 3-1

4-2

ec

SA 4-2

5-2

ec

SA 5-2

6-2

ec

SA 6-2

7-1

ec

SA 7-1

SA 0-2

WL Pre-DecAddress inputData output

SA 1-2 SA 2-2 SA 3-2

Blo

ck 4

-2

WL

Dec

SA 4-2

Blo

ck 5

-2

WL

Dec

SA 5-2

Blo

ck 6

-2

WL

Dec

SA 6-2

Blo

ck 7

-2

WL

Dec

SA 7-2


128

W

Blo

ck 4

WL

De

Blo

ck 5

WL

De

Blo

ck 6

WL

De

Blo

ck 7

WL

De

128 BLs


16

3D Bitline-Partitioned RAM

Block 0-2

WL

Dec

Block 1-2

WL

Dec

Block 2-2

WL

Dec

Block 3-2

WL

Dec

Block 0-2WL

Dec

Mux & SA

WL Pre-Dec

Block 1-2WL

Dec

Mux & SA

Block 2-2WL

Dec

Mux & SA

Block 3-1WL

Dec

Mux & SA

Block 4-1

WL

Dec

Mux & SA

Block 5-1W

L D

ec

Mux & SA

Block 6-1

WL

Dec

Mux & SA

Block 7-1

WL

Dec

Mux & SA

64 W

Ls

Mux & SA

WL Pre-DecAddress inputData output

Mux & SA Mux & SA Mux & SA

Block 4-2

WL

Dec

Mux & SA

Block 5-2W

L D

ec

Mux & SA

Block 6-2

WL

Dec

Mux & SA

Block 7-2

WL

Dec

Mux & SA


W W W W 6

256 BLs


Design Example: 3D RAM


Source: G. H. Loh, ISCA 2008

17

Design Example



Road Map of 3D Integration with TSVs



18

Summary

3D integration technology using TSV is one of future IC design technologiesI ff d h 2D It can offer many advantages over the 2D integration technologyHowever, there are some challenges should be overcome before volume-production of TSV-based 3D IC becomes possible


Documents

EE3032 Introduction to VLSI Design