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EE241
1
UC Berkeley EE241 B. Nikolić
EE241 - Spring 2001Advanced Digital Integrated Circuits
Lecture 17Power Delivery
Arithmetic Circuits
UC Berkeley EE241 B. Nikolić
Power Distribution Chapter 24, Design and analysis of Power
Distribution Networks by Blauuw, Panda and Chaudhury
S. Lin, N Chang, ISSCC Microprocessor Design Workshop 2001
EE241
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UC Berkeley EE241 B. Nikolić
Power Distribution• Power-Ground Design Challenges
» IR drop» L di/dt fluctuation» Electromigration
• Efficient P/G Analysis Techniques• Sufficient On-chip De-coupling Capacitance• Intrinsic De-coupling Capacitance Modeling• Active Power-Ground Stabilization
UC Berkeley EE241 B. Nikolić
Power Distribution Supply current is brought on
chip at specific locations» on the edge for most chips
which are peripherally bonded
» distributed over the area of the chip for area bonded (C4, solder ball) chips
Loads consume this current at different locations on the chip at different times
There is often a large parasitic inductance associated with each bond-wire or solder-ball (0.1-10nH)
Current is distributed from the bond pads to the loads on thin metal wires» 0.04Ω/ typical
Load currents may be very high» average current may be as
large as 20A for very hot chips (50W at 2.5V)
» peak current may be 4-5x this amount (100A!)
L di/dt of bond wire and IR drop across on-chip wires are often a major source of supply noise
From [Dally]
EE241
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UC Berkeley EE241 B. Nikolić
di/dt Trends di/dt increases roughly as I*f
P6Pentium® proc
486386286
8086
80858080
800840040.01
0.10
1.00
10.00
100.00
1,000.00
1970 1980 1990 2000 2010Year
Icc
(am
p)
P6Pentium® proc
486386
286
8086
80858080
80084004
1.E-041.E-031.E-021.E-011.E+001.E+011.E+021.E+031.E+041.E+051.E+061.E+07
1970 1980 1990 2000 2010Year
L(di
/dt)/
Vdd
UC Berkeley EE241 B. Nikolić
On-Chip Bypass Capacitors
• Much of the difference between peak and average current may be supplied by local, on-chip bypass (decoupling) capacitors
• Bypass capacitors are also critical in mitigating the effects of the supply bond-wire inductance
• Decoupling is done by all the devices, N-wells, and specific capacitors
• Capacitors need fuses to prevent manufacturing shorts, sizing for limited oscillations.
EE241
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UC Berkeley EE241 B. Nikolić
3x Reduction in Peak Current
0
00.1
0.3
J (A
/mm
2 )
1 2 3t (ns)
Capacitor mustsupply this charge
( )( )( )
22
2922
pF/mm26725.0
pC/mm67
pC/mm675.0101A/mm3.032
==∆
=
=×
= −
VVQC
Q
UC Berkeley EE241 B. Nikolić
Power Grid
Power grid of PPC 750Courtesy of IEEE Press, New York. 2000
EE241
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UC Berkeley EE241 B. Nikolić
Voltage Fluctuation
Courtesy of IEEE Press, New York. 2000
UC Berkeley EE241 B. Nikolić
Grid Resonance
Courtesy of IEEE Press, New York. 2000
EE241
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UC Berkeley EE241 B. Nikolić
Arithmetic Circuits
Chapter 10: High-Speed VLSI Arithmetic Units: Adders and Multipliers, by V. Oklobdzija
Selected journal publications Books:
» K. Hwang, "Computer Arithmetic : Principles, Architecture and Design", John Wiley and Sons, 1979.
» E. E. Swartzlander, “Computer Arithmetic” Vol. 1 & 2, IEEE Computer Society Press, 1990.
» S.Waser, M.Flynn, “Introduction to Arithmetic for Digital Systems Designers”, Holt, Rinehart and Winston 1982.
» I. Koren, Computer Arithmetic Algorithms,” Brookside 1998.» B. Parhami, “Computer Arithmetic,” Oxford 2000.
Basics from Rabaey’s Digital ICs
UC Berkeley EE241 B. Nikolić
Full-Adder
A B
Cout
Sum
Cin Fulladder
EE241
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UC Berkeley EE241 B. Nikolić
The Binary Adder
S A B Ci⊕ ⊕⊕ ⊕⊕ ⊕⊕ ⊕=
A= BCi ABCi ABCi ABCi+ + +
Co AB BCi ACi+ +=
A B
Cout
Sum
Cin Fulladder
UC Berkeley EE241 B. Nikolić
Full Adder Implementation
Standard CMOS Multiplexer-based
Courtesy of IEEE Press, New York. 2000
EE241
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UC Berkeley EE241 B. Nikolić
Full Adder in DPL
UC Berkeley EE241 B. Nikolić
The Ripple-Carry AdderA0 B0
S0
Co,0Ci,0
A1 B1
S1
Co,1
A2 B2
S2
Co,2
A3 B3
S3
Co,3
(= Ci,1)FA FA FA FA
Worst case delay linear with the number of bits
tadder N 1–( )tcarry tsum+≈≈≈≈
td = O(N)
Goal: Make the fastest possible carry path circuit
EE241
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UC Berkeley EE241 B. Nikolić
Complimentary Static CMOS Full Adder
VDD
VDD
VDD
VDD
A B
Ci
S
Co
X
B
A
Ci A
BBA
Ci
A B Ci
Ci
B
A
Ci
A
B
BA
28 Transistors
UC Berkeley EE241 B. Nikolić
Inversion PropertyA B
S
CoCi FA
A B
S
CoCi FA
EE241
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UC Berkeley EE241 B. Nikolić
Minimize Critical Path by Reducing Inverting Stages
A0 B0
S0
Co,0Ci,0
A1 B1
S1
Co,1
A2 B2
S2
Co,2 Co,3FA’ FA’ FA’ FA’
A3 B3
S3
Odd CellEven Cell
Exploit Inversion Property
Note: need 2 different types of cells
UC Berkeley EE241 B. Nikolić
A Better Structure: The Mirror Adder
VDD
Ci
A
BBA
B
A
A BKill
Generate"1"-Propagate
"0"-Propagate
VDD
Ci
A B Ci
Ci
B
A
Ci
A
BBA
VDD
SCo
24 transistors
EE241
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UC Berkeley EE241 B. Nikolić
Carry-Skip Adder
FA FA FA FA
P0 G1 P0 G1 P2 G2 P3 G3
Co,3Co,2Co,1Co,0Ci,0
FA FA FA FA
P0 G1 P0 G1 P2 G2 P3 G3
Co,2Co,1Co,0Ci,0
Co,3
Mul
tiple
xer
BP=PoP1P2P3
Idea: If (P0 and P1 and P2 and P3 = 1)then Co3 = C0, else “kill” or “generate”.
Bypass (Skip)
MacSorley, Proc IRE 1/61Lehman, Burla, IRE Trans on Comp, 12/61
UC Berkeley EE241 B. Nikolić
Carry-Skip Adder
Setup
CarryPropagation
Sum
Setup
CarryPropagation
Sum
Setup
CarryPropagation
Sum
Setup
CarryPropagation
Sum
Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15
Ci,0
Critical Path
( ) ( ) RCASKIPRCAd tktkNtkt 121 −+
−+−=
For N-bit adder with k-bit groups
EE241
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UC Berkeley EE241 B. Nikolić
Carry-Skip Adder
Courtesy of IEEE Press, New York. 2000
UC Berkeley EE241 B. Nikolić
Carry-Skip Adder
( ) SKIPRCAd tkNtkt
−+−= 212
Critical path delay with constant groups
N
tp
ripple adder
bypass adder
4..8
EE241
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UC Berkeley EE241 B. Nikolić
Carry-Skip Adder
Variable Group Length
Oklobdzija, Barnes, Arith’85
321 cNcctd ++=
UC Berkeley EE241 B. Nikolić
Carry-Skip Adder
Courtesy of IEEE Press, New York. 2000
EE241
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UC Berkeley EE241 B. Nikolić
Carry-Skip Adder
Variable Block Lengths
Oklobdzija, Barnes, Arith’85
UC Berkeley EE241 B. Nikolić
Manchester Carry Chain
P0
Ci,0
P1
G0
P2
G1
P3
G2
P4
G3 G4
φ
φ
VDD
Kilburn, et al, IEE Proc, 1959.
•Implement P with pass-transistors•Implement G with pull-up, kill (delete) with pull-down•Use dynamic logic to reduce the complexity and speed up
EE241
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UC Berkeley EE241 B. Nikolić
Sizing Manchester Carry Chain
R1
C1
R2
C2
R3
C3
R4
C4
R5
C5
R6
C6
Out
M0 M1 M2 M3 M4MC
Discharge Transistor
1 2 3 4 5 6
tp 0.69 Ci Rjj 1=
i∑
i 1=
N∑=
1 1.5 2.0 2.5 3.0k
5
10
15
20
25
Spee
d
1 1.5 2.0 2.5 3.0k
0
100
200
300
400
Area
Speed (normalized by 0.69RC) Area (in minimum size devices)
UC Berkeley EE241 B. Nikolić
Manchester Chain with Carry-Skip
P0
Ci,0
P1
G0
P2
G1
P3
G2
BP
G3
BP
Co,3
Delay model:
EE241
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UC Berkeley EE241 B. Nikolić
PTL with SA-F/F Implementation
Matsui,JSSC 12/94