EE2174: Digital Logic and Lab

EE2174: Digital Logic EE2174: Digital Logic and Laband Lab

Professor Shiyan HuProfessor Shiyan Hu

Department of Electrical and Computer Department of Electrical and Computer EngineeringEngineering

Michigan Technological UniversityMichigan Technological University

Encoder and DecoderEncoder and Decoder

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Overview of Encoder and Overview of Encoder and DecoderDecoder

MUX GateMUX Gate Rudimentary functionsRudimentary functions Binary DecodersBinary Decoders

ExpansionExpansion Circuit implementationCircuit implementation

Binary EncodersBinary Encoders Priority EncodersPriority Encoders

MultiplexerMultiplexer ““ Selects” binary information from one of Selects” binary information from one of

many input lines and directs it to a single many input lines and directs it to a single output line.output line.

Also know as the “selector” circuit,Also know as the “selector” circuit, Selection is controlled by a particular set Selection is controlled by a particular set

of inputs lines whose # depends on the # of inputs lines whose # depends on the # of the data input lines.of the data input lines.

For a 2For a 2nn-to-1 multiplexer, there are 2-to-1 multiplexer, there are 2nn data data input lines and input lines and n n selection lines whose bit selection lines whose bit combination determines which input is combination determines which input is selected.selected.

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Combinational LogicPJF - 3

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Multiplexer (cont.)Multiplexer (cont.)

2-2-to-1-Line Multiplexerto-1-Line Multiplexer Since 2 = 2Since 2 = 211, n = 1, n = 1 The single selection variable S has two values:The single selection variable S has two values:

S = 0 selects input IS = 0 selects input I00

S = 1 selects input IS = 1 selects input I11

The equation:The equation:

Y = S’ IY = S’ I00 + SI + SI11

The circuit:The circuit:

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S

I0

I1

DecoderEnablingCircuits

Y

Example: 4-to-1 MUX using Cell Example: 4-to-1 MUX using Cell Library Based DesignLibrary Based Design

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4–to–1-Line Multiplexer using Transmission Gates

MUX as a Universal GateMUX as a Universal Gate We can construct AND and NOT gates We can construct AND and NOT gates

using 2-to-1 MUXs. Thus, 2-to-1 MUX is a using 2-to-1 MUXs. Thus, 2-to-1 MUX is a universal gate. universal gate.

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PJF - 8Combinational Logic

z = 0x + 1x’ = x’z = 0x + 1x’ = x’ z = xz = x11xx00 + 0x + 0x00’ = x’ = x11xx00

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Until now, we have examined single-Until now, we have examined single-bit data selected by a MUX. What if bit data selected by a MUX. What if we want to select m-bit data/words?we want to select m-bit data/words? Combine MUX blocks in parallel Combine MUX blocks in parallel with common select and enable with common select and enable signalssignals

Example: Construct a logic circuit Example: Construct a logic circuit that selects between 2 sets of 4-bit that selects between 2 sets of 4-bit inputs (see next slide for solution).inputs (see next slide for solution).

Multiple Bit SelectionMultiple Bit Selection

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Example: Quad 2-to-1 MUXExample: Quad 2-to-1 MUX Uses four 4-to-1 Uses four 4-to-1

MUXs with common MUXs with common select (S) and enable select (S) and enable (E).(E).

Select line chooses Select line chooses between Abetween Aii’s and ’s and BBii’s. The selected ’s. The selected four-wire digital four-wire digital signal is sent to the signal is sent to the YYii’s’s

Enable line turns Enable line turns MUX on and off (E=1 MUX on and off (E=1 is on).is on).

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Implementing Boolean Implementing Boolean functions with Multiplexersfunctions with Multiplexers

Any Boolean function of Any Boolean function of nn variables variables can be implemented using a 2can be implemented using a 2nn-1-1-to-1 -to-1 multiplexer. A MUX is basically a multiplexer. A MUX is basically a decoder with outputs ORed together, decoder with outputs ORed together, hence this isn’t surprising.hence this isn’t surprising.

The SELECT signals generate the The SELECT signals generate the minterms of the function.minterms of the function.

The data inputs identify which The data inputs identify which minterms are to be combined with an minterms are to be combined with an OR.OR.

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ExampleExample•F(X,Y,Z) = X’Y’Z + X’YZ’ + XYZ’ + XYZ = Σm(1,2,6,7)•There are n=3 inputs, thus we need a 2222-to-1 MUX-to-1 MUX•The first n-1 (=2) inputs serve as the selection linesThe first n-1 (=2) inputs serve as the selection lines

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Efficient Method for Efficient Method for implementing Boolean implementing Boolean

functionsfunctions For an For an nn-variable function (-variable function (e.ge.g., f(A,B,C,D)):., f(A,B,C,D)): Need a 2Need a 2nn-1-1 line MUX with line MUX with nn-1 select lines.-1 select lines. Enumerate function as a truth table with consistent Enumerate function as a truth table with consistent

ordering of variables (ordering of variables (e.g.e.g., A,B,C,D), A,B,C,D) Attach the most significant Attach the most significant nn-1 variables to the -1 variables to the nn-1 -1

select lines (select lines (e.g.e.g., A,B,C), A,B,C) Examine pairs of adjacent rows (only the least significant Examine pairs of adjacent rows (only the least significant

variable differs, variable differs, e.g.e.g., D=0 and D=1)., D=0 and D=1). Determine whether the function output for the (A,B,C,0) Determine whether the function output for the (A,B,C,0)

and (A,B,C,1) combination is (0,0), (0,1), (1,0), or (1,1).and (A,B,C,1) combination is (0,0), (0,1), (1,0), or (1,1). Attach 0, D, D’, or 1 to the data input corresponding to Attach 0, D, D’, or 1 to the data input corresponding to

(A,B,C) respectively.(A,B,C) respectively.

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The Other ExampleThe Other Example

Consider F(A,B,C) = Consider F(A,B,C) = m(1,3,5,6). We m(1,3,5,6). We can implement this function using a can implement this function using a 4-to-1 MUX as follows.4-to-1 MUX as follows.

The index is ABC. Apply A and B to The index is ABC. Apply A and B to the Sthe S11 and S and S00 selection inputs of the selection inputs of the MUX (A is most sig, SMUX (A is most sig, S11 is most sig.) is most sig.)

Enumerate function in a truth table.Enumerate function in a truth table.

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MUX Example (cont.)MUX Example (cont.)

AA BB CC FF

00 00 00 00

00 00 11 11

00 11 00 00

00 11 11 11

11 00 00 00

11 00 11 11

11 11 00 11

11 11 11 00

When A=B=0, F=CWhen A=B=0, F=C

When A=0, B=1, When A=0, B=1, F=CF=CWhen A=1, B=0, When A=1, B=0, F=CF=CWhen A=B=1, When A=B=1, F=C’F=C’

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MUX implementation of MUX implementation of F(A,B,C) = F(A,B,C) = m(1,3,5,6)m(1,3,5,6)

AA

BB

CC

CC

CC

C’C’

FF

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A larger ExampleA larger Example

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Rudimentary FunctionsRudimentary Functions

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SelectionSelection

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EnablingEnabling

““gating” ?gating” ?

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The Other Code ConverterThe Other Code ConverterBCD-to-Seven-Segment BCD-to-Seven-Segment

ConverterConverter Seven-segment display:Seven-segment display:

7 LEDs (light emitting diodes), each one 7 LEDs (light emitting diodes), each one controlled by an inputcontrolled by an input

1 means “on”, 0 means “off”1 means “on”, 0 means “off” Display digit “3”?Display digit “3”?

Set a, b, c, d, g to 1Set a, b, c, d, g to 1 Set e, f to 0Set e, f to 0

d

a

b

c e

f g

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BCD-to-Seven-Segment BCD-to-Seven-Segment ConverterConverter

Input is a 4-bit BCD code Input is a 4-bit BCD code 4 inputs 4 inputs (w, x, y, z).(w, x, y, z).

Output is a 7-bit code (a,b,c,d,e,f,g) Output is a 7-bit code (a,b,c,d,e,f,g) that allows for the decimal equivalent that allows for the decimal equivalent to be displayed.to be displayed.

Example: Example: Input: 0000Input: 0000BCDBCD

Output: 1111110 Output: 1111110 (a=b=c=d=e=f=1, g=0)(a=b=c=d=e=f=1, g=0)

d

a

b

c e

f g

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BCD-to-Seven-Segment (cont.)BCD-to-Seven-Segment (cont.)Truth TableTruth Table

DigitDigit wxyzwxyz abcdefgabcdefg

00 00000000 11111101111110

11 00010001 01100000110000

22 00100010 11011011101101

33 00110011 11110011111001

44 01000100 01100110110011

55 01010101 10110111011011

66 01100110 X011111X011111

77 01110111 11100X011100X0

DigitDigit wxyzwxyz abcdefgabcdefg

88 10001000 11111111111111

99 10011001 111X011111X011

10101010 XXXXXXXXXXXXXX






??

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DecodersDecoders

A combinational circuit that converts A combinational circuit that converts binary information from binary information from nn coded coded inputs to a maximum 2inputs to a maximum 2n n coded coded outputs outputs n-to- n-to- 22nn decoderdecoder

n-to-mn-to-m decoder, decoder, m m ≤ ≤ 22nn Examples: BCD-to-7-segment Examples: BCD-to-7-segment

decoder, where decoder, where n=4n=4 and and m=10 m=10

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Decoders (cont.)Decoders (cont.)

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1-2 Decoder1-2 Decoder

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2-to-4 Decoder2-to-4 Decoder

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2-to-4 Active Low Decoder2-to-4 Active Low Decoder

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3-to-8 Decoder3-to-8 Decoder

ad

dre

ssad

dre

ss

data

data

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3-to-8 Decoder (cont.)3-to-8 Decoder (cont.)

Three inputs, AThree inputs, A00, A, A11, A, A22, are decoded into , are decoded into eight outputs, Deight outputs, D0 0 through Dthrough D77

Each output DEach output Dii represents one of the represents one of the minterms of the 3 input variables.minterms of the 3 input variables.

DDii = 1 when the binary number A = 1 when the binary number A22AA11AA00 = = ii Shorthand: DShorthand: Dii = m = mii

The output variables are The output variables are mutually mutually exclusiveexclusive; exactly one output has the ; exactly one output has the value 1 at any time, and the other seven value 1 at any time, and the other seven are 0.are 0.

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Decoder ExpansionDecoder Expansion

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Decoder with enableDecoder with enable

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AnyAny combinational circuit can be constructed combinational circuit can be constructed using decoders and OR gates! Why?using decoders and OR gates! Why?

Here is an example:Here is an example:Implement a full adder circuit with a decoder Implement a full adder circuit with a decoder and two OR gates.and two OR gates.

Recall full adder equations, and let X, Y, and Recall full adder equations, and let X, Y, and Z be the inputs:Z be the inputs: S(X,Y,Z) = X+Y+Z = S(X,Y,Z) = X+Y+Z = m(1,2,4,7) m(1,2,4,7) CC (X,Y,Z) = (X,Y,Z) = m(3, 5, 6, 7).m(3, 5, 6, 7).

Since there are 3 inputs and a total of 8 Since there are 3 inputs and a total of 8 minterms, we need a 3-to-8 decoder.minterms, we need a 3-to-8 decoder.

Implementing Boolean Implementing Boolean functions using decodersfunctions using decoders

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Implementing a Binary Adder Using a Decoder

S(X,Y,Z) = SUM m(1,2,4,7)

C(X,Y,Z) = SUM m(3,5,6,7)

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EncodersEncoders

An encoder is a digital circuit that An encoder is a digital circuit that performs the inverse operation of a performs the inverse operation of a decoder. An encoder has 2decoder. An encoder has 2nn input input lines and lines and nn output lines. output lines.

The output lines generate the binary The output lines generate the binary equivalent to the input line whose equivalent to the input line whose value is 1.value is 1.

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Encoders (cont.)Encoders (cont.)

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Encoder ExampleEncoder Example Example: 8-to-3 binary encoder (octal-to-binary)Example: 8-to-3 binary encoder (octal-to-binary)

A0 = D1 + D3 + D5 + D7

A1 = D2 + D3 + D6 + D7

A2 = D4 + D5 + D6 + D7

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Encoder Example (cont.)Encoder Example (cont.)

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Encoder Design IssuesEncoder Design Issues There are two ambiguities associated There are two ambiguities associated

with the design of a simple encoder:with the design of a simple encoder:1.1. Only one input can be active at any given Only one input can be active at any given

time. If two inputs are active simultaneously, time. If two inputs are active simultaneously, the output produces an undefined the output produces an undefined combination (for example, if Dcombination (for example, if D33 and D and D66 are 1 are 1 simultaneously, the output of the encoder will simultaneously, the output of the encoder will be 111.be 111.

2.2. An output with all 0's can be generated when An output with all 0's can be generated when all the inputs are 0's,or when Dall the inputs are 0's,or when D00 is equal to 1. is equal to 1.

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Priority EncodersPriority Encoders

Solves the ambiguities mentioned Solves the ambiguities mentioned above.above.

Multiple asserted inputs are allowed; Multiple asserted inputs are allowed; one has priority over all others.one has priority over all others.

Separate indication of no asserted Separate indication of no asserted inputs.inputs.

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Example: 4-to-2 Priority Example: 4-to-2 Priority EncoderEncoder

Truth TableTruth Table

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4-to-2 Priority Encoder 4-to-2 Priority Encoder (cont.)(cont.)

The operation of the priority encoder The operation of the priority encoder is such that:is such that:

If two or more inputs are equal to 1 at If two or more inputs are equal to 1 at the same time, the input in the the same time, the input in the highest-numbered position will take highest-numbered position will take precedence.precedence.

A A valid output indicatorvalid output indicator, , designated by V, is set to 1 only when designated by V, is set to 1 only when one or more inputs are equal to 1. V one or more inputs are equal to 1. V = D= D33 + D + D22 + D + D11 + D + D00 by inspection. by inspection.

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Example: 4-to-2 Priority Example: 4-to-2 Priority EncoderEncoderK-MapsK-Maps

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Example: 4-to-2 Priority Example: 4-to-2 Priority EncoderEncoder

Logic DiagramLogic Diagram

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8-to-3 Priority Encoder8-to-3 Priority Encoder

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Uses of priority encoders Uses of priority encoders (cont.)(cont.)

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Link Between Multiplexer Link Between Multiplexer and Decoderand Decoder

Note the regions of the multiplexerNote the regions of the multiplexer 1-to-2-line Decoder1-to-2-line Decoder 2 Enabling circuits2 Enabling circuits 2-input OR gate2-input OR gate

In general, for an 2In general, for an 2nn-to-1-line multiplexer:-to-1-line multiplexer: nn-to-2-to-2nn-line decoder-line decoder 22nn AND gates AND gates

S

I0

I1

DecoderEnablingCircuits

Y

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Summary of Encoder and Summary of Encoder and DecoderDecoder

MUX GateMUX Gate Rudimentary functionsRudimentary functions Binary DecodersBinary Decoders

ExpansionExpansion Circuit implementationCircuit implementation

Binary EncodersBinary Encoders Priority EncodersPriority Encoders

Documents

EE2174: Digital Logic and Lab