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ELECTRICAL ENGINEERING DEPARTMENT
EE202
DIGITAL ELECTRONICS
NOT,AND,OR,NAND, and NOR GATES
PREPARED FOR:
MR. RABINDRA A/L GANDHI THAGARAJOO
PREPARED BY:
MUHD. AMIRUL MUKMININ BIN ZAKARIA 06DTK11F1017
AHMAD ARIFF FADHIL BIN SUHAIMI 06DTK11F1023
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DATE : 6/12/2012
EXPERIMENT : 1 (A)
SUBJECT : NOT,AND,OR,NAND and NOR gates.
OBJECTIVE(S) : - Recognise the Basic Logic Gates (NOT,AND,OR,NAND and NOR).
-To identify the operations of NOT,AND,OR,NAND and NOR gates according to
respective truth tables.
EQUIPMENT(S): Digital ICs (IC 74LS08,IC 74LS32,IC 74LS04,IC 74LS00 and IC 74LS02), Digital Trainer,
Single Core Wire, Breadboard/Prototyping board, Cutter and IC extractor.
THEORY :
Logic Gates
Electronic Gates require a high power supply Gates INPUT are driven by voltages having two nominal values.(0V representing logic 0,wheres
5V represents logic 1).
The OUTPUT of a gates provides two nominal values of voltage only.(In general, there is onlyone output to a logic gates).
The is always a time delay between an input being applied and output responding.Truth Table
Truth Table are used to represents the functions of specified logic gates.
Logic Gates Distinctive Shape Truth Table Description
AND -Require two inputs
and have one output.
-It only produces an
output of one when
both the inputs are 1,
otherwise the output
is 0.
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NOT -Also known as
inverter, because it
changes the input into
its opposite.
-Only accept one
input, the output is
opposite of the input
(in other words, a low
voltage input (0) is
converted to a high
voltage output).
OR -Has two input lines
and one output lines.
-Basically, if either or
both of the inputs are
one, the resulting
output value is a 1.
NAND -A NOT-AND gate
which is equal to an
AND followed by a
NOT gate.
-The output of all
NAND gates are high if
any of the inputs are
low.
-The small circle
represents inversion.
NOR -A NOT-OR gate which
is equal to an OR gate
followed by a NOT
gate.
-The outputs of all
NOR gates are low if
any of the inputs are
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high.
-The small circle
represents inversion.
Experiment Procedure 1:
NOT Gate (1a)
1. Digital Trainer are connected to the 220V AC power supply.2.
By using IC 74LS04, the circuit are connected:
Pin 1 Pin 2
SW 1
3. Connections to the IC consulting gate ICs data sheet and pin configuration diagram are made.4.
IC are being power up by applying +5 volts at pin 14 and grounding pin 7.
5. Data switch SW1 are set to logic 0, the results of L1 are stated in the truth table below.6. Data switch SW1 are then set to logic 1,and the output are verified.0 used to show low
input/output signal; while 1 used to show high input/output signal.
7. Truth Table are completed based on the experiment results.
Input SW 1
Output (L1)
Theory Practical
0 1 1
1 0 0
Table 1.1 : Truth Table for NOT gate
Experiment Procedure 2:
AND Gate (2a)
1. By using IC 74LS08, the circuit are connected:
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Input A (to SW 1) output (to L1)
Input B (to SW 2)
2. IC are connected by applying +5V at pin 14 and grounding pin 7.3. Data switch SW1 and SW2 are set to logic 0.The results are tabulated in the truth table below.4. Data switch SW1 are set to logic 0 while SW2 to logic 1.Results L1 shown in the truth table
below.
5. Data switch SW1 and SW2 are set following the truth table below. Output verified and truthtable are filled up.
Input Output (L1)
A = SW 1 B = SW 2 Theory Practical
0 0 0 0
0 1 0 0
1 0 0 0
1 1 1 1
Table 1.3 : Truth Table for AND gate
NAND Gate (2b)
1. By using IC 74LS00, the circuit are connected:SW 1 L1
SW 2
2. IC are connected by applying +5V at pin 14 and grounding pin 7.3. Data switch SW1 and SW2 are set to logic 0.The results are tabulated in the truth table below.
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4. Data switch SW1 are set to logic 0 while SW2 to logic 1.Results L1 shown in the truth tablebelow.
5. Data switch SW1 and SW2 are set following the truth table below. Output are verified and truthtable are filled up.
Input Output (L1)
A = SW 1 B = SW 2 Theory Practical
0 0 1 1
0 1 1 1
1 0 1 1
1 1 0 0
6. Table 1.5 : Truth Table for NAND gate
Experiment Procedure 3:
OR Gate (3a)
1. By using IC 74LS32, the circuit are connected:PIN 1 SW1 L1
PIN 2 SW 2 PIN 3
2. IC are connected by applying +5V at pin 14 and grounding pin 7.3. Data switch SW1 and SW2 are set to logic 0.The results are tabulated in the truth table below.4. Data switch SW1 are set to logic 0 while SW2 to logic 1.Results L1 shown in the truth table
below.
5. Data switch SW1 and SW2 are set following the truth table below. Output are verified and truthtable are filled up.
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Input Output (L1)
A = =SW 1 B = SW 2 Theory Practical
0 0 0 0
0 1 1 1
1 0 1 1
1 1 1 1
Table 1.8 : Truth Table for OR gate
NOR Gate (3b)
1. By using IC 74LS02, the circuit are connected:PIN 3 SW 1 L1
PIN 2 SW 2 PIN 1
2. IC are connected by applying +5V at pin 14 and grounding pin 7.3. Data switch SW1 and SW2 are set to logic 0.The results are tabulated in the truth table below.4. Data switch SW1 and SW2 are set following the truth table below. Output are verified and truth
table are filled up.
Input Output (L1)
A = SW 1 B = SW 2 Theory Practical
0 0 1 1
0 1 0 0
1 0 0 0
1 1 1 0
Table 1.10 : Truth Table for NOR gate
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DISCUSSION :
1. Based from the results of the experiments, NOT gate (inverter) truth table are not same asNAND and NOR gate truth table. This is because NOT gate in electronic circuit produces an
inverted version of the input at its output. If the input variable is A, the inverted output is known
as NOT A (also known as ).
2. Observation from the procedures are:-ICs used for every experiment to study a variety of Truth Table are different from one another.
-all ICs are powered by +5V at pin 14 and grounded at pin 7.
-excepts for NOT gate, all the ICs data switch SW1 and SW2 are set to logic 0.
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DATE : 13/1/2012
EXPERIMENT : 1(B)(Combinational Logic Gates)
OBJECTIVES : - Find out and identify the operation of Basic Logic Gates and their Truth Table.
- Create Logic Gates and circuit and truth table.- Fabricate the affiliation Logic Gates circuit and truth table from the Boolean
expressions.
EQUIPMENT(S): Digital ICs (IC 74LS08,IC 74LS32,IC 74LS04,IC 74LS00 and IC 74LS02), Digital Trainer,
Single Core Wire, Breadboard/Prototyping board, Cutter and IC extractor.
Procedure :
1. The circuit are connected as shown by using a appropriate ICs.SW1 L1 L2
SW2
L4
SW3 L3
SW4
2. SW1,SW2,SW3 and SW4 are tuned on to the origin position that suitable to the truth table 1.6 inpart 2 result and the output state are recorded.
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RESULT :
INPUT OUTPUT
SW1 SW2 SW3 SW4 L1 L2 L3 L4
Theory Practical Theory Practical Theory Practical Theory Practical
0 0 0 0 0 0 1 1 0 0 0 0
0 0 0 1 0 0 1 1 1 1 1 1
0 0 1 0 0 0 1 1 1 1 1 1
0 0 1 1 0 0 1 1 1 1 1 1
0 1 0 0 0 0 1 1 0 0 0 0
0 1 0 1 0 0 1 1 1 1 1 1
0 1 1 0 0 0 1 1 1 1 1 1
0 1 1 1 0 0 1 1 1 1 1 1
1 0 0 0 0 0 1 1 0 0 0 0
1 0 0 1 0 0 1 1 1 1 1 1
1 0 1 0 0 0 1 1 1 1 1 1
1 0 1 1 0 0 1 1 1 1 1 1
1 1 0 0 1 1 0 0 0 0 0 0
1 1 0 1 1 1 0 0 1 1 0 0
1 1 1 0 1 1 0 0 1 1 0 0
1 1 1 1 1 1 0 0 1 1 0 0
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DISCUSSION :
1. The truth table for 3 inputs AND gate:INPUT OUTPUT
A B C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
2. The truth table for 3 inputs NOR gate:INPUT OUTPUT
A B C Y
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
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3. Logical circuit base expression with truth table solution.
a. M = ( A . B ) + ( C + D )A
B M
C
D
Circuit Truth Table
INPUT OUTPUT
A. B C + D M = ( A . B ) + ( C + D )
0 0 0 0 0
0 1 0 1 1
1 0 0 1 1
1 1 1 1 1
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b. Z = ( M + N ) ( P. Q )M
N M
P
Q
Circuit Truth Table
INPUT OUTPUT
M + N P . Q Z = ( M + N ) ( P. Q )
0 0 1 0 0
0 1 0 1 0
1 0 0 0 0
1 1 0 0 0
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CONCLUSION :
1. Logic Gates is physical device implementing Boolean Function, as it performs a logical operationon one or more logic inputs and produces a single logic output.
2. Digital Electronics system are used to be constructed by using a Logic Gates. Thesegates are the AND,NOT,OR,NAND,NOR,EXOR and EXNOR (we only studying about
AND,NOT,OR,NOR and NAND).
3. With the aid from Truth Table, the basic operations of these Logic Gates can be described.4. Logic Gates are primarily implemented using diodes or transistors and acts as electronic
switches.
REFERENCE :
1.http://en.wikipedia.org/wiki/Logic_gate (12/1/2010,2013)
2.http://simple.wikipedia.org/wiki/Logic_gate (12/1/2012, 2015)
3.http://whatis.techtarget.com/definition/0,,sid9_gci213512,00.html (12/1/2012, 2019)
4.http://www.ee.surrey.ac.uk/Projects/Labview/gatesfunc/index.html5. (12/1/2012, 2025)
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