EE 435 - Iowa State Universityclass.ece.iastate.edu/ee435/lectures/EE 435 Lect 22 Spring 2012.pdf · EE 435 Lecture 22 Offset Voltages . How linear is the amplifier ? ... assume their

EE 435

Lecture 22

Offset Voltages

How linear is the amplifier ?

Vd

VEB1

IT

I

EB1V2

ID1

1% Linear =

0.3VEB1

IT

M1

M2

ID1 I

D2

V1

V2

VS

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-0.2 -0.1 0 0.1 0.2

Vd

I

IC1

1% linear = .56Vt

2Vt

Signal Swing and Linearity of Bipolar Differential Pair

IT

Q1 Q

2

IC1 I

C2

V1

V2

VE .

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Applications as a programmable OTA

gm

IABC

The current-dependence of the gm of the differential pair is often used to

program the transconductance of an OTA with the tail bias current IABC

MOS

m ABC OXW

g = I 2uCL

m OX EBW

g =uC VL

Two decade change in current for every

decade change in gm

One decade decrease in signal swing for

every decade decrease in gm

BJT

ABCm

t

Ig =

V

One decade change in current for every

decade change in gm

No change in signal swing when gm

Is changed

Limited gm adjustment possibility Large gm adjustment possible

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Linearity of Common-Source Amplifier

VSS

VDD

ViS

VOUT

IB

For convenience, will consider situation where current source biasing

Is ideal

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VSS

VDD

ViS

VOUT

IB1 2

OS iS iSEB EB

2 -

λV 2V

V V V

Is this a linear or nonlinear relationship?

-5

-4

-3

-2

-1

0

1

2

3

4

5

-0.025 -0.02 -0.015 -0.01 -0.005 0 0.005 0.01 0.015 0.02 0.025

VEB= 1V

λ=0.01Fit Line

Can’t see nonlinearity in this plot

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VSS

VDD

ViS

VOUT

IB

Is this common-source amplifier linear or nonlinear?

VSS

VDD

ViS

VOUT

IB

CL

IOUT

High-Gain Amplifier Transconductance Amplifier

The transconductance amplifier driving a load CL is performing as an integrator

gm

CL

ViS VOS

Integrators often used in filters where |VOS| is comparable to |ViS|

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VSS

VDD

ViS

VOUT

IB

Is this common-source amplifier linear?

VSS

VDD

ViS

VOUT

IB

CL

IOUT

M1M2


• Reasonably linear if used in high-gain applications and

VEB is large (e.g. if AV=gm/go=2/((λVEB)=100 and Vo=1V, Vin=10mV)

• Highly nonlinear when used in low-gain applications

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Linearity of Common-Emitter Amplifier

Is this common-emitter amplifier linear?


• Very linear if used in high-gain applications

(e.g. if AV=gm/g0=VAF/Vt=4000 and Vo=1V, Vin=250uV)

• Highly nonlinear when used in low-gain applications

VSS

ViS

VOUT

IB

CL

IOUT

Q1

VSS

ViS

VOUT

IB

CL

IOUT

Q1 RL

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• Systematic Offset Voltage

• Random Offset Voltage

Offset Voltage

VICQ

VOUT

Definition: The output offset voltage is the difference between the desired

output and the actual output when Vid=0 and Vic is the quiescent common-

mode input voltage.

OUTOFF OUT OUTDESV = V - V

Note: VOUTOFF is dependent upon VICQ although this dependence is

usually quite weak and often not specified

Two types of offset voltage:

Offset Voltage

Definition: The input-referred offset voltage is the differential dc input voltage

that must be applied to obtain the desired output when Vic is the quiescent

common-mode input voltage.

VICQ

VOUT

VOFF

Note: VOFF is usually related to the output offset voltage by the expression

OUTOFFOFF

C

VV =

ANote: VOFF is dependent upon VICQ although this dependence is

usually quite weak and often not specified

• Systematic Offset Voltage

• Random Offset Voltage

Offset Voltage

VICQ

VOUT

Two types of offset voltage:

After fabrication it is impossible (difficult) to distinguish between the

systematic offset and the random offset in any individual op amp

Measurements of offset voltages for a large number of devices will

provide mechanism for identifying systematic offset and statistical

characteristics of the random offset voltage

Systematic Offset Voltage

Offset voltage that is present if all device and model parameters

assume their nominal value

Easy to simulate the systematic offset voltage

Almost always the designer’s responsibility to make systematic

offset voltage very small

Generally easy to make the systematic offset voltage small

Random Offset Voltage

Due to random variations in process parameters and device dimensions

Random offset is actually a random variable at the design level but

deterministic after fabrication in any specific device

Distribution nearly Gaussian

Has zero mean

Characterized by its standard deviation or variance

Often strongly layout dependent

Due to both local random variations and correlated gradient effects

Will consider both effects separately

Gradient effects usually dominate if not managed

Good methods exist for driving gradient effects to small levels and will be

discussed later

In what follows it will be assumed that gradient effects have been managed

Gradient and Random Effect

Offset Voltage

VOS

Can be modeled as a dc voltage source in series with the input

Offset Voltage

VMt

VDD

VINVOUT

VIN VOUT

R2R1

Effects of Offset Voltage - an example

Desired I/O relationship

Offset Voltage

VMt

VDD

VINVOUT

VIN VOUT

R2R1

Effects of Offset Voltage - an example

Desired I/O relationship

VMt

VDD

VIN

VOUT

VM

t

VDD

VIN

VOUT

Actual I/O relationship due to offset

Offset Voltage

Effects can be reduced or eliminated by adding equal amplitude opposite

Dc signal (many ways to do this)

Widely used in offset-critical applications

Comes at considerable effort and expense

VOS

VOS

Prefer to have designer make VOS small in the first place

Effects of Offset Voltage

• Deviations in performance will change from one

instantiation to another due to the random component

of the offset

• Particularly problematic in high-gain circuits

• A major problem in many other applications

• Not of concern in many applications as well

Offset Voltage Distribution

1 2 3 4 5 6-1-2-3-4-5-6

number

Offset Voltage Bins

Typical histogram of random offset voltage (binned) after fabrication


1 2 3 4 5 6-1-2-3-4-5-6

number

Offset Voltage Bins

Gaussian

(Normal) pdf

Typical histogram of offset voltage (binned) after fabrication

Mean is nearly 0 (actually the systematic offset voltage)


1 2 3 4 5 6-1-2-3-4-5-6

number

Offset Voltage Bins

Typical histogram of offset voltage (binned) in shipped parts

Extreme offset parts have been sifted at test


Typical histogram of offset voltage (binned) in shipped parts

Low-offset parts sold at a premium

Extreme offset parts have been sifted at test

1 2 3 4 5 6-1-2-3-4-5-6

number

Offset Voltage Bins


x

0

Pdf of zero-mean Gaussian distribution

Characterized by its standard deviation σ or variance σ2

Offset voltage often specified as the 1σ or 3σ value

Offset Voltage Distribution Pdf of zero-mean Gaussian distribution

Percent between: ±σ 68.3%

±2σ 95.5%

±3σ 99.73%

x

f(x)

-kσ kσ

Source of Random Offset Voltages

Consider as an example: VDD

VSS

R1 R2

M1 M2

VOUT

IT

Ideally R1=R2=R, M1 and M2 are matched

TOUT DD

IV = V - R

2

Assume this is the desired output voltage


Consider as an example: VDD

VSS

R1 R2

M1 M2

VOUT

IT

If everything ideal except R2=R +ΔR

TOUT DD

IV = V - R+ R

2

TOUT

IV = - R

2


Consider as an example:

VDD

VSS

R1 R2

M1 M2

VOUT

IT

VDD

VSS

R1 R2

M1 M2

VOUT

IT

-Vd/2 Vd/2

mV

gA = - R

2


Determine the offset voltage – i.e. value of VX needed to obtain desired output

mV

gA = - R

2

VDD

VSS

R R+ΔR

M1 M2

VOUT

IT

VX

TDD

TOUT V X

IV = - ΔR - A V

IV R

2 2-

TX

V

I-1V = ΔR

A 2


Determine the offset voltage – i.e. value of VX needed to obtain desired output

mV

gA = - R

2

VDD

VSS

R R+ΔR

M1 M2

VOUT

IT

VX

TX

V

I-1V = ΔR

A 2

T T TX EB

m m T EB

I I I2 ΔR ΔR ΔRV = ΔR = V

g R 2 g R I /V R R

X EBΔR

V = VR


The random offset voltage is almost entirely that of the input stage in most op amps

M1 M2

M3 M4

V2

VX

VS

IT

(a)

M1 M2

M3 M4

VDD

V1V2

VX

VS

IT

(b)

V1

VDD

VOUTVOUT

Random Offset Voltages Gate DrainSource

Bulk

n-channel MOSFET

Gate DrainSource

Bulk

n-channel MOSFET

Impurities vary randomly with position as do edges of gate, oxide and diffusions

Model and design parameters vary throughout channel and thus the corresponding

equivalent lumped model parameters will vary from device to device

Random Offset Voltages

M1 M2

M3 M4

V2

VX

VS

IT

V1

VDD

VOUT

The random offset is due to missmatches in the

four transistors, dominantly missmatches in the

parameters {VT, μ,COX,W and L}

The relative missmatch effects become more

pronounced as devices become smaller

VTi=VTN+VTRi

COXi=COXN+COXRi

μi=μN+μRi

Wi=WN+WRi

Li=LN+LRi

Each design and model parameter is comprised of a nominal part and

A random component


M1 M2

M3 M4

V2

VX

VS

IT

V1

VDD

VOUT

VTi=VTN+VTRi

COXi=COXN+COXRi

μi=μN+μRi

Wi=WN+WRi

Li=LN+LRi

2N Ri OXN OXRi N Ri

Di GSi TN TRi N Ri DSN Ri

μ μ C C W +WI = V -(V V ) 1+ λ +λ V

2 L L

For each device, the device model is often expressed as

Because of the random components of the parameters in every device, matching

from the left-half circuit to the right half-circuit is not perfect

This mismatch introduces an offset voltage which is a random variable


n p

OS

2 2 2COX μ μ2 2 n n p p n n p p p2 2VTO n n EB n

VTO pV 2 n n n n p 2 2

w L 2 2 2 2 n n p p n n p p

1 1 1 1A + A +A +

W L W L W L W LA μ VLσ 2 + A +

W L μ 4W L 1 1 1 1+2A + +A +

W L W L L W L W

OS

2 p2 2 VTO n n

VTO pV 2 n n n n p

A μ Lσ 2 + A

W L μ W L

M1 M2

M3 M4

V2

VX

VS

IT

V1

VDD

VOUT

3

2

OX

VT0

2 2μ C

L W

21mV•μ (n-ch)A

25mV•μ (p-ch)

.016μ (n-ch)A +A

.023μ (p-ch)

A =A 0.017μ

From a straightforward but tedious analysis it follows that:

where the terms AVT0, Aμ, ACOX, AL, and AW are process parameters

Usually the AVT0 terms are dominant, thus the variance simplifies to


OS

2 p2 2 VTO n n

VTO pV 2 n n n n p

A μ Lσ 2 + A

W L μ W L

2

pp

2

nn

2

w2

pp

2

nn

2

L

ppnn

2

COX

2

pp

2

nn2

EBn2

VTOp2

pn

n

n

p

nn

2

VTOn2

V

WL

1

WL

1A

LW

1

LW

1A2

LW

1

LW

1AA

LW

1A

LW

1

4

VA

LW

L

LW

A2

pn

OS

M1 M2

M3 M4

VDD

V1V2

VX

VS

IT

VOUT

Correspondingly:

which again simplifies to

Note these offset voltage expressions are identical!


OS

2 p2 2 VTO n n

VTO pV 2 n n n n p

A μ Lσ 2 + A

W L μ W L

M1 M2

M3 M4

VDD

V1V2

VX

VS

IT

VOUT

Example: Determine the 3σ value of the input offset voltage for

The MOS differential amplifier if

a) M1 and M3 are minimum-sized and

b) the area of M1 and M3 are 100 times minimum size

OS

p2 2 2 VTO n VTO pV

n n n

μ2σ A + A

W L μ

a)

OS

2 2 2 V 2

2 1σ .021 + .025

30.5

72OSV

σ mV

216OSV

3 σ mV

Note this is a very large offset voltage !


OS

2 p2 2 VTO n n

VTO pV 2 n n n n p

A μ Lσ 2 + A

W L μ W L

M1 M2

M3 M4

VDD

V1V2

VX

VS

IT

VOUT

Example: Determine the 3σ value of the input offset voltage for

The MOS differential amplifier is

a) M1 and M3 are minimum-sized and

b) the area of M1 and M3 are 100 times minimum size

OS

p2 2 2 VTO n VTO pV

n n n

μ2σ A + A

W L μ

b)

100OS

2 2 2 V 2

2 1σ .021 + .025

30.5

7.2OSV

σ mV

21.6OSV

3 σ mV

Note this is much lower but still a large offset voltage !

The area of M1 and M3 needs to be very large to achieve a low offset voltage

End of Lecture 22

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EE 435 - Iowa State Universityclass.ece.iastate.edu/ee435/lectures/EE 435 Lect 22 Spring 2012.pdf · EE 435 Lecture 22 Offset Voltages . How linear is the amplifier ? ... assume their