Lecture #17Page 1

EE 367 – Logic Design

Lecture #17

• Agenda

1. MSI Encoders

2. MSI Multiplexers

• Announcements

1. HW #8 assigned.

Lecture #17Page 2

Integrated Circuit Scaling

• Integrated Circuit ScalesExample # of Transistors

SSI - Small Scale Integrated Circuits Individual Gates 10's

MSI - Medium Scale Integrated Circuits Mux, Decoder 100's

LSI - Large Scale Integrated Circuits RAM, ALU's 1k - 10k

VLSI - Very Large Scale Integrated Circuits uP, uCNT 100k - 1M

ULSI - Ultra Large Scale Integrated Circuits Modern uP's > 1M

SoC - System on Chip Microcomputers

SoP - System on Package Different technology blending

- we use the terms SSI and MSI. Everything larger is typically just called "VLSI"

- VLSI covers design that can't be done using schematics or by hand.

Lecture #17Page 3

Encoders

• Encoder

- an encoder has 2n inputs and n outputs

- it assumes that one and only one input will be asserted

- depending on which input is asserted, an output code will be generated

- this is the exact opposite of a decoder

ex) truth table of binary encoder

Input Output 0001 00 0010 01 0100 10 1000 11

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Encoders

• Encoder

- an encoder output is a simple OR structure that looks at the incoming signals

ex) 4-to-2 encoder

I3 I2 I1 I0 Y1 Y0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 0 1 0 0 0 1 1

Y1 = I3 + I2 Y0 = I3 + I1

Lecture #17Page 5

Encoders

• Encoders in VHDL

- 8-to-3 binary encoder modeled with Structural VHDL

entity encoder_8to3_binary is generic (t_delay : time := 1.0 ns); port (I : in STD_LOGIC_VECTOR (7 downto 0); Y : out STD_LOGIC_VECTOR (2 downto 0) );

end entity encoder_8to3_binary;

architecture encoder_8to3_binary_arch of encoder_8to3_binary is

component or4 port (In1,In2,In3,In4: in STD_LOGIC; Out1: out STD_LOGIC); end component; begin U1 : or4 port map (In1 => I(1), In2 => I(3), In3 => I(5), In4 => I(7), Out1 => Y(0) ); U2 : or4 port map (In1 => I(2), In2 => I(3), In3 => I(6), In4 => I(7), Out1 => Y(1) ); U3 : or4 port map (In1 => I(4), In2 => I(5), In3 => I(6), In4 => I(7), Out1 => Y(2) );

end architecture encoder_8to3_binary_arch;

Lecture #17Page 6

Encoders

• Encoders in VHDL

- 8-to-3 binary encoder modeled with Behavioral VHDL

entity encoder_8to3_binary is generic (t_delay : time := 1.0 ns); port (I : in STD_LOGIC_VECTOR (7 downto 0); Y : out STD_LOGIC_VECTOR (2 downto 0) );

end entity encoder_8to3_binary;

architecture encoder_8to3_binary_arch of encoder_8to3_binary isbegin ENCODE : process (I) begin case (I) is when "00000001" => Y <= "000"; when "00000010" => Y <= "001"; when "00000100" => Y <= "010"; when "00001000" => Y <= "011"; when "00010000" => Y <= "100"; when "00100000" => Y <= "101"; when "01000000" => Y <= "110"; when "10000000" => Y <= "111"; when others => Y <= "ZZZ"; end case;

end process ENCODE;

end architecture encoder_8to3_binary_arch;

Lecture #17Page 7

Priority Encoders

• Priority Encoder

- a generic encoder does not know what to do when multiple input bits are asserted

- to handle this case, we need to include prioritization

- we decide the list of priority (usually MSB to LSB) where the truth table can be written as follows:

ex) 4-to-2 encoder I3 I2 I1 I0 Y1 Y0 1 x x x 1 1 0 1 x x 1 0 0 0 1 x 0 1 0 0 0 1 0 0

- we can then write expressions for an intermediate stage of priority bits “H” (i.e., Highest Priority):

H3 = I3 H2 = I2∙I3’ H1 = I1∙I2’∙I3’ H0 = I0∙I1’∙I2’∙I3’

- the final output stage then becomes: Y1 = H3 + H2 Y0 = H3 + H1

Lecture #17Page 8

Priority Encoders

• Priority Encoders in VHDL

- 8-to-3 binary priority encoder modeled with Behavioral VHDL

- If/Then/Else statements give priority

- Concurrent Conditional Signal Assignments give priority

entity encoder_8to3_priority is generic (t_delay : time := 1.0 ns); port (I : in STD_LOGIC_VECTOR (7 downto 0); Y : out STD_LOGIC_VECTOR (2 downto 0) );

end entity encoder_8to3_priority;

architecture encoder_8to3_priority_arch of encoder_8to3_priority is begin Y <= "111" when I(7) = '1' else -- highest priority code "110" when I(6) = '1' else "101" when I(5) = '1' else "100" when I(4) = '1' else "011" when I(3) = '1' else "010" when I(2) = '1' else "001" when I(1) = '1' else "000" when I(0) = '1' else -- lowest priority code "ZZZ";

end architecture encoder_8to3_priority_arch;

Lecture #17Page 9

Multiplexer

• Multiplexer

- gates are combinational logic which generate an output depending on the current inputs

- what if we wanted to create a “Digital Switch” to pass along the input signal?

- this type of circuit is called a “Multiplexer”

ex) truth table of Multiplexer

Sel Out 0 A 1 B

Lecture #17Page 10

Multiplexer

• Multiplexer

- we can use the behavior of an AND gate to build this circuit:

X∙0 = 0 “Block Signal” X∙1 = X “Pass Signal”

- we can then use the behavior of an OR gate at the output state (since a 0 input has no effect) to combine the signals into one output

Lecture #17Page 11

Multiplexer

• Multiplexer

- the outputs will track the selected input

- this is in effect, a “Switch”

ex) truth table of Multiplexer

Sel A B Out 0 0 x 0 0 1 x 1 1 x 0 0 1 x 1 1

- an ENABLE line can also be fed into each AND gate

Lecture #17Page 12

Multiplexer

• Multiplexers in VHDL

- Structural Model

entity mux_4to1 is port (D : in STD_LOGIC_VECTOR (3 downto 0); Sel : in STD_LOGIC_VECTOR (1 downto 0); Y : out STD_LOGIC); end entity mux_4to1;

architecture mux_4to1_arch of mux_4to1 is

signal Sel_n : STD_LOGIC_VECTOR (1 downto 0); signal U3_out, U4_out, U5_out, U6_out : STD_LOGIC; component inv1 port (In1: in STD_LOGIC; Out1: out STD_LOGIC); end component; component and3 port (In1,In2,In3 : in STD_LOGIC; Out1: out STD_LOGIC); end component; component or4 port (In1,In2,In3,In4: in STD_LOGIC; Out1: out STD_LOGIC); end component;

begin U1 : inv1 port map (In1 => Sel(0), Out1 => Sel_n(0)); U2 : inv1 port map (In1 => Sel(1), Out1 => Sel_n(1)); U3 : and3 port map (In1 => D(0), In2 => Sel_n(1), In3 => Sel_n(0), Out1 => U3_out); U4 : and3 port map (In1 => D(1), In2 => Sel_n(1), In3 => Sel(0), Out1 => U4_out); U5 : and3 port map (In1 => D(2), In2 => Sel(1), In3 => Sel_n(0), Out1 => U5_out); U6 : and3 port map (In1 => D(3), In2 => Sel(1), In3 => Sel(0), Out1 => U6_out); U7 : or4 port map (In1 => U3_out, In2 => U4_out, In3 => U5_out, In4 => U6_out, Out1 => Y);

end architecture mux_4to1_arch;

Lecture #17Page 13

Multiplexer

• Multiplexers in VHDL

- Structural Model w/ EN

entity mux_4to1 is port (D : in STD_LOGIC_VECTOR (3 downto 0); Sel : in STD_LOGIC_VECTOR (1 downto 0); EN : in STD_LOGIC; Y : out STD_LOGIC);end entity mux_4to1;

architecture mux_4to1_arch of mux_4to1 is

signal Sel_n : STD_LOGIC_VECTOR (1 downto 0); signal U3_out, U4_out, U5_out, U6_out : STD_LOGIC;

component inv1 port (In1: in STD_LOGIC; Out1: out STD_LOGIC); end component; component and4 port (In1,In2,In3,In4: in STD_LOGIC; Out1: out STD_LOGIC); end component; component or4 port (In1,In2,In3,In4: in STD_LOGIC; Out1: out STD_LOGIC); end component;

begin U1 : inv1 port map (In1 => Sel(0), Out1 => Sel_n(0)); U2 : inv1 port map (In1 => Sel(1), Out1 => Sel_n(1)); U3 : and4 port map (In1 => D(0), In2 => Sel_n(1), In3 => Sel_n(0), In4 => EN, Out1 => U3_out); U4 : and4 port map (In1 => D(1), In2 => Sel_n(1), In3 => Sel(0), In4 => EN, Out1 => U4_out); U5 : and4 port map (In1 => D(2), In2 => Sel(1), In3 => Sel_n(0), In4 => EN, Out1 => U5_out); U6 : and4 port map (In1 => D(3), In2 => Sel(1), In3 => Sel(0), In4 => EN, Out1 => U6_out); U7 : or4 port map (In1 => U3_out, In2 => U4_out, In3 => U5_out, In4 => U6_out, Out1 => Y);end architecture mux_4to1_arch;

Lecture #17Page 14

Multiplexer

• Multiplexers in VHDL

- Behavioral Model w/ EN

entity mux_4to1 is port (D : in STD_LOGIC_VECTOR (3 downto 0); Sel : in STD_LOGIC_VECTOR (1 downto 0); EN : in STD_LOGIC; Y : out STD_LOGIC); end entity mux_4to1;

architecture mux_4to1_arch of mux_4to1 is begin MUX : process (D, Sel, EN) begin if (EN = '1') then case (Sel) is when "00" => Y <= D(0); when "01" => Y <= D(1); when "10" => Y <= D(2); when "11" => Y <= D(3); when others => Y <= 'Z'; end case; else Y <= 'Z'; end if;

end process MUX;end architecture mux_4to1_arch;