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Chapter 1Chapter 1

Verilog HardwareVerilog Hardware

Description LanguageDescription Language



Embedded Design using Programmable Gate Arrays

Chapter 1

VerilogVerilog

Verilog was invented byVerilog was invented by PhilPhil MoorbyMoorby andand PrabhuPrabhu GoelGoel inin

1985 as a proprietary hardware modeling language.1985 as a proprietary hardware modeling language.Verilog came into the public domain under theVerilog came into the public domain under the OpenOpen

Verilog InternationalVerilog International (OVI) organization. Verilog was later (OVI) organization. Verilog was later

submitted tosubmitted to IEEEIEEE and becameand became IEEEIEEE Standard 1364Standard 1364--

1995, commonly referred to as1995, commonly referred to as Verilog Verilog --95 95 ..

Extensions to VerilogExtensions to Verilog--95 were submitted95 were submitted

to cover the deficiencies that users hadto cover the deficiencies that users hadfound in the original Verilog standard.found in the original Verilog standard.

These extensions becameThese extensions became IEEEIEEE

Standard 1364Standard 1364--2001 also known as2001 also known asVerilog Verilog --20012001..




Chapter 1

VerilogVerilog

Verilog Verilog --2005 2005 ((IEEEIEEE Standard 1364Standard 1364--2005) consists of 2005) consists of

minor corrections, clarifications, and a few new languageminor corrections, clarifications, and a few new languagefeatures.features.

SystemVerilog SystemVerilog ((IEEEIEEE standard P1800standard P1800--2005) is a2005) is a supersetsuperset

of Verilogof Verilog--2005, with many new features and capabilities2005, with many new features and capabilitiesto aid designto aid design--verification and designverification and design--modeling.modeling.




Chapter 1

Verilog Number FormatVerilog Number Format. Integer numbers are specified. Integer numbers are specifiedas <as <sign>sign><<sizesize><><base format base format ><><number number >.>. If the <If the <sizesize> is> is

not given, then the number of bits is a default minimum of not given, then the number of bits is a default minimum of

32.32.

Listing 1.7Listing 1.7 Examples of valid and invalid integer number formats in VeriloExamples of valid and invalid integer number formats in Verilogg

138138

// decimal number, 32 bit as 00000000000000000000000010001010// decimal number, 32 bit as 00000000000000000000000010001010

1010′ ′ d138d138 // decimal number, 10 bit as 0010001010// decimal number, 10 bit as 0010001010

66′ ′ o74o74 // octal number, 6 bits as 111100// octal number, 6 bits as 111100

2424′ ′ h25Fh25F // hexadecimal number, 24 bit as 000000000000001001011111// hexadecimal number, 24 bit as 000000000000001001011111

88′ ′ hxBhxB // hexadecimal number, 8 bit as xxxx1011// hexadecimal number, 8 bit as xxxx1011

33′ ′ b010b010 // binary number, 3 bits as 010// binary number, 3 bits as 010--66′ ′ b101b101 // 6 bit, two// 6 bit, two’’s complement of 000101 or 111011s complement of 000101 or 111011

--1010′ ′ d15d15 // 10 bit, two// 10 bit, two’’s complement of 0000001111 or 1111110001s complement of 0000001111 or 1111110001

55′ ′ d124d124 // decimal number, 5 bits as 11100 since 7 bits are required// decimal number, 5 bits as 11100 since 7 bits are required

1212′ ′ oF2oF2 // invalid, F is not a octal digit// invalid, F is not a octal digit




Chapter 1

Verilog Number FormatVerilog Number Format. The <. The <base format base format > consist of > consist of an apostrophe ( ' ) followed byan apostrophe ( ' ) followed by bb (binary, base(binary, base--2),2), d d

(decimal, base(decimal, base--10),10), oo (octal, base(octal, base--8) or 8) or hh (hexadecimal,(hexadecimal,

basebase--16) for integer numbers. If the <16) for integer numbers. If the <base format base format > is not> is notused, the base is assumed to be decimal.used, the base is assumed to be decimal.

Listing 1.7Listing 1.7 Examples of valid and invalid integer number formats in VeriloExamples of valid and invalid integer number formats in Verilogg

138138 // decimal number, 32 bit as 00000000000000000000000010001010// decimal number, 32 bit as 00000000000000000000000010001010

1010′ ′ d138d138 // decimal number, 10 bit as 0010001010// decimal number, 10 bit as 0010001010

66′ ′ o74o74 // octal number, 6 bits as 111100// octal number, 6 bits as 111100

2424′ ′ h25Fh25F // hexadecimal number, 24 bit as 000000000000001001011111// hexadecimal number, 24 bit as 000000000000001001011111

88′ ′ hxBhxB // hexadecimal number, 8 bit as xxxx1011// hexadecimal number, 8 bit as xxxx1011

33′ ′ b010b010 // binary number, 3 bits as 010// binary number, 3 bits as 010

--66′ ′ b101b101 // 6 bit, two// 6 bit, two’’s complement of 000101 or 111011s complement of 000101 or 111011

--1010′ ′ d15d15 // 10 bit, two// 10 bit, two’’s complement of 0000001111 or 1111110001s complement of 0000001111 or 1111110001

55′ ′ d124d124 // decimal number, 5 bits as 11100 since 7 bits are required// decimal number, 5 bits as 11100 since 7 bits are required1212′ ′ oF2oF2 // invalid, F is not a octal digit// invalid, F is not a octal digit




Chapter 1

Verilog ConstantsVerilog Constants. Constants in Verilog are declared. Constants in Verilog are declaredwith the keywordwith the keyword parameter parameter and can include arithmeticand can include arithmetic

expressions with other constants. The keywordexpressions with other constants. The keyword defparamdefparam

is used to redefine a parameter within a module. Theis used to redefine a parameter within a module. Theredefinition can be specifically applied to the parametersredefinition can be specifically applied to the parameters

of a specific (M2) nested module (of a specific (M2) nested module (auxbusauxbus).).

Listing 1.8Listing 1.8 ConstantConstant parameter parameter declaration anddeclaration and defparamdefparam redefinition with inredefinition with inVerilogVerilog

parameter BUS_WIDTH = 32;parameter BUS_WIDTH = 32; // integer // integer

parameter XMAX=640, YMAX = 480;parameter XMAX=640, YMAX = 480; // integers// integersparameter START_VALUE = 8parameter START_VALUE = 8′ ′ b00001111;b00001111; // register // register

parameter SIZE = XMAX*YMAX;parameter SIZE = XMAX*YMAX; // arithmetic expression// arithmetic expression

defparamdefparam auxbus.M2.BUS_WIDTH = 16;auxbus.M2.BUS_WIDTH = 16; // redefinition of BUS// redefinition of BUS--WIDTH inWIDTH in

// instance M2 of nested// instance M2 of nested

// module// module auxbusauxbus




Chapter 1

Verilog WireVerilog Wire. The net variable type. The net variable type wirewire establishesestablishesbehavioral connectivity with logic values of 0, 1,behavioral connectivity with logic values of 0, 1, x x

(unknown) or (unknown) or z z (high impedance) determined by the(high impedance) determined by the

modulemodule port port that drives the signal variable.that drives the signal variable.

Listing 1.9Listing 1.9 Net variableNet variable wirewire declaration in Verilogdeclaration in Verilog

wirewire glbrstglbrst;; // scalar net signal// scalar net signal

wirewire mclkmclk,, davdav;; // scalar net signals// scalar net signals

wire [31:0] average;wire [31:0] average; // 32// 32--bit vector net signalbit vector net signal

wire [0:7]wire [0:7] adc_valueadc_value;; // 8// 8--bit vector net signal, reversed MSBbit vector net signal, reversed MSB




Chapter 1

Verilog Register VariablesVerilog Register Variables. Register variables are used. Register variables are usedin behavioral modeling, are assigned values by proceduralin behavioral modeling, are assigned values by procedural

statements and store information. Register variables thatstatements and store information. Register variables that

are used in a Verilog HDL behavioral description areare used in a Verilog HDL behavioral description are

declared by the keywordsdeclared by the keywords reg reg andand integer integer ..

The keywordThe keyword reg reg is the abstraction of a hardware storageis the abstraction of a hardware storage

element and has a default size of one bit and an initialelement and has a default size of one bit and an initiallogic value of logic value of x x (unknown).(unknown).

Listing 1.10Listing 1.10 Register variableRegister variable reg reg declaration in Verilogdeclaration in Verilog

reg clock;reg clock; // register signal// register signal

reg reset, read_data;reg reset, read_data; // register signals// register signals

reg signed [7:0] sum;reg signed [7:0] sum; // 7// 7--bit plus sign register signalbit plus sign register signal

reg [15:0] accum;reg [15:0] accum; // 16// 16--bit register signal, reversed MSBbit register signal, reversed MSB




Chapter 1

Verilog Register VariablesVerilog Register Variables. The integer type of register . The integer type of register variable supports numerical computation in Verilogvariable supports numerical computation in Verilog

behavioral synthesis. Integer variables are declared bybehavioral synthesis. Integer variables are declared by

the keywordthe keyword

integer integer

, have a default but fixed size of 32, have a default but fixed size of 32

bits in signed twobits in signed two’’s complement format and a default initials complement format and a default initial

value of zero.value of zero.

Integers areIntegers are true abstractionstrue abstractions that must have a numericalthat must have a numericalvalue, but the procedures that they comprise are compiledvalue, but the procedures that they comprise are compiled

by the Verilog HDL to synthesizable hardware.by the Verilog HDL to synthesizable hardware.

Listing 1.11Listing 1.11 Register variable integer declaration in Verilog

integer data; // integer

integer i, j, k; // multiple integers

integer data[1:1000] // integer array




Chapter 1

Verilog String VariablesVerilog String Variables. Verilog utilizes the register . Verilog utilizes the register variable with thevariable with the reg reg declaration to store ASCII character declaration to store ASCII character

strings as 8strings as 8--bit values. The string can be initially assignedbit values. The string can be initially assigned

to the register variableto the register variable

reg reg

declaration by enclosing itdeclaration by enclosing it

within quotation marks.within quotation marks.

If the string assignment uses less than the availableIf the string assignment uses less than the available

number of bits, the unused register variablenumber of bits, the unused register variable reg reg declaration bits are filled with zero.declaration bits are filled with zero.

Listing 1.12Listing 1.12 String and memory register variableString and memory register variable reg reg declaration in Verilogdeclaration in Verilog

parameter STRING_LENGTH = 11;parameter STRING_LENGTH = 11; // parameter declaration// parameter declaration

reg [8 * STRING_LENGTH]reg [8 * STRING_LENGTH] string_datastring_data;; // arithmetic calculation of size// arithmetic calculation of size

reg [7:0]reg [7:0] byte_memorybyte_memory [0:511];[0:511]; // MSB bit first, 512 byte memory// MSB bit first, 512 byte memory

strdatastrdata == ””hello worldhello world””;; // string assignment to a register // string assignment to a register




Chapter 1

Verilog String VariablesVerilog String Variables. The assignment of a string to a. The assignment of a string to aregister variable with theregister variable with the reg reg declaration is a singledeclaration is a single

addressaddress memory memory . Multiple addressable register variables. Multiple addressable register variables

of the same size can be accommodated with the formatof the same size can be accommodated with the format

<<word size>word size><<variable namevariable name><><memory sizememory size>.>.


parameter STRING_LENGTH = 11;parameter STRING_LENGTH = 11; // parameter declaration// parameter declaration

reg [8 * STRING_LENGTH]reg [8 * STRING_LENGTH] string_datastring_data;; // arithmetic calculation of size// arithmetic calculation of size

reg [7:0]reg [7:0] byte_memorybyte_memory [0:511];[0:511]; // MSB bit first, 512 byte memory// MSB bit first, 512 byte memory

strdatastrdata == ””hello worldhello world””;; // string assignment to a register // string assignment to a register

lcddata[7:0] = strdata[ilcddata[7:0] = strdata[i--:8];:8]; // variable selection of a register // variable selection of a register

lcddata[7:0] = strdata[87:80];lcddata[7:0] = strdata[87:80]; // fixed selection of a register // fixed selection of a register

reg [3:0] data = {adata[1:0], bdata[1:0]};reg [3:0] data = {adata[1:0], bdata[1:0]}; // concatenation// concatenation




Chapter 1

Verilog String VariablesVerilog String Variables. Verilog supports the selection. Verilog supports the selectionof a word or the contiguous part of a word for net or of a word or the contiguous part of a word for net or

register variables with the part select operators (<register variables with the part select operators (<start bit start bit >>

+: <+: <

widthwidth

> and <> and <

start bit start bit

>>

– –

: <: <

widthwidth

>). The parameter >). The parameter

widthwidth specifies the size of the selection which is obtainedspecifies the size of the selection which is obtained

by either incrementing ( +: ) or decrementing (by either incrementing ( +: ) or decrementing ( – –: ) the: ) the

index of the bits in the register. The integer register index of the bits in the register. The integer register

variable i sets the parameter variable i sets the parameter start bit start bit as the startingas the startingposition for the selection.position for the selection.


lcddata[7:0] = strdata[ilcddata[7:0] = strdata[i--:8];:8]; // variable selection of a register // variable selection of a register

lcddata[7:0] = strdata[87:80];lcddata[7:0] = strdata[87:80]; // fixed selection of a register // fixed selection of a register

reg [3:0] data = {adata[1:0], bdata[1:0]};reg [3:0] data = {adata[1:0], bdata[1:0]}; // concatenation// concatenation




Chapter 1

Verilog Array VariablesVerilog Array Variables. Although Verilog supports. Although Verilog supportsmultidimensional array, the Xilinx ISE WebPACK EDAmultidimensional array, the Xilinx ISE WebPACK EDA

software tool only supports arrays with no more than threesoftware tool only supports arrays with no more than three

dimensions.dimensions.

Listing 1.13Listing 1.13 Multidimensional arrays and word selection in Verilog 2001Multidimensional arrays and word selection in Verilog 2001

reg [7:0]reg [7:0] pix_datapix_data [0:639] [0:479];[0:639] [0:479]; // two dimensional array of bytes// two dimensional array of bytes

wire [7:0]wire [7:0] pixoutpixout [120] [330];[120] [330]; // fixed word of pixel (120,330)// fixed word of pixel (120,330)wirewire msb_pixmsb_pix == pix_datapix_data [120] [330] [7];[120] [330] [7]; // MSB of pixel (120,330)// MSB of pixel (120,330)




Chapter 1

Verilog Bitwise Signal OperationsVerilog Bitwise Signal Operations. Verilog provides. Verilog providesintrinsic signal operations which describe logicintrinsic signal operations which describe logic

symbolically in behavioral synthesis, rather than bysymbolically in behavioral synthesis, rather than by

Verilog primitives in a structural model which utilizeVerilog primitives in a structural model which utilize

combinational logic gates.combinational logic gates.

TheThe bitwisebitwise operators combine two signal operands tooperators combine two signal operands to

form a signal result.form a signal result.

Table 1.1Table 1.1 Bitwise operations in VerilogBitwise operations in Verilog

~~ NegationNegation (one(one’’s complement)s complement)

&& And And

|| Inclusive Or Inclusive Or

^̂ Exclusive Or Exclusive Or

~ ^~ ^ Exclusive Not Or Exclusive Not Or ^ ~^ ~ Exclusive Not Or Exclusive Not Or




Chapter 1

Verilog Reduction OperationsVerilog Reduction Operations. The. The reductionreduction operatorsoperatorsproduce a scalar with logic values of 0, 1, or produce a scalar with logic values of 0, 1, or x x (unknown)(unknown)

from a single signal operand. Each bit of the signalfrom a single signal operand. Each bit of the signal

operand participates in the reduction operation to produceoperand participates in the reduction operation to produce

the result. For example, if x = 1001, then &x = 0 and |x =the result. For example, if x = 1001, then &x = 0 and |x =

1. The scalar value is1. The scalar value is x x (unknown) if the operand contains(unknown) if the operand contains

at least a single bit which is unknown.at least a single bit which is unknown.

Table 1.2Table 1.2 Reduction operations in VerilogReduction operations in Verilog

&& And And

~ &~ & Not AndNot And|| Or Or

~ |~ | Not Or Not Or

^̂ Exclusive Or Exclusive Or

~ ^~ ^ Exclusive Not Or Exclusive Not Or

^ ~^ ~ Exclusive Not Or Exclusive Not Or




Chapter 1

Verilog Relational OperationsVerilog Relational Operations. The. The relational relational operatorsoperatorscompare two signal operands and produce a scalar withcompare two signal operands and produce a scalar with

logic values of 0 (false), 1 (true), or logic values of 0 (false), 1 (true), or x x (unknown).(unknown).

The scalar value isThe scalar value is x x (unknown) if either operand contains(unknown) if either operand contains

at least a single bit which is unknown or at least a single bit which is unknown or z z (high(high

impedance).impedance).

Table 1.3Table 1.3 Relational operations in VerilogRelational operations in Verilog

<< Less ThanLess Than

< =< = Less Than or Equal ToLess Than or Equal To>> Greater ThanGreater Than

> => = Greater Than or Equal ToGreater Than or Equal To




Chapter 1

Verilog Equality OperationsVerilog Equality Operations. The. The logical equality logical equality andandlogical inequality logical inequality operators compare two signal operandsoperators compare two signal operands

bit bit --by by --bit bit and produce a scalar with logic values of 0and produce a scalar with logic values of 0

(false), 1 (true), or (false), 1 (true), or x x (unknown).(unknown).

The scalar value isThe scalar value is x x (unknown) if the operand contains at(unknown) if the operand contains at

least a single bit which is unknown or least a single bit which is unknown or z z (high impedance).(high impedance).

Table 1.4Table 1.4 Equality operations in VerilogEquality operations in Verilog

= = == = = Case EqualityCase Equality

! = =! = = Case InequalityCase Inequality= == = Logical EqualityLogical Equality

! =! = Logical InequalityLogical Inequality




Chapter 1

Verilog Equality OperationsVerilog Equality Operations. The. The case equality case equality andandcase inequality case inequality operators compare two signal operandsoperators compare two signal operands

bit bit --by by --bit bit utilizing the four logic values (0, 1,utilizing the four logic values (0, 1, x x ,, z z ) and) and

produce a scalar with logic values of 0 (false) and 1 (true).produce a scalar with logic values of 0 (false) and 1 (true).

Table 1.4Table 1.4 Equality operations in VerilogEquality operations in Verilog

= = == = = Case EqualityCase Equality

! = =! = = Case InequalityCase Inequality

= == = Logical EqualityLogical Equality

! =! = Logical InequalityLogical Inequality




Chapter 1

Verilog Logical OperationsVerilog Logical Operations. The. The logical logical operators areoperators aresimilar to the reduction operators but produce a scalar similar to the reduction operators but produce a scalar

with logic values of 0, 1, or with logic values of 0, 1, or x x (unknown) from two signal(unknown) from two signal

operands. Each bit of the two signal operandsoperands. Each bit of the two signal operands

participates in the logical operation to produce the result.participates in the logical operation to produce the result.

Table 1.5Table 1.5 Logical operations in VerilogLogical operations in Verilog

& && & Logical AndLogical And

| || | Logical Or Logical Or

!! Logical NegationLogical Negation




Chapter 1

Verilog Logical OperationsVerilog Logical Operations. For example, if x = 1001. For example, if x = 1001and y = 0110 then x && y = 0 and x || y = 1.and y = 0110 then x && y = 0 and x || y = 1.

The scalar value isThe scalar value is x x (unknown) if either of the operands(unknown) if either of the operands

contains at least a single bit which is unknown. Thecontains at least a single bit which is unknown. The

operation is evaluated from left to right and ends as soonoperation is evaluated from left to right and ends as soon

as result is unequivocally true or false.as result is unequivocally true or false.

Table 1.5Table 1.5 Logical operations in VerilogLogical operations in Verilog

& && & Logical AndLogical And

| || | Logical Or Logical Or !! Logical NegationLogical Negation




Chapter 1

Verilog Logical Shift OperationsVerilog Logical Shift Operations. The logical shift. The logical shiftoperator shifts the bits in a signal operand to the right or operator shifts the bits in a signal operand to the right or

left and fills the vacated bits with a logic value of 0.left and fills the vacated bits with a logic value of 0.

For example, if x = 10011100 then x << 2 = 01110000.For example, if x = 10011100 then x << 2 = 01110000.

Table 1.6Table 1.6 Logical shift operations in VerilogLogical shift operations in Verilog

> >> > Logical Shift RightLogical Shift Right

< << < Logical Shift LeftLogical Shift Left




Chapter 1

Verilog Arithmetic Shift OperationsVerilog Arithmetic Shift Operations. Verilog supports. Verilog supportsthe arithmetic shift operator which shifts the bits in a signalthe arithmetic shift operator which shifts the bits in a signal

to the right or left and fills the vacated bits with the mostto the right or left and fills the vacated bits with the most

significant bit (MSB) if a right shift and a logic value of 0 if significant bit (MSB) if a right shift and a logic value of 0 if

a left shift.a left shift.

For example, if x = 10011100 then x >>> 2 = 11100111.For example, if x = 10011100 then x >>> 2 = 11100111.

The left shift arithmetic operator is functionally the sameThe left shift arithmetic operator is functionally the sameas the left shift logical operator.as the left shift logical operator.

Table 1.7Table 1.7 Arithmetic shift operations in Verilog Arithmetic shift operations in Verilog

> > >> > > Arithmetic Shift Right Arithmetic Shift Right

< < << < < Arithmetic Shift Left Arithmetic Shift Left




Chapter 1

Verilog Arithmetic OperationsVerilog Arithmetic Operations. The common arithmetic. The common arithmeticoperations in Verilog manipulate the register variableoperations in Verilog manipulate the register variable reg reg

declaration as signed or unsigned integers of any bit size.declaration as signed or unsigned integers of any bit size.

The keywordThe keyword signed signed is used to declare that the register is used to declare that the register

variablevariable reg reg declaration is signed. The register variabledeclaration is signed. The register variable

integer integer declaration has a default but fixed size of 32 bitsdeclaration has a default but fixed size of 32 bits

for signed twofor signed two’’s complement arithmetic.s complement arithmetic.

Table 1.8Table 1.8 Arithmetic operations in Verilog Arithmetic operations in Verilog

** MultiplicationMultiplication// DivisionDivision

%% ModulusModulus

++ Addition Addition

– – SubtractionSubtraction




Chapter 1

Verilog Conditional OperationsVerilog Conditional Operations. The conditional. The conditionaloperation in Verilog can utilize the logic true or false of aoperation in Verilog can utilize the logic true or false of a

Boolean expression to select one of two possibleBoolean expression to select one of two possible

arithmetic expressions.arithmetic expressions.

The form of the conditional operation is:The form of the conditional operation is:

<<Boolean expressionBoolean expression> ? <> ? <result if trueresult if true> : <> : <result if falseresult if false>.>.

Listing 1.14Listing 1.14 Conditional operation in VerilogConditional operation in Verilog

reg signed [15:0] c;reg signed [15:0] c;

reg signed [7:0] a;reg signed [7:0] a;reg signed [7:0] b;reg signed [7:0] b;

c = (a > b) ? 1 : 0;c = (a > b) ? 1 : 0; // c will be either 1 or 0// c will be either 1 or 0

c = (a == b) ? ac = (a == b) ? a – – b : a + b;b : a + b; // c will be either a// c will be either a – – b or a + bb or a + b

c = (ac = (a – – b) > 4 ? a : b;b) > 4 ? a : b; // c will be either a or b// c will be either a or b




Chapter 1

Verilog Nested Modules.Verilog Nested Modules. Modules can beModules can be nested nested or or called multiple times. Unlike subroutines each separatecalled multiple times. Unlike subroutines each separate

instance is evoked in hardware. The Verilog structuralinstance is evoked in hardware. The Verilog structural

model for a combinationalmodel for a combinational half half --adder adder is shown.is shown.

Listing 1.15Listing 1.15 Verilog structural model of a 1Verilog structural model of a 1--bit adder with carrybit adder with carry

modulemodule half_add(outputhalf_add(output sum, carry, input a, b);sum, carry, input a, b);

xor (sum, a, b);xor (sum, a, b); // exclusive OR// exclusive OR

and (carry, a ,b);and (carry, a ,b); // and// and

endmoduleendmodule




Chapter 1

Verilog Modules.Verilog Modules. The Verilog structural or behavioralThe Verilog structural or behavioralmodel consists of declarations beginning with the keywordmodel consists of declarations beginning with the keyword

modulemodule and ending with the keywordand ending with the keyword endmoduleendmodule..

The declarations specify the signal inputs and outputs of The declarations specify the signal inputs and outputs of

the model at thethe model at the port port and the manipulation of the signalsand the manipulation of the signals

using the Verilog operations.using the Verilog operations.



xor (sum, a, b);xor (sum, a, b); // exclusive OR// exclusive OR

and (carry, a ,b);and (carry, a ,b); // and// and

endmoduleendmodule




Chapter 1

Verilog Modules.Verilog Modules. The module name is case sensitiveThe module name is case sensitiveand the namesand the names half_adder half_adder andand Half_adder Half_adder are assumedare assumed

by the Verilog compiler to be different modules.by the Verilog compiler to be different modules.



xor (sum, a, b);xor (sum, a, b); // exclusive OR// exclusive ORand (carry, a ,b);and (carry, a ,b); // and// and

endmoduleendmodule




Chapter 1

Verilog Nested Modules.Verilog Nested Modules. Modules can be nested usingModules can be nested usingthethe connection by positionconnection by position in the definition.in the definition.

Listing 1.16Listing 1.16 Verilog nested structural model of a 1Verilog nested structural model of a 1--bit fullbit full--adder with carryadder with carry

with portwith port connection by positionconnection by position

modulemodule full_add(outputfull_add(output sum_outsum_out,, carry_outcarry_out, input, input a_ina_in,, b_inb_in,, carry_incarry_in););

wire w1, w2, w3;wire w1, w2, w3;

half_addhalf_add M1 (w1, w2,M1 (w1, w2, a_ina_in,, b_inb_in););

half_addhalf_add M2 (M2 (sum_outsum_out, w3,, w3, carry_incarry_in, w1);, w1);

or (or (carry_outcarry_out, w2, w3);, w2, w3);

endmoduleendmodule




Chapter 1

Verilog Nested Modules.Verilog Nested Modules. Modules can be nested usingModules can be nested usingthethe connection by nameconnection by name in the definition using thein the definition using the dot dot (.)(.)

notationnotation

Listing 1.17Listing 1.17 Verilog nested structural model of a 1Verilog nested structural model of a 1--bit fullbit full--adder with carryadder with carrywith portwith port connection by nameconnection by name

modulemodule full_add(outputfull_add(output sum_outsum_out,, carry_outcarry_out, input, input a_ina_in,, b_inb_in,, carry_incarry_in););

wire w1, w2, w3;wire w1, w2, w3;

half_addhalf_add M1 (.M1 (.a(a_ina(a_in), .sum(w1), .), .sum(w1), .b(b_inb(b_in), .carry(w2));), .carry(w2));

half_addhalf_add M2 (.M2 (.sum(sum_outsum(sum_out), .b(w1), .carry(w3), .), .b(w1), .carry(w3), .a(carry_ina(carry_in));));

or (or (carry_outcarry_out, w2, w3);, w2, w3);

endmoduleendmodule




Chapter 1

Verilog Control Flow.Verilog Control Flow. The case statement is usedThe case statement is usedextensively for control flow and for finite state machinesextensively for control flow and for finite state machines

(FSM).(FSM).

Listing 1.28Listing 1.28 Verilog behavioral model of a four channel multiplexer using tVerilog behavioral model of a four channel multiplexer using thehecasecase statementstatement

module mux4ch (output reg data, input [1:0] select, input a, b,module mux4ch (output reg data, input [1:0] select, input a, b, c, d);c, d);

always@(aalways@(a or b or c or d or select)or b or c or d or select)

case (select)case (select)

0: data = a;0: data = a;

1: data = b;1: data = b;

2: data = c;2: data = c;

3: data = d;3: data = d;

default data = 1default data = 1′ ′ bz;bz;

endcaseendcase

endmoduleendmodule




Chapter 1

Verilog Control Flow.Verilog Control Flow. TheThe for for loop is used with a nonloop is used with a non--register variable to form a repetitive flow.register variable to form a repetitive flow.

Listing 1.30Listing 1.30 Verilog behavioral model of an odd parity generator using theVerilog behavioral model of an odd parity generator using the

for loopfor loop constructconstruct

modulemodule oddparity_for oddparity_for (output reg parity, input [7:0] data);(output reg parity, input [7:0] data);

integer k;integer k;

always@(data)always@(data)

beginbegin

parity = 1;parity = 1;

for (k = 0; k <= 7; k = k+1)for (k = 0; k <= 7; k = k+1)

beginbegin

if (if (data[kdata[k] == 1)] == 1)parity = ~parity;parity = ~parity;

endend

endend

endmoduleendmodule




Chapter 1

Verilog Control Flow.Verilog Control Flow. TheThe repeat repeat loop is similar but usesloop is similar but usesa constant expression.a constant expression.

Listing 1.31Listing 1.31 Verilog behavioral model of an odd parity generator using theVerilog behavioral model of an odd parity generator using the

repeat looprepeat loop constructconstruct

modulemodule oddparity_repeatoddparity_repeat (output reg parity, input [7:0] data);(output reg parity, input [7:0] data);

integer k;integer k;

always@(data)always@(data)

beginbegin

parity = 1;parity = 1;

k = 0;k = 0;

repeat (8)repeat (8)

beginbeginif (if (data[kdata[k] == 1)] == 1)

parity = ~parity;parity = ~parity;

k = k + 1;k = k + 1;

endendendend

endmoduleendmodule




Chapter 1

Verilog Nested Modules.Verilog Nested Modules. TheThe whilewhile looploop construct isconstruct issimilar to the C language.similar to the C language.

Listing 1.32Listing 1.32 Verilog behavioral model of a gated clock generator using theVerilog behavioral model of a gated clock generator using the

while loopwhile loop constructconstruct

modulemodule gated_clockgated_clock (output reg(output reg gclkgclk, input, input clkclk,, clkgateclkgate););

always@(clkalways@(clk or or clkgateclkgate))

beginbegin

while (while (clkgateclkgate))

gclkgclk == clkclk;;

endend

endmoduleendmodule




Chapter 1

Verilog FunctionVerilog FunctionListing 1.33Listing 1.33 Verilog module with a function which returns the greater of twoVerilog module with a function which returns the greater of two

88--bit signed variablesbit signed variables

module greater (input signed [7:0] a, b, output reg signed [7:0]module greater (input signed [7:0] a, b, output reg signed [7:0] c);c);

always @(a, b)always @(a, b)

beginbegin

c = great(a, b);c = great(a, b);

endend

function [7:0] great (input signed [7:0] x, y);function [7:0] great (input signed [7:0] x, y);

beginbegin

if (x >= y)if (x >= y)great = x;great = x;

elseelse

great = y;great = y;

endend

endfunctionendfunctionendmoduleendmodule




Chapter 1

Verilog TaskVerilog TaskListing 1.34Listing 1.34 Verilog module of a 1Verilog module of a 1--bit full adder with a task implementing twobit full adder with a task implementing two

11--bit half addersbit half adders

modulemodule full_add(outputfull_add(output reg sum, output regreg sum, output reg carry_outcarry_out, input a, b,, input a, b, carry_incarry_in););

regreg psumpsum, p1carry, p2carry;, p1carry, p2carry;

always@(aalways@(a, b,, b, carry_incarry_in))

beginbegin

half_adder(psum, p1carry, b, carry_in);half_adder(psum, p1carry, b, carry_in);half_adder(sum, p2carry, psum, a);half_adder(sum, p2carry, psum, a);

carry_out=p1carry | p2carry;carry_out=p1carry | p2carry;

endend

task half_adder(output half_sum, half_carry, input x, y);task half_adder(output half_sum, half_carry, input x, y);

beginbegin

half_sum=x ^ y;half_sum=x ^ y;

half_carry=x & y;half_carry=x & y;

endendendtaskendtask

endmoduleendmodule




Chapter 1

Finite State Machines (FSM)Finite State Machines (FSM)

Figure 1.5Figure 1.5





Chapter 1

XilinxXilinx StateCADStateCAD graphical interface for state machinegraphical interface for state machinedesign.design. Figure 1.7Figure 1.7




Chapter 1

Arbitrary Moore FSMArbitrary Moore FSM





Chapter 1

Arbitrary Moore FSMArbitrary Moore FSMListing 1.39Listing 1.39 Verilog HDL of the arbitrary Moore FSMVerilog HDL of the arbitrary Moore FSM

reg [2:0] state;reg [2:0] state;

always@(posedgealways@(posedge CLOCK)CLOCK)

beginbegin

if (RESET)if (RESET)

beginbeginstate <= 1;state <= 1;

X <= 0;X <= 0;

Y <= 0;Y <= 0;

Z <= 0;Z <= 0;endend

elseelse




Chapter 1

Arbitrary Moore FSMArbitrary Moore FSMcase (state)case (state)

1: begin1: begin

if (A | | B)if (A | | B)

state <= 2;state <= 2;

X <= 0;X <= 0;

Y <= 0;Y <= 0;

Z <= 0;Z <= 0;

endend2: begin2: begin

if (!A && C)if (!A && C)


else if (A && D)else if (A && D)state <= 3;state <= 3;

X <= 1;X <= 1;

Y <= 1;Y <= 1;

Z <= 0;Z <= 0;

endend

G




Chapter 1

Arbitrary Moore FSMArbitrary Moore FSM3: begin3: begin

if (!A | | !C)if (!A | | !C)


else if (A && C)else if (A && C)


X <= 0;X <= 0;

Y <= 0;Y <= 0;


4: begin4: begin

if (D)if (D)

state <= 5;state <= 5;X <= 0;X <= 0;

Y <= 1;Y <= 1;

Z <= 0;Z <= 0;

endend

E b dd d D i i P bl G t A




Chapter 1

Arbitrary Moore FSMArbitrary Moore FSM5: begin5: begin

if (!B && D)if (!B && D)


else if (B)else if (B)


X <= 1;X <= 1;

Y <= 0;Y <= 0;


default: state <= 1;default: state <= 1;

endcaseendcase

endend





Chapter 1

Controller Controller --Datapath Construct.Datapath Construct. TheThe datapathdatapath is theis themodule that inputs andmodule that inputs and

outputs data. The datapathoutputs data. The datapath

accepts control signalsaccepts control signals

from and returns statusfrom and returns status

signals to the controller.signals to the controller.






Chapter 1

Controller Controller --Datapath Construct.Datapath Construct. TheThe controller controller acceptsacceptscontrol inputs (stimuli) fromcontrol inputs (stimuli) from

and provides status outputand provides status output

signals to other modules.signals to other modules.






Chapter 1

C to Verilog Translation.C to Verilog Translation. C language assignment andC language assignment andloop statement construct.loop statement construct.






Chapter 1

C to Verilog Translation.C to Verilog Translation. C language branch statementC language branch statementconstruct.construct.






Chapter 1

C to Verilog Translation.C to Verilog Translation. Greatest common denominator Greatest common denominator (GCD) algorithm.(GCD) algorithm.

Listing 1.40Listing 1.40 Greatest common denominator C language algorithmGreatest common denominator C language algorithm

intint gcdgcd (int(int xinxin, int yin), int yin)

{{

int x, y;int x, y;

x =x = xinxin;;

y = yin;y = yin;

while(xwhile(x != y)!= y)

{{

if (x < y)if (x < y)

y = yy = y – – x;x;elseelse

x = xx = x – – y;y;

}}

return x;return x;

}}







Chapter 1

C to Verilog Translation.C to Verilog Translation.Verilog controller Verilog controller --

datapath construct for thedatapath construct for the

greatest commongreatest common

denominator denominator

(GCD) algorithm.(GCD) algorithm.






Chapter 1

C to Verilog Translation.C to Verilog Translation. GCD controller module.GCD controller module.

Listing 1.41Listing 1.41 Greatest common denominator C language algorithm VerilogGreatest common denominator C language algorithm Verilog

controller modulecontroller module

modulemodule gcdcontroller gcdcontroller (input clock,(input clock, gcddatagcddata,, lddatalddata,, xneqyxneqy,, xltyxlty, input, input xysubxysub,,

yxsubyxsub, output, output gcdinitgcdinit,, datagcddatagcd,, datalddatald,, subxysubxy,, subyxsubyx))

reg [2:0]reg [2:0] gcdstategcdstate;;

always@(posedgealways@(posedge clock)clock)

beginbegin

if (if (gcddatagcddata == 0)== 0)

beginbegingcdstategcdstate = 1;= 1;

datagcddatagcd = 0;= 0;

gcdinitgcdinit = 1;= 1;

datalddatald = 0;= 0;

endend

elseelse





Chapter 1

C to Verilog Translation.C to Verilog Translation. GCD controller module.GCD controller module.elseelse

case(gcdstatecase(gcdstate))

1: begin1: begin

gcdinitgcdinit = 0;= 0;

datalddatald = 1;= 1;

if (if (lddatalddata))

beginbegin

datalddatald = 0;= 0;gcdstategcdstate = 2;= 2;

endend

endend

2: begin2: begin if (if (xneqyxneqy))

gcdstategcdstate = 3;= 3;

elseelse


endend





Chapter 1

C to Verilog Translation.C to Verilog Translation. GCD controller module.GCD controller module.3: begin3: begin

if (if (xltyxlty))


elseelse


endend

4: begin4: begin

subyxsubyx=1;=1;if (if (yxsubyxsub))

beginbegin

subyxsubyx = 0;= 0;

gcdstategcdstate = 2;= 2;endend

endend





Chapter 1

C to Verilog Translation.C to Verilog Translation. GCD controller module.GCD controller module.5: begin5: begin

subxysubxy = 1;= 1;

if (if (xysubxysub))

beginbegin

subxysubxy = 0;= 0;


endend

endend6: begin6: begin

datagcddatagcd = 1;= 1;

gstategstate = 6;= 6;

endend

default:default: gstategstate = 6;= 6;

endcaseendcase

endend

endmoduleendmodule





Chapter 1

C to Verilog Translation.C to Verilog Translation. GCD datapath module.GCD datapath module.

Listing 1.42Listing 1.42 Greatest common denominator C language algorithm VerilogGreatest common denominator C language algorithm Verilog

datapath moduledatapath module

modulemodule gcddatapathgcddatapath (input clock,(input clock, gcdinitgcdinit,, datagcddatagcd,, datalddatald, input, input subxysubxy,, subyxsubyx,,

outputoutput lddatalddata, output, output xneqyxneqy,, xltyxlty,, xysubxysub,, yxsubyxsub,, inoutinout [15:0][15:0] xdataxdata,,

input signedinput signed ydataydata))

reg [15:0] x;reg [15:0] x;

reg [15:0] y;reg [15:0] y;always@(posedge clock)always@(posedge clock)

beginbegin

if (if (gcdinitgcdinit))

beginbeginlddatalddata = 0;= 0;

xneyxney = 0;= 0;

xltyxlty = 0;= 0;

xysubxysub = 0;= 0;

yxsubyxsub = 0;= 0;

endend





Chapter 1

C to Verilog Translation.C to Verilog Translation. GCD datapath module.GCD datapath module.if (if (datalddatald))

beginbegin

x =x = xdataxdata;;

y =y = ydataydata;;

if (x != y)if (x != y)

xneyxney = 1;= 1;


xltyxlty = 1;= 1;lddatalddata = 1;= 1;

endend

if (if (subxysubxy))

beginbegin

x = xx = x – – y;y;

if (x == y)if (x == y)

xneyxney=0;=0;


xltyxlty = 1;= 1;xysubxysub = 1;= 1;

endend





Chapter 1

C to Verilog Translation.C to Verilog Translation. GCD datapath module.GCD datapath module.if (if (subyxsubyx))

beginbegin

y = yy = y – – x;x;

if (x == y)if (x == y)

xneyxney = 0;= 0;


xltyxlty = 1;= 1;

yxsubyxsub = 1;= 1;endend

if (if (datagcddatagcd))

xdataxdata

= x;= x;

endend

endmoduleendmodule





Chapter 1

PGA and Microprocessor Comparison.PGA and Microprocessor Comparison. VerilogVerilogmodules can operate in parallel facilitating realmodules can operate in parallel facilitating real--timetime

operation.operation.

Listing 1.43Listing 1.43 Verilog HDL modules operating in parallel in an embeddedVerilog HDL modules operating in parallel in an embeddeddesign applicationdesign application

s3eadc M0 (CCLK,s3eadc M0 (CCLK, adcdavadcdav,, davadcdavadc, adc0data, adc1data,, adc0data, adc1data, adcsckadcsck,,

adcspodadcspod,, conadconad););adclcdadclcd M2 (CCLK, BTN0,M2 (CCLK, BTN0, resetlcdresetlcd,, clearlcdclearlcd,, homelcdhomelcd,, datalcddatalcd,, addrlcdaddrlcd,,

initlcdinitlcd,, lcdresetlcdreset,, lcdclear lcdclear ,, lcdhomelcdhome,, lcddatalcddata,, lcdaddr lcdaddr ,, lcddatinlcddatin,,

digitmuxdigitmux, data);, data);

lcdlcd M3 (CCLK,M3 (CCLK, resetlcdresetlcd,, clearlcdclearlcd,, homelcdhomelcd,, datalcddatalcd,, addrlcdaddrlcd,, lcdresetlcdreset,,

lcdclear lcdclear ,, lcdhomelcdhome,, lcddatalcddata,, lcdaddr lcdaddr ,, rslcdrslcd,, rwlcdrwlcd,, elcdelcd, lcdd,, lcdd,

lcddatinlcddatin,, initlcdinitlcd););

genampadcgenampadc M4 (CCLK, SW0, SW1, SW2, SW3,M4 (CCLK, SW0, SW1, SW2, SW3, ampdavampdav,, davampdavamp,,

ampcmd0, ampcmd1,ampcmd0, ampcmd1, adcdavadcdav,, davadcdavadc, adc0data, adc1data,, adc0data, adc1data,

digitmuxdigitmux, data);, data);





Chapter 1

PGA and Microprocessor ComparisonPGA and Microprocessor ComparisonListing 1.44Listing 1.44 Sequential processor data transfer in ASMSequential processor data transfer in ASM--86 for the Intel 808686 for the Intel 8086

sdatosdato proc near proc near ;SDATA from;SDATA from bxbx to DACto DAC

movmov ax,400Hax,400H ;IOW 400H;IOW 400H

movmov dx,axdx,ax

movmov cl,12cl,12 ;count for 12 SDATA bits;count for 12 SDATA bits

sdatlpsdatlp:: rolrol bx,1bx,1

movmov al,blal,bland al,1and al,1 ;SDATA bit 0, SCLK=0 bit 1;SDATA bit 0, SCLK=0 bit 1

outout dx,aldx,al

or al,2or al,2 ;SDATA bit 0, SCLK=1 bit 1;SDATA bit 0, SCLK=1 bit 1

outout

dx,aldx,al

and al,0FDHand al,0FDH

outout dx,aldx,al ;SDATA bit 0, SCLK=0 bit 1;SDATA bit 0, SCLK=0 bit 1

decdec clcl ;decrement count;decrement count

jnz jnz sdatlpsdatlp ;jump if count is not zero;jump if count is not zero

retretsdatosdato endpendp





Chapter 1

PGA and Microprocessor Comparison.PGA and Microprocessor Comparison. VerilogVerilogcontroller controller --datapath construct for the data transfer.datapath construct for the data transfer.






Chapter 1

PGA and Microprocessor Comparison.PGA and Microprocessor Comparison. Data transfer Data transfer datapath module.datapath module.

Listing 1.45Listing 1.45 Verilog datapath module for the data transfer Verilog datapath module for the data transfer

module sdat0(input clock,module sdat0(input clock, dacdavdacdav, input [11:0] data, output reg, input [11:0] data, output reg sdatasdata, output, output

regreg sclksclk, output reg, output reg davdacdavdac););

reg [1:0]reg [1:0] dacstatedacstate;;

integer i;integer i;

always@(posedge clock)always@(posedge clock)

beginbegin

if (if (dacdavdacdav == 0)== 0)beginbegin

i = 12;i = 12;

dacstatedacstate = 0;= 0;

sclksclk = 1;= 1;

endend




g g g y

Chapter 1


elseelse

beginbegin davdacdavdac = 0;= 0;

case (case (dacstatedacstate))

0: begin0: begin

i = ii = i – – 1;1;

if (i == 0)if (i == 0)dasstatedasstate = 3;= 3;

elseelse

sdatasdata == data[idata[i – – 1];1];

dacstatedacstate = 1;= 1;endend




g g g y

Chapter 1


1: begin1: begin

sclksclk = 0;= 0;dacstatedacstate = 2;= 2;

endend

2: begin2: begin

sclksclk = 1;= 1;


3: begin3: begin

davdacdavdac = 1;= 1;


endcaseendcase

endend

endend

endmoduleendmodule



End of Chapter 1End of Chapter 1

Verilog HardwareVerilog Hardware

Description LanguageDescription Language

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EDPGA Chapter 1