MSD P10345

Automated Transistor Noise Characterization Platform

Detailed Design Review

Project overview

The purpose of the Automated Transistor Noise Characterization Platform, nicknamed Viking, is to provide researchers a fast and easy way of characterizing the noise in on-wafer devices by providing an electrically quiet environment and automation of connection switching, instrument control, and data acquisition.

Major competing products retail for over one million dollars and are marketed to large corporations with an interest in characterizing thousands of devices of widely varying types for use in R&D or production testing. Small research budgets do not allow for purchase of these expensive systems, nor do they require the extensive functionality provided. The Viking Platform aims to address the needs of small research groups on a low budget, interested in retrofitting an existing, low-cost wafer probe station with a low-noise measurement environment.

The major design components of the Viking Platform include:

A shielded container to reduce the effects of environmental RF and EMI noise A low noise amplifier to provide gain to very low level signals inside the shielded environment A low noise current source to provide bias currents to devices under test without contributing

additional noise User-controllable bias points, including a high-resolution mode for the current source A software interface that controls all measurement instruments and the low-noise biasing

circuits and automates the measurement process.

Review Objectives

The most important objective of this review is to examine critical design areas (mechanical, digital, analog, and interfaces) to find any errors, so they can be corrected before the first PCB is ordered.

The objectives of this design review are to:

Introduce the proposed system and how it meets customer needs. Explain the mechanical design of the system

o Get input on mechanical design from attendees. Explain the computer interface board (nicknamed Odin)

o Get input from attendees Explain low-noise analog circuit design

o Bias voltage generationo Low noise amplifiero Low noise current source

Get input on each design from attendees Address specific design issues (see below) Defend circuit topology, show noise analysis performed to demonstrate system

feasibility

The design review is aimed as a sanity check on the difficult parts of the design. The circuit topology will be completed over exam week, incorporating elements learned at the design review. Thus, the PCB layout is scheduled to be completed over break week and assembly and testing and revision will begin after assembly.

Description of Key Circuits & ComponentsThis is a brief overview of important circuits designed for the TFT Noise Characterization Platform. Snapshots from the complete schematic are shown with a short description of how each circuit operates. Several terms to note when reading the descriptions are listed below.

Viking: Name given to the overall TFT Noise Characterization Platform. Valhalla: Name given to the RF shielding box which fits over the existing probe station. Odin: Name given to the PCB board and which contains the digital circuitry and communications

with the lab PC. Thor: Name given to the PCB containing the analog circuitry responsible for the DUT biasing and

noise amplification.

Gate & Low Noise Amplifier (LNA) Offset Bias (VBIAS) Circuitry

Both the DUT gate bias voltage and LNA offset correction use duplicate circuitry to generate the voltages needed at each node. The only difference between the two is the existence of Relay C on the gate bias circuit. This relay is first set to connect the DUT gate to the B1500 Semi-conductor Analyzer to generate an I-V plot for the DUT. After the I-V curve is generated Relay C is toggled to connect the gate of DUT to the biasing circuit.

Once the user selects a bias point from the gathered I-V curves the gate bias/ LNA offset information is sent from the computer to the Odin board via connections into Valhalla. The CPLD on Odin then determines the proper input word for the AD7547 DAC in order to produce the correct voltage on output. The current output of the DAC is converted to a voltage between 0V and 10V by the first AD712 op-amp. The second AD712 then allows for up to a ±10V DC voltage on the gate of the DUT depending on whether it is an NMOS or PMOS device.

Up until the output of the second AD712 op-amp the voltage bias circuit was adapted from the data sheet of the AD7547; in order to make the bias voltage meet the required noise specification it would have to be filtered before touching the DUT gate node. Reducing the bias voltage noise to meet spec required a low-pass filter with a large RC time constant. To bypass lengthy charge times on the 1000µF filter capacitor a small pre-charge resistor is connected in parallel to the 1MΩ filtering resistor to speed up charging the filter capacitor. Relay B is toggled via a signal from Odin in order to connect the small pre-charge resistor. Finally the output of the low-pass RC filter is directly connected to the appropriate node.

Low Noise Amplifier Circuit

The output of the LNA bias voltage circuit is fed into the positive terminal of the first AD549 amplifier. The op-amp will then force VBIAS to appear at its negative terminal and at the drain of the DUT. To ensure VBIAS will appear correctly at the drain of the DUT the resistor on the negative terminal of the op-amp was made small to provide negligible voltage drop between the two nodes. Relays F through H allow for the correct amount of gain to be selected so that once the low voltage noise signal is amplified it is able to be accurately measured without clipping. It is also important to note that this first amplifier will be located as close to the DUT as possible to reduce the chance of noise coupling into the signal and corrupting measurements.

The second AD549 is needed to interface with the equipment taking the 1/f noise measurements. Relay I will connect the 100Ω resistor to the output in order to match the input impedance of the Spectrum analyzer. Similarly when the Dynamic Signal Analyzer is measuring the DUT Relay I will toggle the 1MΩ resistor into place.

Offset VBIAS

Low Noise Current Source

The low noise current source is designed to be an adjustable current source with very low output current noise.

A control voltage is received from the DAC to set the output current. This voltage is related to the output current by Iout = V/Rc, where Rc is either 10k or 243k, depending on whether the unit is in high or low-current mode. The AD797 operational amplifier tries to mirror the control voltage signal to the negative terminal. The JFET in the feedback loop will therefore be required to sink an amount of current into Rc such that the voltage across Rc will be equal to the control voltage from the DAC. A low pass filter is used on the gate of the JFET to cancel any noise contributions from the AD797 and preceding circuitry, and a large bypass capacitor is used across Rc to filter out noise at that node. Because the filter capacitors are so large (0.33 F), a buffer (HA9P5002) is included to slew the capacitors.

Due to limited voltage rails and the desire to keep both the JFET and the DUT far into saturation, the maximum voltage allowable across R is 1V. Thus, the voltage input from the DAC will be between -13V and -12V with 12 bit resolution in that range. This enables a minimum current of approximately 1nA in low current mode, and a maximum of 100uA in high current mode. Careful attention was paid to the voltage referencing of these circuits to ensure proper operation (Vref, VDD, and VSS of all circuits were calculated to ensure the described operation).

Design Concerns

Some design concerns:

Is the buffer, as shown above, a good solution for slewing the large capacitors? Concerns with noise analysis - if this analysis is incorrect, this large resistance could add a large

amount of noise to the DUT drain node. Is the bias voltage on the second amplifier stage of the LNA correct? (gnd or Vbias?) Theoretically, a JFET will operate to source 1nA in the linear region if the VDS is kept high

enough. Are there any risks with operating a JFET far below its rated current, assuming the VDS is forced high enough?

Is the proposed solution of voltage referencing on bias-current DAC to achieve the desired output levels on the current-reference resistor appropriate?

It has been noted that we are currently using parallel-input current DACs to produce a voltage output. These are a remnant of a previous design, and several suitable voltage-output DACs have been found that will help reduce pin count and circuit complexity.

Digital Circuitry on Odin

The main component of the Odin board is a Xilinx CoolRunner II XC2C64A CPLD. This part was chosen because it was available in a VQ44 package, which helps minimize board space without the complexity of a BGA device, and providing a sufficient 33 I/O pins. Ignoring BGA devices, competing products from Altera are only available in 100 TQFP packages.

To isolate the ground used by the controller PC, inputs to the CPLD are isolated using Fairchild Semiconductor FOD8001-ND optoisolators. These devices take a digital input and produce an isolated digital output. Since the NI USB 6501 uses a 5V Vcc and the CPLD requires a 3.3V Vccio, these devices also perform the necessary level shifting.

The CPLD’s digital outputs are connected to the Thor board through a 30 pin connector. This provides 30 I/Os for control of the DACs and relays used on the Thor device. A 3.3V I/O voltage (Vccio) was chosen for compatibility with the parts selected for the Thor board. The CPLD is able to configure its I/O pins for LVTTL or LVCMOS operation.

In addition to the 3.3V Vccio supply, the CPLD requires a 1.8V supply for its logic core. (Vcc) To provide these rails, National Semiconductor LP2989 series low-dropout linear regulators were chosen. These devices use a standard SOIC-8 package (without large thermal dissipation/grounding paddle), are able to provide enough current to CPLD under worst case conditions, (500 mA max, Xilinx quotes Icc of 175 mA maximum) and the regulators also provide an active-low error flag, which is used to drive an LED to indicate a low-battery condition.

The final element required to use the CPLD is the JTAG test/programming interface. To facilitate easy programming using a Xilinx Parallel Cable IV or Xilinx USB Platform Cable II, a 14 pin Molex 87833-1420 connector is used, so the 14 pin ribbon cable included with those two programming cables can be used without modification. Dr. Lukowiak in the Computer Engineering department has access to a Xilinx USB Platform Cable II, and mentioned that it would be possible to borrow it when needed.

Computer Interface to Odin

The controller PC running the Labview software will connect to the Odin board using an NI USB 6501 device. This device provides 24 digital I/O lines at 5V TTL logic levels. While only 3 I/Os are necessary for the current design, this is the least expensive USB interface provided by National Instruments.

This device allows easy control with the Labview software, with no driver programming required.

CPLD Design

The CPLD will use a three wire half-duplex SPI interface to receive configuration information from the PC. To allow for easy control, the data input is broken into an instruction (4 bits) and data. (20 bits) The following image shows the operation of the bus:

While not in use, the clock, data, and strobe bits are held at Vcc.

The instruction input is processed by a state machine, which then enables the appropriate register or state machine inside the CPLD to process the data. The internal structure of the CPLD is shown below:

Viking Control Software

To control the developed circuitry and test equipment, a Labview-based control application, Viking, will be developed. The software has to control an HP3562A dynamic signal analyzer, Agilent B1500 semiconductor parameter analyzer, an Agilent N9010A Spectrum Analyzer, and the USB 6051 board used to communicate with Odin board. Labview drivers for all of these devices are available from National Instruments, so the majority of effort will be Viking specific. The following algorithm will be implemented to take a noise measurement:

After implementing this process, a GUI application will be created to allow easy use of the application.

Description of Key Mechanical Design Areas and Requirements:

The main goal of the mechanical component of the TFT noise characterization is to provide a continuous ground plane around a noise measurement system that uses Cascade Microtech’s M150 Measurement Platform. This ground plane acts as a shield to block the discernible influence of RF and EMI interference from sources external to the system. This shield, hereafter referred to as “Valhalla” [Mechanical Figures 7 and 8], was required to attach to the M150 Measurement platform without the modification of the platform, allow a card created by Sigma Probe to make contact with silicon or glass wafers on the M150 wafer chuck, contain the electronic circuitry needed for noise characterization, provide a way to view the probes and landing zones, as well as the on-wafer transistors, through the M150’s microscope, and allows for the measurement of all transistors, at any position, on the wafer. [Table 1] All of these design requirements, along with the primary requirement of providing an electrically continuous shield, can all be met using Valhalla’s current geometry.

Requirement Important Design RestrictionsProvide RF and EMI shield Must provide a continuous ground plane

encompassing the transistor wafer, the Sigma Probe card, and the system’s electronic components.

Attach to M150 Measurement Platform Wafer chuck diameter: 6”Distance between the bottom of the Sigma Probe card and the M150 bench top: 1.375” Thickness of bench top: .875”Minimum distance between bench top and microscope: .875”Distance between the M150’s support rails: 24”Distance between the wafer chuck and corner brackets: .0625”

Allow Sigma Probe card to measure transistors Thickness: .0625”Width: 4.5”(Max) 3.875(Min)Length: 7.375”Needle Height: .03125”Needle Holder Height: .0625”Distance from end of card to needle window: 2.25”Contact Circle Diameter: 2.5”

Contain electrical system components Power: 5 9V batteriesAnalog PCB Width: 4”Analog PCB Length: 6”Digital PCB Width: 2.5”Digital PCB Length: 3.8”

Table 1: System Requirements and Design Restrictions

The restrictions presented by the system requirements and the unique design of the M150 demanded a very careful approach to the design of Valhalla. Because the design was not allowed to

damage or alter the M150 probe station and because the station was not designed to contain an RF/EMI shield, the design was geometrically constrained in many regards. These restrictions posed the interesting design challenge of fully containing the measurement system in a continuous ground plane, while retaining the full functionality of the probe station.

Mechanical Design Description

The large rectangular plates found affixed to both the collar and the holder (Mechanical Figures 1 and 2) are designed to interface through a thin layer of compressible conductive foam to provide a continuous electrical contact while still allowing the wafer chuck to move. The card-holder’s odd geometry was created so that it would slide onto the probe stations standard card holder, provide a well that the card can sit in, connect to the large rectangular interface, and still allow the card to be within 0.09375” of the wafer. The well is then sealed by the window’s complementary insert. A plate with notched rails, connected to the top of the insert, extends horizontally to the same width as the lower rails so the entire assembly can be clamped together by the probe station’s standard card holder. The height of the viewing window and its supporting metal structure from the probe card was dimensioned so that it does not come too near the microscope and so that the conductive glass does not touch the card. The width and length of this viewport were designed to show the entire probe card contact circle. A corridor that runs from the viewport to near the back edge of the structure is kept at least .25” away from the card to allow for the connection of wires to the probe card. The board box then fits onto the complementary slot in the window. This slotted connection was designed to have an insert and an additional plate that overlaps the rear wall of the window for mechanical stability, while still providing a channel through which wires can run. Additional supports, in the form of horizontal brackets that bolt to the probe stations standard card holder, have been added on the wings of the board box to assist in supporting it. The box was sized to contain 2 PCBs as well as five 9V batteries.

Mechanical Figures:

*Detailed CAD Drawings will be provided on Friday, February 12, 2010. These are not necessary for the preread package.

Figure Object Name Purpose Description1 Collar The collar is structure designed to fit onto the wafer chuck on

the M150 probe station, as well as provide a large electrical contact surface.

2 Holder An object that fits around the M150 probe card holder, provides a large electrical contact area, holds the probe card, fits under the probe station’s bench top and allows the probe card tips to make contact with a wafer held on the probe station’s chuck

3 Window The window fits into the holder to contain the probe card, allows the operator to view the probe card tips without disrupting the shield, provides support for the board box, and does not touch the probe station’s microscope.

4 Board Box The board box attaches to both the window, bolts to the M150

probe card holder, and contains the circuitry and power for the systems electronic components.

5 Lid The lid seals the board box.6 Insert The insert attaches to, and completes the perimeter ground for,

the holder.7 Valhalla Valhalla is a containment unit that houses a system for

characterizing noise performance using the M150 probe station that provides Rf and emi protection.

8 Valhalla See above

Figure 1

Figure 2

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Figure 8