edaTrend DATE07

DATE07April 16-20, 2007Nice, France

Collected EDA essentials in industry and business

Table of Contents

and Example

About edaTrend DATE07The “edaTrend DATE07” report summarizes the important topics and trends from the 10th “De-sign Automation and Test” Conference (DATE) in Nice, France. Due to the huge amount of informa-tion presented at DATE, the “edaTrend DATE07” report focuses on the conference’s top events, such as its keynotes and panel discussions. Here, you will find many essential details and personal impressions gathered on site by our team of edi-tors.

The “edaTrend DATE07” report is divided into several sections: The first section contains gener-al information about DATE, the second discusses the technical program (and the panel sessions in particular), and the third focuses on the panel ses-sions in the Exhibition Theatre, but also includes some impressions from the exhibition. One very special highlight of Section 3 is an interview with Chris Rowen, CEO and President of Tensilica, who spoke exclusively with edacentrum on the subject of ESL and configurable processors.

Fig. 1: DATE07 was held at Acropolis, Nice, France

Fig. 2: The beach of Nice

Imprint„edaTrend DATE07“ was published in June 2007 by edacentrum GmbH.

edacentrum GmbHSchneiderberg 3230167 Hanover, Germany

Editor: Ralf PoppAuthors: See page 102f.Lecturer: Mike MackenDesign & Layout: Niklas MöllerPrinted by Druckerei Hartmann GmbH, Germany

Thanks to all contributors to this report.

Copyright 2007 by edacentrum GmbH

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ContentHey, ho, let’s go (to DATE07) .......................................................................................... 6

edaTrend DATE07 starting over for the first timeTrend Report on the DATE07 Exhibition & Conference in Nice, France, April 16 – 20, 2007

Written and edited by edacentrum, Germany

Is More Moore Possible? ...............................................................................................10Challenges of digital consumer and mobile SoCsPLENARY SESSION KEYNOTE 1 –

Tohru Furuyama – Challenges of digital consumer and mobile SoC’s: More Moore possible? –

Tue, 0900-1000, Apollon

Survival of the Fittest Most Flexible ............................................................................ 13Was Darwin wrong?PLEANRY SESSION KEYNOTE 2 –

Alan Naumann – Was Darwin wrong? Has design evolution stopped at the RT level … or will software and custom processors (or system-level design) extend Moore’s law? –

Tue, 0950 - 1030, Apollon.

Configurability on the Consumer Market ................................................................... 16Trade-off between flexibility and cost1.1 EXECUTIVE SESSION –

Bridging the Field Programmable Reconfigurable SoC (FPSoC) Divide –

Tue, 1130 - 1300, Hermes, Level 2

Don’t Be Afraid of Risk: Be as Bold as Brass! ............................................................. 18Voting for a successful fabless company2.1. EXECUTIVE SESSION –

Building a successful business model as a European fabless company –

Tue, 1430 - 1600, Hermes Level 2

How to Avoid the Minotaur in the Labyrinth of Performance ................................... 20Power and parallelism rule terascale integration in microprocessor design2.4. PANEL SESSION – HOT TOPIC:

Microprocessors in the Era of Terascale Integration –

Tue, 14:30-16:00, Thalie, Level 3

Reliability Rules in Automotive Electronics ............................................................... 24Panel discussed the challenges of automotive electronics design3.1. EXECUTIVE SESSION –

A Roundtable on Automotive Systems Design –

Tue 1600 - 1730, Hermes Level 2

DFM and DFY – A Matter of Equipment or Attitude? ................................................. 27Discussion about the best way to do DFM/DFY3.6 PANEL SESSION –

Should You Trust the Surgeon or the Family Doctor? –

Tue, 16:30-18:00, Erato, Level 3

Everyday Life as the Killer Application ...................................................................... 31Lunchtime keynote presents Nokia’s ubiquitous communication approach5.1.2. WEDNESDAY LUNCHTIME KEYNOTE –

Heikki Huomo – Emerging solutions technology and business technology views for ubiquitous communica-tion –

Wed 1340 - 1430, Athena Level 2

May the Road Rise to Meet You ................................................................................... 33System-in-a-Package – Viewed from different Perspectives5.4 EMBEDDED TUTORIAL –

Heterogeneous Systems on Chip and Systems in Package –

Wed, 1100 - 1230, Thalie, Level 3

Size Doesn’t Matter? – Yes it Does!.............................................................................. 35Mixed-Signal issues and aches with 65 nm6.6 PANEL SESSION –

Life Begins at 65 – Unless You Are Mixed Signal –

Wed, 14:30 – 16:00, Erato, Level 3

How Can We Test Flying Cars? ..................................................................................... 39Panel addressed future trends in testing7.1 PANEL SESSION –

Testing 35 Billion Transistors in 2020 – Is It Possible? –

Wed, 1630 - 1800, Gallieni AB, Level 2

Embedded Systems Somewhere Over the Rainbow ................................................. 42Aerospace between military and civilians, business and innovation8.1. TUTORIAL SESSION –

State of the Art for Safety-Critical Embedded Systems (Space & Aeronautics Day) –

Tue, 08:30-10:00, Hermes, Level 2

Just Enough Flexibility ................................................................................................. 46Trading energy for flexibility with customizable processors8.6 EMBEDDED TUTORIAL/PANEL –

The future of customizable processors: Are we there yet? –

Thu, 0830 - 1000, Erato, Level 3

I am Flying, Passing High Clouds... ............................................................................. 48Embedded Systems in aeronautic applications9.1.2 LUNCH TIME KEYNOTE –

Flying embedded: The industrial scene and challenges for embedded systems in aeronautics and space –

Thu, 1330 - 1400, Athena, Level 2

ENIAC and ARTEMIS Ready to Take Off ...................................................................... 50Joint technology initiatives include Design Automation10.4. EMBEDDED TUTORIAL –

EDA: A Pivotal Theme in the European Technology Platforms ARTEMIS and ENIAC –

Thu, 1400 - 1530, Thalie Level 1

Open Source is Indispensable ..................................................................................... 53Panel discusses pros and cons of Open-Source software11.1. PANEL SESSION –

Towards Total Open Source in Aeronautics and Space? –

Thu, 1600 - 1630, Hermes Level 2

Is Another Network Revolution Coming? ................................................................... 57Networks on chip: New hope or a pain in the neck?X1 EXHIBITION THEATRE PANEL SESSION –

Networks on Chip: Panacea for IP Integration & SoC Design? –

Tue, 1040 - 1140, Rhodes Level 2

Improving Design Efficiency ........................................................................................ 60Realizing SoC designs using high-level approachesX2 EXHIBITION THEATRE TESTIMONIAL SESSION –

How to Realize SoC Designs Using High Level Approaches? –

Tue, 1140 - 1300, Rhodes. Level 2

My Car is Multilingual .................................................................................................. 66Federation and harmonization on standard languagesX5 EXHIBITION THEATRE PANEL SESSION –

Multilanguage SoC Design –

Tue, 1600 - 1700, Rhodes Level 2

Next-Generation Electronic System Development .................................................... 68Shake it! Mixing MDD and ESL technologiesX6 EXHIBITION THEATRE PRESENTATION –

The MARTES Project. Combining MDD and ESL Technologies for Addressing the Challenges of Next-gen-eration Electronic Systems Development –

Tue, 1700 - 1745, Rhodes Level 2

Welcome to the “Multies” ............................................................................................ 71MPSoC design: From application heaven to deep Sub-Micron HellX7 EXHIBTION THEATRE PANEL SESSION –

Meeting of Hardware and Software – It’s Not Coming; It’s Here! –

Wed 1010 - 1120, Rhodes Level 2

Talk, Talk, Talkin‘ on Performance‘s Door ..................................................................... 73Performance or less performance – That is the questionX8 EXHIBITION THEATRE TESTIMONIALS –

How to Ensure Proper Performance of SoC Designs–

Wed 1120 -1200, Rhodes Level 2

Is Open Source a Threat? ..............................................................................................76De-facto standards and Open SourceX9 EXHIBITION THEATRE PRESENTATION –

GreenSocs: Collaborative Work on ESL Infrastructure, User Experience and Ecosystem –

Wed., 12:00 – 12:40, Rhodes Level 2

Do Analog Designers Wear a Tie? ................................................................................ 80Panel discusses the essence of analogX10 EXHIBITION THEATRE PANEL SESSION –

Analog Design: Still More Art Than Engineering? –

Wed, 1300 -1400, Rhodes Level 2

Wanted: Compilers for Utilizing MPSoCs ................................................................... 84Insufficient compiler technology threatens to stop Moore’s LawX11 EXHIBITION THEATRE PANEL SESSION –

Taming the Dragon: Putting Compiler Technology to Work–

Wed, 1400 - 1500, Rhodes Level 2

Building a Better Verification Plan ............................................................................... 86Importing predictability and confidence for verificationX12 EXHIBITION THEATRE PANEL SESSION –

Building a Better Verification Plan for Greater Predictability and Confidence to Innovate –

Wed, 1600 - 1700, Rhodes Level 2

Exhibition Walkabout .................................................................................................... 90Editors’ Choice

ESL and the Adoption of Configurable Core Methodologies .................................... 97Interview with Chris Rowen, President and CEO of TensilicaInterview held by Peter Neumann

Still Looking for the Heirs of HDL ...............................................................................101Commentary

About us .......................................................................................................................102edacentrum and edaTrend Authors

Technical

Business

Innovative

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Just Enough FlexibilityTrading energy for flexibility with cus-tomizable processors

8.6 EMBEDDED TUTORIAL/PANEL – The future of customizable processors: Are we there yet? – Thu, 0830 - 1000, Erato, Level 3

Keywords: MPSoC, ESL, configurable, extendible, processor, soft-ware, compiler, heterogeneous, multi-processor

Abstract

Customizable processors are being used increas-ingly in SoC designs. During the past few years, they have proven to be a good way to solve the conflicting flexibility and performance require-ments in embedded systems design. While their usefulness has been demonstrated in a wide range of products, this panel addressed the chal-lenges that remain.

Panelists

• P. Paulin, STMicroelectronics (Moderator)• L. Pozzi, Lugano U (Tutorial Speaker)• C. Rowen, Tensilica• H. Meyr, Aachen U / CoWare• N. Topham, ARC• N. Wehn, Kaiserslautern U• J. M. Moutin, STMicroelectronics• P. Young, Nemerix

Energy vs. Flexibility

Although it started at 8:30 a.m. on the day after the DATE event, a large audience attended this panel discussion. The excellent tutorial speaker, Laura Pozzi, and the experienced panel modera-tor, Pierre Paulin, made it worth getting up early.

The future of customizable cores is safe. This be-came obvious within just a few minutes.

Small changes to the instruction set architecture (ISA) of a generic RISC can have a significant influence on performance and power. If, for ex-ample, the inner loop of a computation-intensive data processing algorithm can be sped up by sup-plying the designer with specialized instructions, a performance improvement of 5 to 10 times the level of the overall algorithm is not unusual.

On the other hand, vectorization of data pro-cessing can lead to a decreased clock frequency which, in turn, means less power consumption.

“If your application allows you to use a RISC with extensions, you should do so.”Heinrich Meyr, University of Aachen / Coware

The question, however, is if this should be done semi-automatically with manually extended and configured RISC processor core templates or with fully-customized processors. Both methods require a new mindset on the part of the hard-ware designer, who now must have a clear un-derstanding of the software algorithm running on the core. Furthermore, good communication between the software designer optimizing the algorithm and the hardware designer providing the means for it is a must.

“Automation is the low-hanging fruit.”Chris Rowen, CEO of Tensilica

The question in which way this is done, however, is associated with significant commercial impact.

Overall impression

´´´´´Excellent speaker / moderator, good presen-tations, hot topic

Fig. 1: Moderator P Paulin from ST Microelectronics

www.edacentrum.de/edatrend | edaTrend DATE07 | April 2007 | Page 47

If area and/or power are high-priority issues for the design in question, a fully customizable pro-cessor design approach might be the best choice. These implementations, therefore, tend to be tar-geted to one specific application.

If the time-to-market window is most critical, a more highly automated method using a proces-sor template approach is probably faster for im-plementation and verification. A good approach here is to not only target a specific application, but also make the processor generic for a specific domain of applications. This additionally opens up the door for reuse of designs, late specifica-tion changes, and application software updates.

Another important aspect is royalties. The mar-ket segment that a company is addressing might force it to build an in-house, royalty-free core so that the end product fits into a certain range of production costs. The use of a configurable pro-cessor template – which currently always involves royalties – might not be an option here.

One big disadvantage of fully customizable cores, however, was missing during the discussion: verification of a processor is non-trivial and can be considered a highly sophisticated task. This comes for free when you use processor tem-plates.

No matter what strategy is used, a design with customizable processors will only be accepted in the future if automated software tool-chain generation is provided. Then the question is not whether or not you should use configurable cores, but what to watch out for when you do.

For this reason, Phil Young of Nemerix strongly recommended that HW/Software interactions should be simplified in order not to loose perfor-mance at the interface. Furthermore, the impact of multi-threaded applications and pre-emptive context saving must be taken care of. Finally, data-structure ordering has a huge impact on accelerated hardware. Or simply speaking: Ul-timately, load/store is limiting data processing systems.

“Don’t leave the architecture entirely to a tool.”Phil Young, Chief Scientist, Nemerix

There is also a trade-off between algorithm vs. implementation optimization. Since experts know the applications best, they should not leave the architecture entirely to a tool. Automation processes are not able to replace the designers’ knowledge of applications and algorithms.

So will we see heterogeneous or homogeneous multi-processor systems in the future? The panel agreed that fully homogeneous MP systems will not be mainstream for some time. A mixture of both, however (where, for example, a main CPU oversees a set of homogeneous data processing processor cores), is already available in some products today. Probably the biggest future chal-lenge is the interaction of cores and the automa-tion of partitioning software on multi-processor systems-on-chip (MPSoC).

Conclusion

Customizable, configurable cores already reach a significant volume in shipped units today. So are we there yet? The answer is probably yes.

However choosing the right approach, i.e. a fully customizable core or an extendable RISC, de-pends significantly on the application.

A design with configurable and extendable cores speeds up the design process and offers a con-siderable advantage in verification, since the pro-cessor comes as a pre-verified piece of IP.

The designer’s knowledge of the application can never be replaced. So for very specific applica-tions, fully customizable processors are probably the best option.

Or to quote Prof. Meyr: “It’s not about design au-tomation, it’s about design efficiency in cost.”

Author

Peter Neumann, edacentrum

Fig. 1: Chris Rowen from Tensilica, a panelist full of en-gagement

Technical

Business

Innovative

Page 102 | edaTrend DATE07 | April 2007 | www.edacentrum.de/edatrend

About usedacentrum and edaTrend authors

The edacentrum is an independent organization dedicated to the promo-tion of research and development in the area of electronic design automa-

tion (EDA). Its main role is to initiate, evaluate and supervise industry driven EDA R&D projects and to provide individual services in the EDA sec-tor. Further by encouraging cluster research proj-ects and EDA networks, it bundles and reinforces the EDA expertise of universities and research institutes.

The edacentrum provides individual services in the EDA sector, including consulting, proj-ect management, the organization of trainings, workshops and networking events and provides a communication platform to the EDA communi-ty. The edacentrum actively engages in public re-lations in order to sensitize higher management levels, the public and the political arena about the central importance of design automation in solving the system and silicon complexity prob-lems in microelectronics.

The edacentrum consists of an association (edacentrum e.V.) and a company (edacentrum GmbH). The association operates on behalf of its members and the projects supported by it and actively engages in public relations for EDA. The company provides individual services in the EDA sector. At present more than 50 companies are member of the edacentrum e.V. The association is open to all persons and legal entities.

Dr. Jürgen Haase is Office Director of edacentrum e. V. since 2001 and manages the office of edacentrum in Hanover. In his previous positions he worked for the Institute for Network-

and System Theory at University of Stuttgart, for Philips Communications Industry AG in Nürnberg and for Sican GmbH/sci-worx GmbH in Hannover on applications of digital video communication, on optical telecommunication systems, and on ASIC and SoC designs. He was involved in a lot of international R&D projects and managed the design of numerous ASICs as design services for customers based in Europe, US and Asia. (haase@edacentrum.de)

Dr. Cordula Hansen received her Dipl.-Inf. degree in computer sci-ence in 1993 from the University Karlsruhe (TH), Germany. From 1993 to 1995 she worked for a Ger-

man EDA company called ISDATA, where she was responsible for the product development of VHDL synthesis tools. From 1996 to 2001 she worked for the Research Center for Information Technologies (FZI) in Karlsruhe and the Department of Com-puter Engineering at the University of Tübingen, where she received her PhD in 1999. Her research interests included high level synthesis and test bench generation. In 2001 she joined edacentrum and is responsible for R&D project consulting, product development and process management. (hansen@edacentrum.de)

Technical

Business

Innovative

www.edacentrum.de/edatrend | edaTrend DATE07 | April 2007 | Page 103

Dr. Dieter Treytnar, received his PhD in Electrical Engineering from the Uni-versity of Hanover, Germany. His the-sis is about „The influence of parasitic effects in nanometer interconnect sys-

tems on the digital test pattern quality“ in 2005. From 1997 to 2002 he worked at the Institute of Electromagnetic Theory and Microwave Tech-nique, University of Hanover in the field of Sig-nal Integrity Problems and Test in Deep Submi-cron Designs arising from Interconnects between Cores. In February 2002 he joined edacentrum. (treytnar@edacentrum.de)

Dr. Andreas Vörg received his Dipl.-Ing. in electrical engineering with em-phasis on technical information pro-cessing in 2000 from the University of Karlsruhe, Germany. 5 years later

he received his PhD in computer science in 2005 from the University of Tuebingen, Germany. His field of experience is the automated qualification and delivery of reusable components (IP) since 2000. In February 2005 he joined edacentrum where he is responsible for EDA consulting ser-vices and management of EDA funding projects. (vörg@edacentrum.de)

Peter Neumann holds a BEng Hons in Computer and Information En-gineering from Southbank Univer-sity London, and a Dipl. Ing. (FH) in Electronic Engineering from Fach-hochschule Bremen. For more than

a decade he has been working in industry in various digital areas including Design Flow, IP Qualification, Chip Design and Verification, and Top-Level SoC Integration. The last two years he spent in the field of Configurable Proces-sors. Peter joined edacentrum in April 2007 and is responsible for Business Development. (neumann@edacentrum.de)

Ralf Popp received his Dipl.-Ing. de-gree in electrical engineering in 1996 from the University of Hanover, Ger-many. From 1997 to 2002 he worked at the Institute of Microelectronic Sys-

tems, University of Hanover in the field of com-puter-aided design of analog circuits. His main working area were symbolic analysis, behavioral modeling and simulation of analog and MS-cir-cuits, a field in which he currently writes his PhD thesis. In April 2002 he joined edacentrum and is responsible for public relations and marketing. (popp@edacentrum.de)

Susanne Sass received her Dipl.-Ing. in electrical engineering with main focus on technical computer science/computer engineering in autumn 2006. Her diploma thesis focussed on developing a hard-/software environment to analyze

the status of a real time operating system. She joined edacentrum in January 2007 and is now responsible for comprehensive tasks in man-agement and coordination of research projects. (sass@edacentrum.de)

edacentrum GmbHSchneiderberg 3230167 HannoverGermany

info@edacentrum.dewww.edacentrum.de/edatrend