EDA360 the Way Forward Vision

8/7/2019 EDA360 the Way Forward Vision

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The Way Forward for Electronic Design

As founder of an organization that is transforming the economics and technology of an

industry so that we can improve opportunity for millions, I am constantly watching what

others are doing. Cadence has a vision and model with the potential to transform the

economics and performance of the microprocessor industry and, by extension, devices

every consumer takes for granted. This document outlines a vision that bears watching.

Nicholas Negroponte, Founder and Chairman, One Laptop per Child


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The changing basis o competition in some mainstream semiconductor markets will

punish frms that do not adapt to the new environment. EDA360 lays out a high-level

ramework, leveraging modularity and architectural innovation, or proftable adaptation

to this new wave o disruptive change.

Steven King, Founder, Innovo Strategies

Todays 1.5B connected consumers will balloon to 6B or more by 2015but those

consumers will join the global network in emerging markets, where actors like income,

literacy, and access to electrical power require a new set o breakthroughs in the

electronics industry. The EDA360 document issues a call to action or the semiconductor

industry to deliver these breakthroughs.

Yankee Groups Emily Green, author o Anywhere: How Global Connectivity is

Revolutionizing the Way We Do Business

Being able to design complete systems rom the ground up and deliver a total platorm

or system integration, applications development, and system validation represents the

uture o EDA. The EDA360 vision has the potential to allow semiconductor companies

to create powerul products that would enable consumer technology providers to deliver

a device platorm with an ecosystem o hardware, sotware, and services. That in itsel

could help tech companies be more competitive and proftable.

Tim Bajarin, President, Creative Strategies, Inc.

EDA360: ThE WAy ForWArD For ElEcTronic DEsign

capte 1: EDA idut Fu st t iteat ad Pftabt 1

capte 2: Appat-Dve stem reazat 8

capte 3: stwae-Awae sc reazat 16

capte 4: EDA360 Eabe s reazat 22

cADEncE V is ion - EDA360 - ThE WAy ForWArD For ElEcTronic DEs ign


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IntrOduCtIOn a reVOlutIOn Interrupted?

Fom mobi os o ioim vics i cs, om ii cms o

moios, om -s o wo-w visios, o wo is s b icsi

soisic ii coic vics. a wo wio vics w

icocivb js 10 o 20 s o wo b iob o. t ssms

smicoco comis s is coics voio v o o ics

cioi oi, b v so ss coss o oi w w os

o css mo comi ow miios o os 30 s o.

Wi w coiz ms sc s IBM, I, Sms, a, So s s o

is coics voio, is imo o mmb is o iovio s b

mow b coic si omio (eda). t commci eda is ovis

sow, svics, ic o (Ip) m vc smicoco

ssm si ossib. Sv cs o, eda sow ws i vo

ws s o b w comis. Ov s 30 s, commci

eda is s bo vc i cici (IC) si cbiiis o comis

o sizs, ici ss v vo som o mos civ ocs i

m.

to, ssms smicoco comis oi isiv somio

so oo v bs-ow comis wi b imc. t eda is

ow ss cossos w i so ms c i o o coi s sccss,

i bsiss. Wio c, eda wi bcom m is

oi sboim, oo soios i o sov csom obms. as

s, ow ovi b coics voio wi com o ssi.

t s? a sq ooi o coo iovio, imiis

coibio b coics is o -bi ob coom.

t isiv somio w si o is o bo eda voi w si

oos. I is o bo w mooois. I is o bo cio vicio cisis, o

mov o coic ssm v (eSl) si, o o isss v omi

iscssios bo eda o . I is bo somi mc . I bis wi si om

si cio o iio i coic ssms is, ss i w ocs

o obii. tis izio, i , os w o eda360, w visio o w

eda is c bcom.

to so, owv, w ms s bc o mom o w vi

ss coics cosm.

Chapter 1:

EDA InDustry Focus shIFts to IntEgrAtIon

AnD ProFItAbIlIty


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the neW COnSuMer eleCtrOnICS Market

eda ovis v o iv v o com-i si (Cad) ms

ii ms, b v o i o sccss ic v oosiio o

coo s. to o so, eda ovis ms s m imivs

coics comis ci, os comis iv v o i

csoms. e cosm ms s eda coo vom. Fo m,

m o ow-ow vics o b ivs s o owi si o

ow-ow IC si oos.

So w o coics cosms w? ti is vocios owi. as o

ow, mos v ms ic:

Mui,cocurrsofwaraicaios.Cosms w o m o

cs, wc movis, icios, is, s Wb o sm

mobi vic.

Commoii.Cosms w o coc o I w, im.

t w iwi, ob vics wi o b ivs. a w i

ics wi s vics o b smss, qii i v o

iio mo vic, sow, wo.

Audio,ido,3Dgrahics.t voic o o o sci. W iv i

vis-oi wo w i-soio vio ics bcomi

ssi o coics oc.

a o cos, cosmizio co wi os coom ivs cos ss.

t is sci iv mb o oi cosms ocs i

Ci Ii.

esbis comis i ssms si sc v so o s

cs b mi sm is o icm imovms v m o.

t v coi o c o i smicoco s o s, b, ow-

ow ICs, b mos v o c i m bsiss mos. a o,

sbis coics comis bi c b m-ci w s.

M o wcoms i i isis o icios, o s.

Fo m, i mobi s m, sbis comis sc s noi,

Sms, Mooo comi wi wcoms ici goo (aoi),

a (ipo), htC, rIM. I mobi isc m, comis sc s

ac/lc, no, eicsso ci w s ici hwi Zte.

a i pC m, ass ac ci w-ow s sc s d hw-pc.

aicios i oms i i isis. as i mobi ss co

ic io, vio, mi, mi o icios vib i its So.

Today, systems and semiconductor companies are undergoing a disruptive transormation

so proound that even the best-known companies will be impacted. The EDA industry now

stands at a crossroads where it also must change in order to continue as a successul,

independent business.


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as i mobi isc co ic oi, c iscio,

cio/cio. a is s s o vi v vic is.

t siic oi is mos o wcoms ocsi i iovio

iiio o s.

M o wcoms osoci w si. I iio, icsi o smicoco ovis o s oios o sow sc, sc s

iosics, ivs, oi ssm (OS), miw. W mi, i

c, icio- oms wi w sow o iv icio,

sc s mobi comi. t comss vc o icio- -

om s bcom s imo s vi s, s, mos ow-ci siico.

t wcoms ii i ocs b bii iq sow icios o

o o os oms.

t sv ocs o bii icio- oms. I iio,

is vom oc, w is vo s, OS

icios . I w- oc sc s a ipo,

w OS i, b icios ms si coom o

w. I w-i, icio-iv vom momi

b o-soc goo aoi OSw c b bi o m s o icio. W wi iscss s ocs i mo i i C 2.

FrOM CreatOrS tO IntegratOrS

Smicoco ms, mwi, v b csi Moos lw o s

cs. tis w os mb o sisos c b c o IC

obs v wo s. I s o coii miio o ow ocss os o

i omc i siz vs. howv, Moos lw is ii w

o isi vom coss. accoi o s m Smico, ssm-o-ci (SoC)

vom coss comi 32m ocss o wi oc $100 miio.

Mc o is cos wi b SoC sow vom.

Figure 1 SoC development costs have soared rom $20 million at 90nm to nearly

$100 million at 32nm. Sotware is the astest growing part o the cost. [source: IBS]

0

90nm

$MILLIONS

65nm 45nm 32nm 22nm

20

40

60

80

10 0

12 0

14 0

16 0

SoC SOFTWARE

ARCHITECTURE, DESIGN,AND VERIFICATION

IMPLEMENTATION

AND MANUFACTURING


6/32

to b ob o moiz is $100 miio ivsm, smicoco com

m o si 80 miio is. Cosii a si i mo

40 miio is o ipo b o 2009, 80 miio is is .

I s, smicoco comis wo si si o ICs, izi s

o o o wo o m wo cc vs o o s.

a vc ocss os is o o sib. ev smicoco si is

ciic ms b icb o bo m. Js o vom ojc

os ow c si si com.

a w smicoco comis wi coi o oow Moos lw si

ss, mos com, sms ICs. ts iovos si creators. Wi

wi ovi cci o i is, o o sc comis c is.

C ms b w o b sccss ow voms o wi ss vc siico.Cosm m is si s o w is o coc vics w v

v imi . I coic si is o vib o o cos wo c

o m mo b sii 80 miio is, w o s vics wi b bi

ivsi cosms w wi o miiz.

Fo, is o w. Som iovos wi msvs s integrators.

t wi i siico, SoC, ssm vs. t wi m v s o

si siico sow ic o, wi o s

m ocss os, wi ivs vi i mb sow vom.

t wi bcom icio-ocs om ovis, o ci ovis. ts

ios ms c siv obii o i iio

wio scici qi o sc.

t iio s ivovs i s o cs cio. Ios o

b b o oc Ip, v i, soc i mo civ v v bo.

t o i Ip io i om w, si wv cobii is

qi. t o vi s i oms SoCs. Ios so o

i vi mb sow. Fmo, sic -wo cosm

icios ivov bo o ii cici, ios wi o bi

vi mi-si oms.

Bo cos ios im coc bo cos, b oo

obm i i ws. Cos mos coc bo ivi siico wi

bs omc, ows ow, sms i siz. Ios w w

is oo o o sv icio s, b i bis cocs qi,

cos, im o m.

t eda is o s o sv s o cos. I s mos com

io integrators, wo i s o oos cbiiis. W, o m, oos o siico Ip vio, qi ssc, s-i iio? W is

so i siico Ip iio-? a w is bi o o s vicio o

o/ii o w/sow ics?

W o v is mm, vi oos i i. a owi mb o

ios mi somi b.

The EDA industry to date has only served the needs o creators. It has almost completely

ignored integrators, who need a dierent set o tools and capabilities.


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FrOM prOduCtIVIty tO prOFItaBIlIty

t mb o coc o co is ocivi. t s b mc iscssio

bo owi ocivi i IC si s ocss os si comi

ows. Sim , ocivi is ic bw siico cci

ii o ic bw w co b, w c is.

Cosi ocivi is om sov obm, i is o eda ovis

c so coi o ss. eciv ocivi mm bis ioviv

ii cbiiis o si, vicio, immio.

a design v, ocivi wi b c b movi o i v o bscio

b icsi si s. a verication v, ocivi wi b imov wi

mic-iv oc comssi simio, om vicio, mio.

a physical implementation v, eda coo ms wi owi ii

si comi vc os, so mci-w, mi ii,

o co-si.

Figure 2 Closing the productivity gap requires an integrated approach to design,

verication, and implementation.

dsi, vicio, immio ms b cos i. a oo o s

ss om i isoio wi imi bc mo ii ms.

Wi eda commi c so coi o imov ocivi, w

io mos cs bo is obii. t is owi obii i

coics is s b iscss. I is bw bsiss os

si cos, smicoco i cos, im o m (o cos). I so,

i is ic bw w o c m w o c m mo o.

to cos obii , comis ms coo w/sow vom

coss ow coss o ci, mci, s. Bo cooi

coss, ios ms ics v. tis c b o b mi i im-o-m

DESIGN

VERIFYIMPLEMENT

PRODUCTIVITY

MANAGEMENT


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CREATE

INTEGRATEOPTIMIZE

PROFITABILITY

MANAGEMENT

wiows, b sii i oc o i m i im,

voii ovsoo ovis mo cosms wii o o.

t eda is ms cos obii . Cosi ivovs

ss:

Cra.Wv o wv w o sow Ip is vob i o

o i si ms b c wi iio i mi. I ms com wi i

ocmio, b vi, b cob o icio.

Igra. dsi ms ms b b o i i Ip io oms,

vi com SoC o om, ici ics bw o ii

bocs s w s w sow.

Oimi. dsi ms ms b b o c i c coss wi si

qi, owi ow cosmio, immi s coss o omio.

t ms c mb o -s iios.

Figure 3 Silicon IP integration and die/package optimization help close the protability gap.

Fi, coboiv cossm ici smicoco si comis, Ip ovis,

svic ovis, ois, eda vos, ssmb/ci oss is , o

wi bm o o, ss-bs soios. Wio sc cossm,

coics is wi cos bc io o , vic-i comis.

While the EDA community can and should continue to improve productivity, what theintegrator most cares about is protability. There is a growing protability gap in

the electronics industry that has rarely been discussed.


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TOwardS The nexT GeneraTIOn O eda

eda360 povis p, 360-g visio o eda tt svs itgtos s ll

s ctos. eda360 lps clos t poftbility gp toug itgtio-y IP ctio,

IP itgtio, optimiztio. Giv tt mb sot c tk up l t cost

o SoC vlopmt, eda360 lso suppots /sot itgtio vifctio.

It tus ps t scop o eda ll byo its oigil bouis.

wil titiol eda ocuss o giig tms oly, eda360 ill povi cpbilitis

o pojct busiss mgmt. It ill c coss customs ti globl

ogiztiogis, pojct mgs, copot lsto bl poftbility

comptitivss i ts cllgig tims.

wit eda360, uss stt it ustig o t sot pplictios tt ill

u o giv /sot pltom, f systm quimts, t ok

ti y o to sot IP ctio itgtio. eda360 suppots

t impott cpbilitis:

SystemRealization is t vlopmt o complt /sot pltom

tt ill povi ll cssy suppot o -us pplictios. T pltom iclus

o o mo SoCs vlop toug SoC rliztio, s mb sot

istuctu tt typiclly iclus OS, mil, c pplictios.

Systm rliztio is iv by t pplictios tt ill u o t complt systm.

To b succssul, it quis tpis-lvl pogm mgmt.

SoCRealization is t compltio o iiviul SoC (o lttiv pckgig

coic, suc s 3d IC). alog it t itgtio o silico IP vlop toug

Silico rliztio, SoC rliztio iclus b-mtl sot suc s ivs

igostics. I t eda360 visio, Op Itgtio Pltom cilitts IP

itgtio ito SoCs.

SiliconRealization psts vytig it tks to gt sig ito silico. T

sult coul b log o igitl IP block o SoC, IP subsystm, o complt

IC itout mb sot. Silico rliztio icsigly ivolvs t ctio

itgtio o lg compl igitl, log, mi-sigl IP blocks. It gos ll

byo covtiol mi-sigl sigs tt itgt smll log blocks

ito igitl SoC.

IP ctio, us, soucig t t co o t eda360 visio. IP itgtio tks

plc uig ll t stps list bov, it sot IP comig ito ply uig SoC

rliztio Systm rliztio. Itgtio is t is om t top

mts t is possibl om t bottom.

With EDA360, users start with an understanding o the sotware applications that will run

on a given hardware/sotware platorm, defne system requirements, and then work their

way down to hardware and sotware IP creation and integration.


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Chapter 2:

ApplICAtIOn-DRIvenSySteMReAlIzAtIOn

SYSTEM REALIZATION

SoC REALIZATION

SILICONREALIZATION

Add Embedded Software

Add Application Software

Add Mechanical (Board, etc.)

Add Bare-Metal Software

Add Packaging

IP INTEGRATION IP Creation

IP Reuse

IP Sourcing

Figure 4 EDA360 extends down rom System Realization to SoC and Silicon Realization.

COnCluSIOneda360 wi cos obii o cio, iio, oimizio,

i wi ovi b so o bo cos ios. as sc, i wi

s coic o vib, ioi coics is wi oss o

s. t is wi o o c w w wo i wi ovi

soios w o cosvio, viom, c, cio,

soio.

to i mo isi io eda360 wo i wi s, i is bs o s wi

iscssio o Ssm rizio. tos mos commci sccss ssms

icio-iv, wic ms i si s o b o i co. tis qis

om wi ow -s icios o m i si i omis,

osiiv imci bo obii ii ocivi.

ecoics ocs o bo icios. as sc, w si w

oc o ssms si i wic comis bi ojcs wi si

o s o icios wi o ssm. t, s

si o vo oimiz om o so icios. I iio

o w, is om ics b m (w-)

oi ssm s o sow.

tiio, i cos, mos ssms vo om boom , si wi

w. t OS iss o is vo wi v ic si o

i w, icios wi wii imiios o

-mi w sow isc cbiiis.


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t s b mc i coic si wo bo w ssm comiss.

I is iscssio, iz ssm is w/sow om o

icio(s). Ssm rizio ms com vs o sow sc, om

b-m sow OS o ibis icios.

t platorm coc is c o Ssm rizio. I smicoco is,

ios bi cob oms cosc om ibis o comos sc

s ic o bocs o m si ms o cosmizioi-

obii, s im o m, ow cos. I SoC rizio s scib i C

3, s Ip bocs o js iio siico Ip. t o oimiz Ip sc

om b-m sow o sic ows visibii io coo o w om OS icio.

a w-ow om m i smicoco is is nxp ni,

wic is s o coc mimi vics. I iio o ommb SoCs

comio ICs, ni coms wi c sis, ssm sow, vom

oos. no ss imo is nxps si om, wic bis cossm o

ni soios.

a dISJOInted apprOaCh tO SySteM deVelOpMent

t iio oc o ssm vom is is. I mos css, w

si is iscoc om sow isc vom. to c w,

ssm SoC si ms c o b siico Ip. tis m b Ip wi

sic os, o so Ip c b cov o -v sio wi oic ssis oo. ao mo fib Ip, so Ip is ic

is-s v (rtl), iv ow v o bscio ssms

mico-cic. dsis coi wi immio vicio i

w is si siico Ip iio is com.

Wi oi ssm is -sc, icio vom is

bsc om w. I bsc o vi oo o moc-

oois o wi s b sow vosicios co b com

i w is sic vib. I bcoms zi o o so im

sc, ci o b omms wi i o o coo o, o visibii io,

w socs. hw/sow iio bi occs i

si cc, csi sc s, cos ovs, qi obms.

t -s icios vo, mos i b i wo s i

miii wi i w o sow. aicios ms coom o imiios imos b w o sow. uss i is ov-si, i

om wi obb so ow o icio qims, imii

civi o icios vos.

Electronics products today are all about the applications. As such, we are seeing a new

approach to systems design in which companies begin projects with an understanding o

the needs o the applications that will run on the end system.


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aicio, sow, w vom o b i ms si

i ow oos Ip. tms commic s oc i is

ois. t s is csm bw c o ssicios,

sow, w.

Figure 1 In traditional system development, hardware design comes rst and sotware

is appended later.

asi om im-o-m s, is i obm wi is is

oc. a ics oi ivov mo o o omis is

bov v ic o sov. I icio css, is obm i icio

is, isc sow, o w? I isc sow om

ics mmo o, is b i sow o i w is?

M si ms c oos o ow o c ow sc obms qic.

Is, is o i--o o wi o o iio somims o

soio.

I w is si s, sow is , i is ic o oimiz ssm v. to, o m, m ssms ms b oimiz o ow cosmio.

avc eda si fows so ow oimizio ciqs sc s ow so

o mi vo vs. B i sow is o oimiz o v o sc

s, wo b v civ. Fo civ ow-ow oimizio, sow

w so b cosi coc.

to so o icios cosms v com o c, w ms

w-s im o is mov ow icio-iv Ssm

rizio oc.

MOVIng tOWard applICatIOn-drIVen deSIgn

Wi icio-iv Ssm rizio, o o s b bii wo

s b visioi icios o w o . t o w omo wi ssm sow, ici ivs, OS, miw. how o o obi

w/sow om s i o o icio? as o o,

wo i ocs o icio-iv siw- w-

i.

Open Source, Microsoft Studio, e.g.

Hardware

Software

Applications

SYSTEM DOMAIN DESIGN ENVIRONMENT

Silicon IP, EDA tools

OS, embedded software tools


13/32

I w- oc, w is -si i i wi

ssm sow bow icio v. a sow vom i (Sdk) ovis

si viw o ssm, o wi vi vos o c icios

civ o om. t a ipo ss is oc.

Wi w- mooo, icio vos v sb, icbom o wic o bi vi o icios. t c vo icios

so sb icb, bi s m qic, wio sci ow-

o i sow w. Wi s mos vs,

icios ms b wi i coomc wi oms cbiiis. t w

co b co o c. Fom w soi, is cos ssm.

I w-i oc, o i w is o sci.

tis is oc goo s wi aoi, sow sc o mobi vics

ics oi ssm, miw, icios. aoi is ,

o-soc oi coms wi Sdk ovis oos icio

ommi ics (apIs) o voi icios. aoi ovis

o ssm.

Wi w-i oc o icio-iv si, o c soc o

bi om oimiz o o o icioo oo mc cbii, o oo

i, b js i. I cos, w- om co b co o

c, i is i o b oimiz o icio o w o .

Figure 2 Hardware-independent applications development makes it possible to create the

right hardware or a given application.

tis os o m o wo bi o soc csom w o v icio.

r, wi cob w/sow om, sow icio

c co w i w sis icio. Sos o v wbicio ics vio. t icio wi w o o cocio bw

vio ics iv mmo s wi s ossib, s cosi ow

o cios o o wb s. l o, w is im o o som

comio, w wi b co i. t icio,

Cpu, is ioiizi socs.

HARDWARE-

INDEPENDENT

e.g. Android

circa 2008

Hardware

Hardware-independentApplication Platform

ApplicationCustomization

HARDWARE-DEFINED

e.g. iPhone

circa 2006

Operating Systemand Hardware

Application

DISAGGREGATED

Hardware

Operating System

Application


14/32

aicio-iv Ssm rizio ois o 180- o om

is, w-s vom mo. Is o ssm cbiiis ivi

icios, icios ivi ssm qims. B voi

soio is js i o ov-si, ios c sis i im

cocscos, im o m, qi cos obii .

hOW eda needS tO reSpOnd

to so icio-iv Ssm rizio, eda360 ms ovi w

cbiiis. Fiv sc cbiiis s oows:

earsofwardom

Aicaio-drissmigraio

Aicaio-drissmricaio

Drirdomkis

Aicaiodomkis

Is imo o o o o si vo c ovi soios

o w/sow cio, iio, vicio. t is sci

Ssm rizio v, w bo mb sow w

is qi. ecossm coboio wi b ssi o sccss, s wi o

ss ovi coic o csoms. eda vos wi o wi

mb sow comis, Ip ovis, csoms o ovi m o

cbiiis scib bow.

early SOFtWare deVelOpMent

Fom icios sciv, o sim w o o icios i

s soo s ossib o w/sow om ms s qims. yo

ci o w o, sow, si ocss i wic icio vom is

s i w is com. I, sow vom wi s s soo

s ocssos ii s o i bo ov cic.

Vi oos o sow vos c b sow si s

ocsso mos scio-v mos o i w, w bo

w is c bi. tis cbii cs im-o-m cs vom

coss. W imi ccc is qi, owv, w mio oos .

emos c imi- bs vi oo wo miss,

mio is ow vib wi mic ow sis.

Fi, b sow vom so is o mi-co SoCs wi mi

ocssos. tis is sci wi oos mi-co SoCs v i

s o ocssos i oi ssms. to, vos o o o m

iioi i--o wo. B soios qi, wi qi

coboiv o ics eda vos, mb sow ovis,

cmic isi sc commiis.

To support the range o applications consumers have come to expect, we must turn

the hardware-rst paradigm on its head and move toward an application-driven

System Realization approach.


15/32

applICatIOn-drIVen SySteM IntegratIOn

SoCs ssmb om ibis o o, ii, mi-si Ip bocs. ts Ip

bocs somims c i b mo o cs om i-

comis o cqi om o si os. pi Ip o civ

ci is siic c is o w sv b eda is o.

as s, som comis o Ip iio c cos mo wic s mc

s i coss o b Ip i s c.

Ssm rizio c b viw s Ip iio c, o is v o

bscio Ip mi b i SoC, oi ssm, o c ic-

io. hw/sow iio is i ssm v, sci w w

is si s sow is wi imi coo o visibii io

w. t w-sow ic is o o iis cs o bs o occ,

w o, is v ic o mi w cm om w,

mw, sow, o icio.

a icio-iv oc ss w/sow iio cs. h,

o c s sow vom s soo s w bsic cisios (sc s ocsso)

v b m, bsc w qims om sow. W-i

ss m is s. Ci-i oos o i,

simios o ow, i siz, i, cos ow vib. Ov im, ssm

i oos cosi bo sow w wi m.

as iio ocs, om ii c o (eCO) cbii is v v o bscio. Cs ivib, co is

si cc. I so o b css o ssm o -ssiz i

Ip boc bcs o o sm c. t i is o c w/sow

om, o c sci om.

aom eCO oos vib o. ts oos om vi cs, ow

icm si cs miimiz isio. tis cbii is si ocs o

w, b s c b o i-v ssis.

applICatIOn-drIVen hardWare VerIFICatIOn

hw si ms ow vicio cosms mos o w vo-

m im cos. Sow vicio bi q im-cosmi.

a Ssm rizio v, ios ms vi i ssm ms qims cios s c.

Ssm rizio qis icic vicio. t ms o so b b o

vi Ip oc, cc i o, o vi i-boc ics v i

bscio. B im o o Ssm rizio, o ics bw mjo

ssm comos so mi. I wo, o, o o -vicio

No single vendor can provide all the solutions that are needed or hardware/sotware

creation, integration, and verication. That is especially true at the System Realization

level, where both embedded sotware and hardware expertise are required. Ecosystem

collaboration will be essential or success.


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occs, vicio coss o/ii o w/sow bois is m

com. to m is mo comic, ssm-v vicio ms ms

m o s sqcs o co cs bs.

t mic-iv vicio oc voc b Cc ovis v

o w vos o. I ows si ms o s wi cb vic-

io c cov mics sow ow com vicio ocss is.

Bii is coc io mb sow wo, w omiz vicio

mooo is ci, wo b Ssm rizio. Coboio bw

IBM Cc s sow si vicio c coo c bo

w sow vicio.

Mi-si vicio ssm SoC vs is m ci. ao

simos oo sow o ssm-v vicio, v wi bvio moi

ciqs, ic bw o ii cici is v com. B ii

simoswic os o mi s o simosc, i c,

sim o sis i v o coscs ow vib i

s o moi s.

Wi ocs o icios, o vicio cs. I is o o o

o js sims oo wvoms o soc co. to vi vio icio

Ssm rizio v, o w o s vio. to vi msic icio,

o w o msic. I o wos, o w o vi icios i co

o ssm. I is ossib o oios o iv icios o si vioos o mio oos.

drIVer deVelOpMent kItS

to, sow iv vom o csom w is m o. I o s

wi icio c o i w, voi css ivs

c b bi obsc. a wi m w oios o coios, o

m wi mb o i ivs o sm w om.

a iv vom i c . Imi, o m, li iv vom

viom ics ms m i s o wi ivs o mb

li, sowi sow vos ow o sci os is.

Part o EDA360 is providing new tools that oer a dashboard to help companies

manage system development projects, and provide metrics that make sense in hardware

and sotware engineering environments.


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applICatIOn deVelOpMent kItS

a ovis ci sow vom i o icio vos. t i

bscs w is bo i w sow, ovii o w

vos o ow o m icios wo o om. t wbc is

w co b oimiz o csomiz. aoi Sdks s aoi, b

obvios o w goo os ovi.

t is c o icio-iv Sdks o bs o w o

sow oms, b si s bsic cios qi o ic

css o icios. Fo m, i o mobi icios wo s c

i oi, s w s qims o o o io qc (rF) so.

ManagIng the SySteM realIZatIOn prOCeSS

t vom viom bs icio-scic Ssm rizio is is

ssm s ooi mm ic. Mc i is sow

ovi o bsisss, is-v mm is o cos, sc,

so soc mm scs o ssms vom. ts oos o

m oic-iss ms s w s Siico rizio ojcs c

coss mi comis.

eis soc i (erp) oos ovi som o s cbiiis, b

i v ccss o i o si o cs

qims o coic ssm vom. a oo w o ssm iio

co o o sc o ssm iio. a oo wi o si o

vicio co o c moio vicio ocss.

ts, o eda360 is ovii w oos o sbo o comis

m ssm vom ojcs, ovi mics m ss i w

sow ii vioms. t mic-iv vicio cbii vib

ow ois w o w s o b o. to, si vicio ms c

c cb vicio iis ojc mics, cs simio

is, cs cov mics. t c viw os cs wi m m o cos vicio ocss, mi w vicio is

o. as s, vicio socs s civ ov coss c,

i cos obii .

COnCluSIOn

t iio oc i smicoco is is o bi w,

sow (i w v o!) sombo s wo bo icios

i o -bi w. B i comiiv cosm viom w

iiio coms om s civ icios, obii is o

i, is covio oc is i o o sm. Wi icio-iv

Ssm rizio oc, vos c s b visioi icio. t

c si ssm v s s ossib, wo ow o sow,

bi o b w.

t icio-iv oc wi cos obii b ssi cos,

im o m, qi. B is com w w o ooi si, i

cs w ms o ssm ios eda ovis. eda360 is i o

m os ms.


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Wi Ssm rizio ocs com w/sow om oicios om, SoC rizio ss sccss vom o si

SoC o m ssm s. tic, SoCs cosi o b o w siico

is com. I eda360 viw, owv, SoC rizio is o com wio

sow vic ivs o c w sbssm. W biv s ivs so

b vo wi SoC c o s o com

w viw o ow siico Ip so b ovi.

Is o ii o Ip s iso bocs, w oos Ip sc ics

b-m sow s w s w Ip. B-m sow s o vi

bow OS , mos omi o b-m sow is vic

ivs. t Ip sc ic bow so ics vicio Ip (VIp) vis Ip

cioi iio. t sc m ic mcos wi os

o wi ssizb Ip is-s v o scio-v moi

(tlM) v. I so ics si cosis.

Figure 1 An IP stack includes synthesizable RTL or TLM IP, verication IP, and hard macros,

in addition to driver sotware and design constraints.

div sow ows OS icio o m w socs. as sc,

coic ssms ms v icoo vic ivs. So w b m wi

siico Ip ic m s o SoC rizio?

Cosi ow ivs ic vo. I covio SoC si mooo,

w is bi s ivs wi , s b somo w o

is ( s iii cbiiis) o w. tis vs wo b

coics. O is siv, csom iv vom o b somo wo obb

s i w owo i is w so, i o o OS ow.t o coic is o cs ic iv wi v o si

o ow iv o w so o OS, wo v o

o cbiiis o o w.

VIP

HARD

MACRO

HARD

MACRO

HARD

MACRO

DRIVER

DESIGNINTENT

POWER,AREA,TIMING

TLM DIGITAL

RTL DIGITAL

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Chapter 3:

soFtwArE-AwArE soCReAlIzAtIOn


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I i cs, icios iscoc om i w ssm.

t s is w i bw icio w. yo c v

bi ssm wi mo o ss wob i wi obb b sb-oim, ov-

si o -si, , obb oo siv o i obii.

I ivs o Ip sc, owv, wi s o iw cbiiis o oi ssm. tis ms i si o OS o ic

coo o co w socs o m s o icio. Fo m,

vio icio c ic immi c o bwi i s o o

s wb s. I c co w i o som comio.

tis cbii is imiis i ivs o com w.

I is so imo o ic si cosis wi Ip sc. t mos commo

cosis os o ow, imi, . ts cosis com om vios

socs, ici Commo pow Fom (CpF) s o ow, imi scis o oic

ssis, sic o cosis o o bocs. Cosis ssio

o si i, o so bvo v i si cc.

to sv si i, cosis ms b com oo si,

vicio, immio ss css o cos ocivi .

So w ic cosis wi Ip sc? Bcs wio oo si

o si cosis, iio o Ip io SoC wi b ic o-o.

Bs mo i o i ics bw Ip sbssms, ov ssm

cioi m b comomis o , vicio wi b mo cos. a w-sci, oo s o si cosis is s imo sc o iio-

Ip. Cosis so b ovi o s o sc, ici o

mcos, ssizb ii Ip, iv sow.

a BrOader deFInItIOn OF SoCS

Fom siico soi, SoC is cob o ommb IC ics

s o ocsso, som csom oic, mmo coo. a icsi mb o

SoCs mi-co ICs v mi ocssos o sm o i s, sc

s Cpus, gpus, dSps, sciiz w ccos. SoCs m so v o-ci

mmo, is, ooco ics. a o s comos oiz io

sbssms Cpu sbssm, mmo sbssm, I/O sbssm, so o.

giv icsi comi o os SoCs, i is vi o s ci commic-io mo s sbssms. I commicio cic is iq, coc-

i sbssms o wi b i immio s. ts i is ssi o

com commicio wo cic s o SoC rizio.

a w o-ci commicio oc c wo o ci (noC) is omisi

ics fibii o mi-co SoCs.

SoC Realization is not complete without sotware device drivers or each hardware

subsystem. We believe these drivers should be developed with the SoC rather than tacked

on laterand that leads to a completely new view o how silicon IP should be provided.


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Figure 2 SoCs are organized into subsystems. One o the subsystems provides a

communications abric or the others.

So wv s covio iio o SoCs. Wi sow- SoC

rizio, owv, ivs ovi wi c sbssm. t ivs ow

OS o ic v o sciiz w s i c sbssm,

ici o-ci commicios bic.

SoC rizio is mos ci w mi Ip scs ssmb io Ip sbssms.

ts, i , so mjo w sbssms, sc s I/Os, Cpus, o mmo.

Ip ms so b oimiz o iio. dsi cosis imo o

oimizio.

InSIde the Ip StaCk

ls cos oo Ip sc. Covio, mos ii siico Ip ics

coo sic (phy). Fo ss-bs Ip, sc s pCI ess o

uSB, coo is s so o ssizb Ip, wi phy is ic ,

mi ssis o v b com. Cpu Ip, owv, is s

i ssizb.

So Ip is ic bi is-s v o. ts owi mov o

i v o bscio, scio-v moi, wic wi ow mc s si

vicio coic o mico-cics. tscio-v mos c so b

s o bi vi oos o sow vicio. Wi c vibii

o SsmC i-v ssis wi i qi o ss, css oos o

miio o tlM i c.B tlM-bs ii Ip is js o o so. Vicio Ip s bcom icsi

imo so b o Ip sc. VIp ovis com sbcs

o vi Ip coio iio. I iio o sbcs, VIp is vib

ow wi ooco comic mm, so o ssios, scio-bs

ccio, s o mio.

PROCESSOR SUBSYSTEM

On-ChipData Memory

EMBEDDEDCPU

Fabric

On-Chip

Instruction Memory

HIGH-SPEED PERIPHERAL SUBSYSTEM

PHY

PCIe G1/G2 Other IP

PHY

AH B

APB

AXI

BRIDGE

USB3

MEMORY SUBSYSTEM

FlashController

PHY

DDR/LPDDRController

DDR PHY

LOW-SPEED PERIPHERAL SUBSYSTEM

UART I2C INTC

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BRIDGE


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Sic SoCs mi-si, Ip sc wi i ic som o

mcos. Ci-v, mi-si vicio is o o os cs c b SoC

ssm sis o. O w vib soio ms i ossib o sim

o sis isi ii simio viom, wi i v o

mic-iv oc vib o ii vicio.Ws w bo Ip sc iscss , owv, is icsio o vic

ivs si cosis. W Ip co ovis ivs, is o o

css o somo wi i o o w ow o bi m c.

W Ip ovi ics cosis, SoC io c ssmb Ip scs

sbssms wi coc.

Wi is w Ip oc, os o cic imm SoC i?

t sw is mic s is o i w coc c O

Iio pom.

Open IntegratIOn platFOrM

SoC iio ivovs ss:

Analyze the architecture. Bs o icio qims, ssm sis

om w-i ss (bsiss cic), vo ov o SoC,

cosi ms sc s ocssos, I/Os, mmo. t so

b-m sow ows OS o coo w. Ci i

oos c vib o wi som o s ss b owi i, w-i

ss o ow, , cos.

Develop or source integration-optimized IP. W i coms om i socs

o i is, sis ms b b o oc Ip s bs o icio om

m socs vib. tis qis co o ib o Ip ows cic

cos comisos, s w s oos mi w-i sis o ow, omc,

cos. I som css, sis wi ci o c iio-oimiz Ip. Som o

qims o iio oimizio ic:

Fucioaiisw-ddaddocumd

Sourc,shsis,adimmaioackagsarroiddforigraio

Siico-aidadIpisaaiawihcharacriaiodaa

Ipmsdocumdquaiguidis

Ipocksararamrid

Ipsackscomwihdsigcosrais

tsaformforIpcomswihacomricaioiromfor

hardwaraddrirs

Dirasicudacssarscris,guidis,chckiss,ad

documaio

When the IP creator provides the drivers, its no longer necessary or someone with little

or no hardware knowledge to build them ater the act.


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Integrate IP to realize the SoC. Wi iivi bocs o Ip, iio is i

s. W Ip is oiz io -vi, iio-oimiz sbssms, i bcoms

mc si. dsis o b b o s o sbssms. t design, veriy,

implementss o cos ocivi scib i C 1

, vovi o m s o w Ip iio im. pocivicois o b imo o SoC rizio ocss so svs o cos

obii .

a O Iio pom ovis mwo wii wic o c o s

ss. I is iv b Iio dsi eviom is oos o Ide

(I dvom eviom) s b sow vos. I ovis

comsiv s o cbiiis o vo os SoCs, mimizi bo ocivi

obii. I is bs o o ss i Oaccss bs, O

Vicio Mooo (OVM), Ip-xaCt om o Ip sciios, SsmC

tlM 2.0 moi s.

Woi om is SoC-Ide (Iio dsi eviom), sis wi i

csom-scic icio-scic qims, bi i Ip sbssms om

i o socs. t m m s o i- csomizio svics o

ovi is o so ios o imo m, o bi i som ois o sov qsios o mi-si sbssms. Ios c si,

vi, imm iio Ip is , ssmb vi

com SoC, ovii iomio css o bicio o o.

t SoC-Ide ovis sbo o i si, vicio, imm-

io oos. I s s v o isi cbiiis sc s mic-iv vicio,

ow-ow si, mi-si immio vicio, w/sow

iio. ts cbiiis wi coi o vov o m s o SoC ios.

Figure 3 An Open Integration Platorm makes it possible to produce an integrated

SoC rom IP subsystems.

FOUNDRY

THIRD-PARTYSERVICES

INTEGRATIONSERVICES

THIRD-PARTY IP

INTEGRATIONOPTIMIZED IP

(Software and Subsystems)

INTEGRATION DESIGN ENVIRONMENT

DESIGN

VERIFYIMPLEMENT

CUSTOMER EXPERTISE


23/32

SoC rizio s scib cs o sis o c iio-oimiz Ip

w , o i bo i c soc Ip, o vi

oimiz SoC o m ssm qims. ts, ss cos obii

create, integrate, optimize cci o SoC rizio s w.

COnCluSIOn

t eda360 viw o SoC rizio cs o iio o SoCs ics

b-m sow, o wi mo comsiv w o ooi Ip s

scom sic ooco (coo) o ivs o wi

ssoci vicio Ip si cosis. B ici iv sow, ciic

w i is i, owi icios o wo o OS o c o

cis w socs i s.

to so is visio o SoC rizio, w coo is qi. O s is

o m i si o Ip cos o bi ivs. ao s is o cii oo,

mic-iv Ip vicio o oi w -vicio o Ip is css. a

eda360 wi o ovi O Iio pom, wi is bii o w-i

sis o mi bs ossib cic iio, vo iii SoCcic, qic i vi Ip io vi SoCs.

t o Ip wv scib c o com bo o coboiv

cossm. eda comis, mb sow OS vos, Ip ovis, ois,

-s comis ms wo o o iio o Ip o

b-m sow com sbssms.

t oc oi i is c wi o oo o ob, icio-iv

Ssm rizio. Is o si im mo o v sciis vo

csom ivs, o cci imiios o ic iv, SoC ios wi v

iv sow ss cbiiis o i w. Is o fi

bi i io obms wi iio, SoC vos wi oow cosi-

iv iio mooo. t oc scib s ios m

os o cos, im-o-m, qi, o cosi obii .

With individual blocks o IP, integration is a daunting task. When IP is organized into

pre-veried, integration-optimized subsystems, it becomes much easier.


24/32

eda s ws b coc wi Siico rizio. I c, s b i ocs o eda is sic is icio. Fom eda360 oi o viw, Siico

rizio is o o si oi o ssm vom i mis s

ssi s v, is bcomi mc mo ci.

Siico rizio ss vi i s o si io siico, o

si, vicio, immio. I sos so o sow vom

iio, wic ss com wi SoC rizio Ssm rizio.

t o o Siico rizio m b o, ii, o mi-si Ip boc s

i io SoC; IC os o qi mb sow vom;

o SoC o sow iio.

as coics is movs ows icio-iv Ssm rizio,

cocs is bo owi obii , sco comi o Siico

rizio cs wi msoom. Comi wi ow v mo com wi

mov o vc ocss os sc s 32m 22m. Bo eda is iscsoms ms s so o cs.

Sic ici o -wo qis o cici, Siico rizio ws

ivovs combiio o o ii Ip. B Siico rizio os bo

iio viw o mi-si si, wic ic ivovs imoio o w

o mcos io ii SoC. Siico rizio ivovs cio i-

io o m , com o mi-si bocsici bocs

w i cis i vios ocss iosio SoCs so bo s

o cioi. ts s som o/mi-si bocs m b ommb o

cob, s is cs wi sow- io.

Figure 1 Many SoCs today integrate large digital, analog, and mixed-signal blocks, including

audio, video, and wireless interaces that may have previously been entire chips.

Chapter 4:

eDA360enAbleSSIlICOnReAlIzAtIOn

RF Audio

TV

FM

DSP

Modem

Video/camera

interface

LCDdriver

IO/Keypad

USB

SIMPLL

Bluetooth

Wi-Fiinterface

PMU

Communi-cation

processor

Imageprocessor

Applicationprocessor

Externalmemory

interface

S1 S2 S3 S4

Memory


25/32

Siico rizio so ivovs cio o -csom ii, o, rF Ip bocs

ICs. Cocs bo ocivi obii js s c o csom sis

s i ii wo s ss si omio. poss is

i csom IC si s w, som is occi. O m is vo-

m o cosi-iv o si fows.Wi Ssm rizio SoC rizio imi ss o ios, bo

cos ios om Siico rizio. ts, eda360 ms ss s

o cos b cosi ocivi , so ss s o ios b

cosi obii . t m i is o o om coc o siico s

qic s ossib s c s ossib, wi ii i qi

cosms v com o ow m.

three COnCeptS BehInd SIlICOn realIZatIOn

t commo ms bi mos o ocs o cos

ocivi obii s i Siico rizio:

Merge top-down design and bottom-up design. t iio si oc is

boom sis s wi siico sow ic-

ios . t mi icio-iv oc ss wi icio, s

ssm, bscs w sow qims om ssm

iio. B is o o-ow; iomio ms fow w om siico v

s w. I is ssi o s ow, omc, cos ssm v,

is c o i iomio bo siico si, ci, mci is

m vib i vs o bscio.

Raise the level o abstraction. t m ws o wo i, ic v o

bscio. t c mov b ii si vicio ms o scio-v

moi ss o oc, b os. Fo m, o sis

si bvio moi s sc s Vio-aMS, c ow sim o

cicis i ii viom si w . howv is o, i

vs o bscio boos ocivi, ss im-o-m, ow coss.

Apply unifed design intent. W o -csom o ii si, si,

com, co sio o si i wi voi os oo

Siico rizio fow. tis i si i cs scs o si

ici cio, cosis, izioo s vi is woi ows

commo o commo si. Woi om is commo si i

cs iss o scicio misss -sis, ss cs c

imm coc cosis oo si ocss.

Silicon Realization involves the creation and integration o extremely large, complex

analog and mixed-signal blocksincluding blocks that were entire chips in previous process

generationsinto SoCs that support broad ranges o unctionality.


26/32

ClOSIng the prOduCtIVIty gap In SIlICOn realIZatIOn

Cosi ocivi qis ioviv ii cbiiis i si,

vicio, immio. eda360 s o iv oowi cbiiis o

cos ocivi .

deSIgn FOr prOduCtIVIty

Raise the abstraction level early in the design process. Fo bo o ii

si, i is css o c si i s ic i-v om s ossib, s

s ossib. t, oos c ovi o omio o sbsq

si civi. tis ows fibii i i si w ciic si

immio cisios m. Wi tlM, o m, ii sis o

oc io mico-cic, om SsmC i-v ssis ms i

s o o i coics si qims. O o si,

si Vio-aMS o w mos s sis c si i

cc vicio cc o Ip iio.

Tackle multiple objectives simultaneously. tiio, is oc o m

ssims o ow si wi wo, o ocs o js sm mb o

si cosis. a b oc is o ovi -o s

o so iom cisios o bo bsiss cic vs. pomc, ow,

i, mcbii, cos ms b cosi coc i isoio.

ei o os ci i oos, eda360 oos wi ow i, coc

w-i sis b b i vs o bscio.

Use a single source o design intent. t is o oss o i s o s osiico si is o o os woi o s. Wi si, vi

soc o si i, is o oss o i, o is o sio.

I ii si, o soc c si i mb o i omssc s

tlM o is s v Ip Commo pow Fom mos o ci ow

i. I vc mi-si si ssm, commo s o o ii

cosis c si s miis i oo Siico rizio.

VerIFy FOr prOduCtIVIty

Holistic verifcationuse the best tool or the job. t m i

ciqs o ii vicio, ici simio, om vicio, mio.

aocs o o simio om siso-v SpICe simio o o

bvio moi wi Vio-aMS . Woi wi si o ovii si i, iizi vicio , eda oos ms coos

bs oc o iv s o vicio ocss is bc o

vicio . t s is oisic oc o vicio si mos ociv

mos o c s.

Whether or ull-custom or digital design, a single, complete, and coherent representation

o design intent will help avoid errors throughout the Silicon Realization fow.


27/32

Apply metric-driven, predictable verifcation. a mo IC si c coi mo

oi ss mb o oms i ivs (o 1080), so si v

ossib combiio is o sib. Ws is ii vicio ows

ws b s w s. a mic-iv, cb vicio ms

i ossib o moio c si o cov mics mi w sis o b vi. t sm so so sv mi-si vicio o o

ii ics.

Use the right verifcation abstraction. abscio is o o imo o si

i is so ciic o vicio. W omi vicio w o s mos

ssiv sciio vib, ovi js i mo o i o job

o. Fo m, si im sbc is mo wo b v ici

w o om c moi i wo swic. liwis, si SpICe bscio

o mi-si boc i omc si wo o siic s i

vicio cc.

IMpleMent FOr prOduCtIVIty

Use single-pass design. avoii iios qis i s im oc

b b -ow o imo si io c s o si

immio. as iv si m is imm, o iomio s o

b o si s o voi oi obms sv ciic ssmios

om vios ss. ev so, cs ivib. Wi om ii

c o (eCO) cbii i o om vicio, si ocss c coi

smoo w c occs o b is .

Understand realization. I is imo o ow ow si wi b imm.

I si is o o ii Ip boc, sis so ow w s o SoCs i

mi sv w o Ip i mi b ici wi. I si wi b c-

i sc-i (3d IC) coio, is wi ifc m coics. I c s

o si ocss, bo i immio ms b m vib

oi vs o bscio o m civ si os.

Intelligently partition large digital blocks. a vc siico ocss os sc

s 32/28m, si ii Ip boc m coi miios o s. W i

o gi g, gi hz SoC si. tis ss i m cs, ici

com mci s, si siz osio, si o s, i m,

vibii, m os. l, ii si ms so o v o b ici

iio io sm ics o oo sicios o imiios i si is.

eda360 oos wi cci sco, owi sis o wo i mo

sio, o voi m o obscs o ov com mismc

sic oic icis i si. tis bcoms sci imo s i

vs o bscio ow is o c siic oios o si.

For both analog and digital design, it is necessary to capture the design in as rich and

high-level a orm as possible, as early as possible. Then, tools can provide a greater degree

o automation o subsequent design activity.


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ClOSIng the prOFItaBIlIty gap In SIlICOn realIZatIOn

to cos obii o ios, eda360 ms so cio, iio,

oimizio. tis ss somw i s o cs soios

com o os o ocivi .

Create FOr prOFItaBIlIty

Use high levels o abstraction. t sm sciio ws iv i o cos,

b ocs o ios is i i. h, coc is owi i-

os o ocs o v b imii s m css ss s

ossib ci bswo. Ci o soci Ip tlM v is o w o

ccomis o.

Make IP reuse practical. rs is ic s o b cos-civ o mos

comis. I o coss mo o s Ip o bi i om scc. Ios wo

c Ip ms i c bo w i wi o, w icios i wi sv,

w cbiiis i os os o . t ms ovi oi ocmio

ivbs, io o qi cobii. Fi, Ip so b

oo vi so -vicio is o i iio s.

Maintain design intent. a si si o si i is ci

oo cio ocss wi v cos os. tis si so

b ocm cb b s o si ocss. lvi

omio bs o is commo si i wi v siic cos svis.

Integrate FOr prOFItaBIlIty

Apply piece-by-piece signo (iterative correctness). a siic oio o

ov si cos is o vicio, o vicio is om

ici s o si. as c Ip como is bi o soc,

ios so s i s qi cbii o o job. I comos

o vi vi, ios o wo bo ics

i-o cios w ssmb comos. t so b o

o -vi iivi bocs, v os soc .

Use enablement services. a com socs osi Ip m moi

som sciiz is o om v. Fo m, ii si com

mi soc som o Ip bocs wi mi-si iio

vicio. t is siic cos cim c i bii i

m wi o si o sis is is qim. a mo cos-

civ oc wo b o v o i- svics o is so-m

is .

A metric-driven, executable verication plan makes it possible to monitor and track

testing through coverage metrics and determine what still needs to be veried. The same

plan should also serve mixed-signal verication or analog and digital interaces.


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Oer visible integration. W o bocs bo io ii SoC, o ii

bocs bo io mos o IC, imo o o ii comos

o bc bos wi o visibii io i scs. O, bo

mos. tis ss i iciv iio si om i oo mc visibii, wic

cs omc, o oo i visibii, wic imcs qi. Bo oos ovis oIp so b js o visibii o s iio s.

OptIMIZe FOr prOFItaBIlIty

Optimize or cost. Wi cos m msiz cic iios sc s ow

omc, ios coc bo cos o si. t

o sc mos cos-ci immio voi ossib ov-si. t

iio oc ivovs ovsii wi siic s o bs o

miimiz oi obms cos isss. Fo m, bs m qi

imi mi s i s 30 o 50 c, oci ci si o so mc

bo-- o imi omc o vibii, wic i iocs

oo qi, siic ws, os obii . B vi cc-

isics sc s w-i sis bs o i vs o bscio, si ss si,

immio wss, o is i o ov-si c b voi.

Manage changes. Cs ivib, i is mm o is c

c m ic bw ob si s o sc, si

is o m i o m. as sc, i is imo o simi m c

wii si ocss. Fo ios, is is o o o cs m b i

ow m, b b ms o sis om wic Ip ws soc. W

cs , i imc so b miimiz, ociz, c o o

comio si o cbiiis sc s is mm, eCO omio, mic-iv vicio. Mi c civ is mi obii.

Consider sotware as a service. M si ms s o o si

viom v w si c fow b i ocio . Mc

o is ic is c o c o oi is sb ics

i isc. usi Sow-s--Svic ows si viom o b

co os si i ic i- svs o co

comi. SS c ios v cbiiis w

i. tis o c c si cos cc obii. B mi is

viom ocio-w, viom is oimiz o js o csom,

b o o is mci si. t s is i oimiz

si ocss w om si o mci.

I bi, bs w o ss obii is o v o-ow viw o w o

i o bi, om s m is s ossib, s vi comos c sim b s o. lo bocs ovi oo o. Wi lo bocs,

o s b visioi ojc sc s ci s. yo joi mi sm objcs

o o bi bi objcs, i oss. t o c c mi oss o

s. B si oi is si -sc visio o w o o bi.

Reuse is dicult and has not been cost-eective or most companies. It oten costs

more to reuse IP than to build it rom scratch.


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COnCluSIOn

Siico rizio s b o o cs, b w w oo i o

s o bo cos w b o ios, w sciv ms.

Wi iio eda s o ocs o scs o Siico rizio, v-icsi

sco o cs ms is mo wo v o cos ocivi .

Fo m, eda360 ss o is bscio v o bo o ii

si; s si socs o si i; mo mic-iv vicio; s si-

ss, coc-b-coscio si; ovi ii iioi oic

sic vs.

t w c is i ios cos obii . h, eda360 wi

ovi soios m Ip s si, ow iiv cocss, oimiz cos,

m c coss sis i ms. B eda360 is o

js bo oos coo; i so s io bsiss m mos.

Sow-s--Svic mos, o m, wi ios imov si ocss

coo coss, wi svics ms wi ovi ccss o is o

s- bsis.

Wi is c, w is Visio p w eda ic bis ocioo cos-civ, ow-ci siico. B o s, i is o jo b

wi -s m o mi, coc sow icios; w, im

cocivi; io, vio, 3d ics. W v s ow vom o

v-mo civ icios is ivi ssm vom ivi is o w

css o iovos c ios. W v sow ow s o ios

i om os o cos eda is s ws sv.

as wi cisis o ifcio oi, is bo ooi o isi

ovis. a Cc, w s ooi. W o b s i viiz eda

is wi sv bo cos ios. W wi wo wi o cossm

s o ovi css so o Ssm, SoC, Siico rizio, o

b w o icio-iv si. ps joi s s ow w o

i www.cadence.com/eda360 .
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2010 Cadence Design Systems, Inc. All rights reserved. Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. SystemC is a registered trademark

of the Open SystemC Initiative in the U.S. and in other countries and is used by permission. All others are properties of their respective holders. 21451 04/10 MK/ED/PDF


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Phone: 408.943.1234

Fax: 408.428.5001

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EDA360 the Way Forward Vision