EDA tools bridge the system-on-programmable-chip design gap

By Gabe Moretti, Technical Editor - July 25, 2002

Although programmable devices have been available for many years, their role in electronic

design is changing significantly. The increase in the number of gates per die available in

programmable devices and the high cost and complexity of ASIC development are major

contributors to their widening popularity. The industry calls programmable devices PLDs

(programmable-logic devices), CPLDs (complex programmable-logic devices), and FPGAs

(field-programmable gate arrays). Historically, the industry has used the term "PLD" for

smaller devices and "FPGA" for larger devices. Today, the distinction is less clear, and many

AT A GLANCE

Modern PLDs allow designers

to implement an entire system

on a programmable chip.

•

Device vendors are providing

more sophisticated EDA tools.

•

EDA-tools providers have

entered the growing and

financially rewarding PLD-tool

market.

•

Engineers find most of their

ASIC tools are needed for

SOPC (system-on-

programmable-chip)

development.

•

Sidebars:

Designing and debugging

embedded systems

vendors use "PLD" to designate the entire family of programmable-logic devices.

Modern PLDs allow engineers to implement entire systems on a single chip. The industry has

coined a new term for such designs—"SOPC" (system on programmable chip)—to parallel

the SOC (system-on-chip) terminology that ASIC design uses. In trying to solve the "entire-

embedded-SOC" problem, the industry must first address the platform architecture and then

prepare the appropriate tools for design, debugging, and test. Almost all embedded systems

require basic building blocks, including processing capability, memory, and logic. Different

applications and embedded products need a variety of peripherals and IP (intellectual

property), which you must often update or even change during the lifetime of a product.

PLD vendors now have device families that respond to these engineering requirements, with

chip architectures that combine massive, high-performance logic, digital-signal-processing

functions, embedded hard and soft microprocessor cores, multigigabit serial transceivers,

customizable IP, and a significant amount of memory to hold software programs. The

integration of hardware and software modules on a single chip requires new tools (see

sidebar "Designing and debugging embedded systems"). PLDs now cover a number of

application areas and provide operating speeds of more than 300 MHz for microprocessor

options and data throughput reaching 2 Gbits for each DSP. The combination of a variety of

available cores, memory, and programmable digital logic all manufactured with the latest

semiconductor technology, has created a new market. The NRE cost of ASICs has made

them too expensive for many companies to use. In addition, semiconductor houses like to

move their fabs to the newest process as soon as possible. But the ASIC capabilities of the

new processes are overkill for many applications that need "only" around 1 million logic

gates. It does not make financial sense to spend a lot of money for a die on a new process

and have a significant area of the die remain empty. As a result, the programmable-devices

market has seen growth as an alternative for low-end ASIC parts.

Available field-programmable devices

High-end programmable devices provide basic building blocks, including processing

capability, memory, and logic. Different applications and embedded products need a variety

of peripherals and IP, and engineers often need to update or even modify these components

during a product's lifetime. With a single family of programmable devices in inventory, a

design team can target a variety of applications and retain the flexibility of updating the

product as requirements evolve. Although an extensive survey of available devices is beyond

the scope of this article, you can get an idea of the available capabilities from an overview of

the high-end products from Actel, Altera, Quicklogic, and Xilinx.

Actel fabricates its ProASIC Plus family using 0.22-micron flash technology. It supports as

many as 1 million gates and 198 kbits of dual-port SRAM organized in 88 blocks of 256×9

bytes. The company provides a variety of cores, mostly from its third-party IP-partners

program. In it, you can find bus and communication protocols, microprocessors,

microcontrollers, and peripherals controllers. Actel also plays a role in the ASIC market by

providing FPGA cores that can be integrated into ASICs. This offering is particularly helpful

for high-end products in ASIC devices, which require multimillion gates and higher execution

speeds but remain reprogrammable in the field.

Altera combines two high-end product families to serve computation- and communication-

intensive markets. Its Stratix family is based on a 1.5V, 0.13-micron, all-layer-copper process

technology and offers as many as 114,140 logic elements, 10 Mbits of embedded memory,

optimized DSP blocks, and high-performance I/O on a single die. Designers can also use

Altera's soft core Nios embedded processor with Stratix to architect a system capable of 125

MHz to meet the needs of high-bandwidth systems. The Excalibur family combines logic,

memory, and a processor core. The core can be either the Nios soft core or the ARM-based

ARM922T hard core. The ARM922T can achieve more than 200 MIPS and integrates

onboard memory and logic sectors, external memory interfaces, and standard peripherals.

Both product families let you develop a system on a single chip. Altera has taken an

additional step in this market by instituting the HardCopy program. It lets customers order

parts that are exact replicas of their FPGAs but have the programmability removed, resulting

in lower cost per die and higher yields. It is the closest you can get to having your own cake

and eating it too.

The Eclipse family from Quicklogic provides system-level features with internal device speed

of 600 MHz, resulting in chip-to-chip I/O performance of 225 MHz. You can have as much as

82,944 bits of dual-port RAM, 45 clock/control networks, four PLLs, a variety of I/O protocols,

and programmable slew rates. Quicklogic provides both 32- and 64-bit PCI for its devices

and offers one product family that incorporates the MIPS32 core and one that offers fast DSP

elements. If you have a 6800, 8051, or equivalent soft core, you can build an entire system

using a couple of devices from Quicklogic's product families.

Virtex-II Pro is the flagship product family from Xilinx. It offers as many as four PowerPC

RISC cores delivering 420 MIPS each and supporting IBM CoreConnect bus architecture on

a chip (www.ibm.com). The I/O features of this device family provide as many as 16

transceiver blocks, capable of baud rates reaching 3.125 Gbps, resulting in a possible duplex

data rate of 80 Gbps. Other salient features of the devices are as much as 4 Mbits of DRAM,

706 kbits of SelectRAM, and 216 18×18-bit multiplier blocks.

Engineers selecting any of these devices can implement complex designs that they could

have realized just two or three years with only ASIC technology. FPGAs have migrated from

devices that engineers use to collect required hardware-logic circuitry inside one package to

platforms that allow the implementation of systems that can displace microcontrollers and

low-end microprocessors and their associated memory devices from the pc board.

A new EDA landscape

One of the effects of the new market has been a significant change in the EDA tools

designers use to develop programmable-logic designs. When development was based on

schematic entry, device vendors offered most of the tools used for development, often free or

at nominal cost. Therefore, it did not make financial sense for EDA vendors to enter the

market. The situation started changing when designs became complex enough to require

logic simulation and debugging, instead of programming the device and trying it out on a

breadboard. As the complexity increased, direct mapping of a netlist became impossible, and

synthesis programs were developed. Some vendors, notably Xilinx, developed their own

synthesis tool, but most relied on products from EDA vendors.

Consulting company Intrinsix helps clients develop products using FPGAs for networking,

set-top, and video applications. Intrinsix consultant Nick Suttora finds that engineers now

need to use a team-design approach to cope with the size and complexity of the circuit

targeting FPGA implementation. Not too long ago, one engineer would implement an entire

design using schematic entry and EDIF (Electronic Design Interchange Format) output. The

development methods necessary today are similar to the ASIC methods from design

planning through synthesis; only place-and-route functions differ, because the physics of the

two families of devices differs radically. To develop and debug a PLD-based design, you can

use hardware tools, software tools from the silicon vendor, and software tools from

independent EDA vendors. (For more information on hardware tools, see Reference 1.)

Engineers can also mix and match tools from both FPGA vendors and independent EDA

companies to build a flow that best suits their technical and financial requirements.

Silicon vendors' tools

Although a number of PLD vendors exist, not all offer SOPC capabilities and the

development tools that designers require. Actel provides Libero, an integrated design

environment for its ProASIC Plus devices. It includes in-house-developed Designer and

Silicon Sculptor tools for place and route and programming of the devices and Silicon

Explorer for real-time debugging. The rest of the components in the tool suite are licensed

from EDA vendors. These tools help designers develop, verify, and synthesize SOPCs. If you

want to use schematic entry, you can use ViewDraw from Innoveda, and you can mix the

schematic with blocks written in VHDL or Verilog. You can use ModelSim from Mentor

Graphics for verification and for testbench generation, you can use a version of WaveFormer

from Synapticad tailored for Actel. Depending on your requirements, you use Synplicity's

Synplify or Synplify-Lite synthesis tools with Libero.

Actel's Designer also allows engineers to perform static-timing analysis and to estimate

power consumption, a critical parameter in most of the designs that use these devices, which

on average tend to use less power than comparable products from other vendors. Actel also

offers the Designer series development suite, but don't confuse the suite with the Designer

tool, in spite of naming similarities. The Designer development suite allows you to plug in

third-party development tools. It also provides hardware-design aids, such as generation of

clock-conditioning circuits, PLL configurations, 24 RAM/FIFO configurations, and clock-tree

split, as well as functions that help designers interface the device to the board.

Altera provides its customers with Quartus II design software. It offers a framework that

encompasses embedded software, digital-signal processing, board- level analysis, and

synthesis. Figure 1 shows the various components. The blue icons represent files and

models, the yellow blocks show the tools most likely required for SOPC development, and

the green boxes show tools that engineers can use during design verification. SOPC Builder

provides designers with a platform-based method to compose systems using an inventory of

bus-common components. You can find processors, peripheral controllers, and even

software—such as device drivers and OS kernels—in its library.

DSP Builder combines the algorithm development, simulation, and verification capabilities of

The Mathworks' Matlab and Simulink with the rest of Altera's development tools. You use the

Signal Processing Toolbox and the Filter Design Toolbox in Matlab to design the algorithms

that Simulink can then simulate. The DSP Builder's SignalCompiler block then reads

Simulink model files and generates VHDL files and scripts for synthesis, hardware

implementation, and simulation. Like most PLD vendors, Altera does not market its own

verification or synthesis tools. Instead, it relies on OEMs and packages the tools in its

software offering. Mentor Graphics provides ModelSim for simulation and LeonardoSpectrum

for synthesis for Altera products.

Engineers using the Excalibur processors can use the SoftMode co-design feature in

Quartus II, which integrates embedded-processor-development tools, such as a C/C++

compiler, a debugger, and related utilities. The SOPC must meet both chip- and board-level

timing requirements. The Quartus II software includes chip-level timing analysis and outputs

standard-format files to allow engineers to use third-party tools for board-level timing

analysis. Signal integrity and electromagnetic compatibility are key requirements in high-

speed systems. Engineers can obtain IBIS (input/output buffer information specification)

models in Quartus II that are customized based on the I/O standard settings for each pin in

the design. Third-party tools use the models to provide a complete analysis of the board for

compliance verification. Power consumption is an important factor for many handheld-device

applications. The Quartus II PowerGauge analysis tool uses the designer's simulation files to

link the power-consumption estimate with customer-specific design files and operating

parameters for analysis and optimization.

Quicklogic provides design support for Windows or Unix, as well as the WebESP Web-based

design environment. You can establish an account with Quicklogic and then use WebESP's

simple steps, to configure a device that implements a communication protocol (Figure 2). The

tool presents a menu of available protocols you can choose from. The company then mails

you the programmed device within days.

The development environment that Quicklogic provides outside the Web offers tools that both

its own staff and third parties developed. Indigenous tools include support for schematic

capture, place and route, static-timing analysis, and a number of wizards to develop memory,

DSP, and SERDES blocks. You can perform logic verification using either Silos III from

Simucad for Verilog designs or Aldec's simulator for VHDL. You can enter the design in HDL

by using TurboWriter HDL editor from Saros Technology. Designers have access to

Synplicity's Synplify-Lite for synthesis. Quicklogic's QuickMIPS family of devices has

additional development tools specific to its system-design needs. Engineers can obtain

drivers for Ethernet, PCI, UART, and other devices, as well as WindRivers' VXWorks or

BlueCat Linux RTOS from Lynuxworks tailored to the target core.

ISE Foundation is Xilinx's EDA-support package. It provides tools for design entry, synthesis,

implementation, verification, and board integration. In addition to schematic entry and

generators for state machines, DSP, and cores, the design-entry package offers Project

Navigator. This tool allows designers to look at the project hierarchy, facilitating the

navigation through the various modules and providing a graphical representation of the

relationships among the modules of the design. Xilinx provides the XST synthesis product for

its devices. The tool implements register-balancing capabilities in addition to supporting

incremental-design, modular-design, and team-design methodologies. A seamless

integration with third-party synthesis products is also available through ISE Foundation.

Most SOPC designs require timing-driven placement and routing. In ISE, when you specify

timing requirements for critical paths, you have a number of available tools to improve the

performance of your circuit. They include Timing Analyzer, a constraints editor with

TimeSpecs, Floorplanner, and timing closure with ProActive. Timing Analyzer reports a

variety of data about the timing of your design. It includes a hierarchical browsing capability

and a what-if feature that allows for the immediate analysis of your design when targeting

various devices speeds or using different timing constraints. A cross-probing feature provides

a graphical view of critical timing paths between Timing Analyzer and Floorplanner. The

constraints editor guides designers through constraints creation without requiring them to

understand the underlying, often complex, syntax that some EDA tools require. Floorplanner

is particularly useful on structured designs and datapath logic. Designers can see where to

place logic for optimal results.

Invoking Floorplanner after you place and route a design allows you to view and possibly

improve the results of the automatic implementation. Engineers using the ISE Foundation

tools have access to a Xilinx-specific version of ModelSim from Mentor Graphics for design

verification, together with a number of other tools, such as Xpower for power analysis and

HDL Bencher for testbench development. The ChipScope ILA debugging tool embeds a

logic-analyzer core in the design. Once engineers finish debugging, they can reprogram the

chip and eliminate the debug core. This tool is especially useful if you need to debug a

specific module or the interface between two modules before the entire design is complete.

To support integration of an SOPC design with the rest of the circuitry on a board, Xilinx

makes available IBIS models of its devices. In certain high-speed designs, the limitations of

the IBIS format mean that these models are not powerful enough to guarantee error-free

integration. In such cases, engineers can obtain, under separate license, Spice models

compatible with Cadence's SpecctraQuest simulator.

EDA vendors' tools

PLDs that support SOPC can replace some ASIC devices. Therefore, their development

process is just as difficult as that of an ASIC. System companies last year spent more than

$2 billion on EDA tools. More than half of the investment was to support ASIC design. These

companies would like to extend the benefit of their investments by also using the tools for

SOPC design. In addition, using third-party tools allows a company to be independent of the

silicon vendor, thus increasing the probability of more favorable financial arrangements

during the life of the product. All PLD vendors offer integration capabilities that allow

designers to use third-party tools with the required proprietary tools for SOPC development.

Cadence and Synopsys provide high-end simulation, synthesis, and board-integration tools.

They view the SOPC market as an extension of the ASIC market. Many of their customers

develop both SOC and SOPC circuits using the same design team, so it makes sense that

the same tools they would use for both. Synopsys had a special synthesis product targeting

the programmable-devices market, but it has now discontinued it in favor of FPGA Compiler.

This product shares significant amount of technology with Design Compiler, the market

leader for ASIC synthesis. Mentor Graphics has had a market presence in PLDs for many

years. Through its acquisition of Model Technology and Exemplar Logic, it holds, with

ModelSim, the leading position in design simulation and verification and has lately increased

its engineering efforts in synthesis, first targeting programmable devices and later ASICs. Its

newly Precision Synthesis complements and extends LeonardoSpectrum, which has for

some time been in the market. Among the three leading EDA vendors, only Mentor offers a

complete suite of tools targeting programmable devices. The FPGA Advantage development

environment allows you to visualize the architecture of the design, invoke simulation and

synthesis, and debug the design with cross-probing between two tools. Synplicity also makes

its synthesis-and-verification products available to SOPC designers. The company has

established a leading position in the programmable-device market. As with Cadence and

Synopsys, it sees the overlap between ASIC and FPGA applications, and it has now also

introduced a synthesis product for the ASIC market.

Celoxica primarily targets SOPC design. Its DK1.1 integrated development environment

supports the design, validation, iterative refinement, and implementation of complex

algorithms in programmable devices. DK1.1 includes built-in design entry, simulation, and

synthesis—all driven by Handel-C. The Handel-C hardware-implementation language is

based on ANSI-C. It delivers a level of abstraction over RTL, enabling designers to describe

the desired function rather than its underlying structural detail. With Handel-C, you can

restructure ANSI-C programs using parallel constructs and pipelining and accelerate them in

hardware.

Supporting DK1.1 is Celoxica's PAL (Platform Abstraction layer) API and DSM (Data Stream

Manager). PAL and DSM borrow a model from the software world by leveraging libraries of

predefined functions to access processors and peripherals via common APIs.

PAL, an API for accessing peripherals, abstracts the underlying devices and instead presents

an interface for migrating Handel-C applications between hardware platforms. Developed in

partnership with WindRiver, DSM is an API for communicating between hardware and

software that abstracts underlying bus transport. DSM allows integration between

microprocessor applications and Handel-C programs.

Start-up AccelChip addresses the problem of developing DSPs on programmable devices. It

markets a product that takes the direct output of Matlab and Simulink and generates

synthesizable Verilog or VHDL models with their respective testbenches. Xilinx has recently

made two agreements that aim to provide its customers with system-architecture-planning

and formal-verification capabilities. CoWare will integrate its N2C architectural planning

product with Xilinx's ISE environment, and Atrenta will do the same with its Spyglass

predictive-analysis product. As complexity continues to rise, you can expect vendors to

refocus more tools traditionally targeting the ASIC-design market on programmable-device

users.

Reference

Dipert, Brian "Tools help you lose the hardware blues," EDN, April 18, 2002, pg 36.1.