ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS

DESIGN

Dr. ShiDept. of Electrical and Computer Engineering

Random Access Memory (RAM)

Static (SRAM) and Dynamic (DRAM)

SRAMs Static Random Access Memory (SRAM)

Each bit is a latch made of 6 to 8 transistors. Fast, used for CPU cache

World Line to select

Bit Line to read/write

DRAMs Dynamic Random Access Memory

Each bit (cell) uses 1 capacitor and 1 transistor Charge will leak, so need to refresh every few us Inexpensive, used for main memory

Flash Memory: Non-volatile RAM Both SRAM and DRAM will lose its

content when power is turned off Flash memory hold data in “floating

gate”

READ ONLY MEMORIES (ROM)

Overview Read-only memory can normally only be read Internal organization similar to SRAM ROMs are effective at implementing truth tables

Any logic function can be implemented using ROMs Multiple single-bit functions embedded in a single ROM Also used in computer systems for initialization

ROM doesn’t lose storage value when power is removed Very useful for implementing FSMs

Read-Only Memory (ROM) An array of semiconductor devices

diodes transistors field effect transistors

2N words by M bits Data can be read but not changed

(normal operating conditions)

N input bits 2N words by M bits Implement M arbitrary functions of N variables

Example 8 words by 5 bits:

Read-Only Memory (ROM)

3 InputLines

ABC

F0 F1 F2 F3 F4

5 Output Lines

ROM8 wordsx 5 bits

ROM = "Read Only Memory" values of memory locations are fixed ahead of time

A ROM can be used to implement a truth table if the address is m-bits, we can address 2m entries in the ROM. our outputs are the bits of data that the address points to.

ROM is a combinational device, not a sequential one

m is the "height", and n is the "width"

ROM Implementation

m n

0 0 0 0 0 1 10 0 1 1 1 0 00 1 0 1 1 0 00 1 1 1 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 11 1 0 0 1 1 01 1 1 0 1 1 1

Suppose there are 10 inputs10 address lines (i.e., 210 = 1024

different addresses) Suppose there are 20 outputs

ROM is 210 x 20 = 20K bits

Rather wasteful, since lots of storage bits For functions, doesn’t take advantage of K-

maps, other minimizations

ROM Implementation

Each minterm of each function can be specifiedRead-Only Memory (ROM)

3 InputsLines

ABC

F0 F1 F2 F3 F4

5 Outputs Lines

ROM8 wordsx 5 bits

A B C F0 F1 F 2 F 3 F 4

0 0 0 0 1 0 1 00 0 1 1 1 1 1 00 1 0 0 0 0 1 10 1 1 1 1 1 0 11 0 0 0 1 0 1 01 0 1 0 1 1 1 11 1 0 1 0 1 0 11 1 1 1 1 0 1 0

ROM Internal Structure

...

n InputsLines

n bitdecoder

...

m Outputs Lines

.

.

.Memory Array

2n words x m bits

ROM Memory Array

3 to 8decoder

A

B

C

m0=A’B’C’

m1=A’B’C

m2=A’BC’

m3=A’BC

m4=AB’C’

m5=AB’C

m6=ABC’

m7=ABC

F0 F1 F2 F3 F4

Inside the ROM Alternate view

Each possible horizontal/vertical intersection indicates a possible connection

Or gates at bottom output the word selected by the decoder (32 x 8)

ROM Example

A B C F G H

0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

Specify a truth table for a ROM which implements: F = AB + A’BC’ G = A’B’C + C’ H = AB’C’ + ABC’ + A’B’C

ROM Example

A B C F G H

0 0 0 00 0 1 00 1 0 10 1 1 01 0 0 01 0 1 01 1 0 11 1 1 1

Specify a truth table for a ROM which implements: F = AB + A’BC’ G = A’B’C + C’ H = AB’C’ + ABC’ + A’B’C

ROM ExampleSpecify a truth table for a ROM which implements: F = AB + A’BC’ G = A’B’C + C’ H = AB’C’ + ABC’ + A’B’C A B C F G H

0 0 0 0 1 00 0 1 0 1 10 1 0 1 1 00 1 1 0 0 01 0 0 0 1 11 0 1 0 0 01 1 0 1 1 11 1 1 1 0 0

Function Implementation

3 to 8decoder

A

B

C

m0=A’B’C’

m1=A’B’C

m2=A’BC’

m3=A’BC

m4=AB’C’

m5=AB’C

m6=ABC’

m7=ABC

F G H Each column is a new functionNote: two outputs unused!

ROM Implementation of a Moore Machine ROMs implement combinational logic Note that ROMs do not hold state How would you determine the maximum clock

frequency of this circuit? Look at the FF to FF path (NS to PS)

ROM ROMPresent State

Next State

Outputs

Inputs

ROM Implementation of a Mealy Machine

ROMs implement combinational logic Note that ROMs do not hold state How would you determine the maximum clock

frequency of this circuit? Look at the FF to FF path (NS to PS)

ROM

ROMPresent State

Next State

Outputs

Inputs

Summary ROMs provide stable storage for data ROMs have address inputs and data outputs

ROMs directly implement truth tables ROMs can be used effectively in Mealy and Moore

machines to implement combinational logic In normal use ROMs are read-only

They are only read, not written ROMs are often used by computers to store critical

information Unlike SRAM, they maintain their storage after the power is

turned off

PROGRAMMABLE LOGIC ARRAYS (PLA)

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Programmable logic arrays A ROM is potentially inefficient because it

uses a decoder, which generates all possible minterms. No circuit minimization is done.

Using a ROM to implement an n-input function requires: An n-to-2n decoder, with n inverters and 2n n-

input AND gates. An OR gate with up to 2n inputs. The number of gates roughly doubles for each

additional ROM input.

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Programmable logic arrays A programmable logic array, or PLA,

makes the decoder part of the ROM “programmable” too. Instead of generating all minterms, you can choose which products (not necessarily minterms) to generate.

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A blank 3 x 4 x 3 PLA

This is a 3 x 4 x 3 PLA (3 inputs, up to 4 product terms, and 3 outputs), ready to be programmed.

Inputs

Outputs

AND array

OR array

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PLA example

V2 V1 V0

xy’z’

xy

x’z

x’yz’

V2 = m(1,2,3,4)= xy’z’ + x’z + x’yz’V1 = m(2,6,7) = x’yz’ + xyV0 = m(4,6,7) = xy’z’ + xy

x y z

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PLA evaluation A k x m x n PLA can implement up to n functions

of k inputs, each of which must be expressible with no more than m product terms.

Unlike ROMs, PLAs allow you to choose which products are generated. This can significantly reduce the fan-in (number of

inputs) of gates, as well as the total number of gates.

However, a PLA is less general than a ROM. Not all functions may be expressible with the limited number of AND gates in a given PLA.