Last (family) name: _________________________ First (given) name: _________________________ Student I.D. #: _____________________________ Circle section: Hu Saluja

Department of Electrical and Computer Engineering University of Wisconsin - Madison

ECE/CS 352 Digital System Fundamentals

Final Exam Sunday, May 12, 2002 7:45 AM--9:45AM

Instructions: 1. Closed book examination.2. No calculator, hand-held computer or portable computer allowed. 3. Five points penalty if you fail to enter name, ID#, or instructor selection. 4. Answer must be entered into specified boxes if provided. 5. You must show your work to receive full or partial credit for your answers. 6. No one shall leave room during last 5 minutes of the examination. 7. Upon announcement of the end of the exam, stop writing on the exam paper immediately.

Pass the exam to isles to be picked up by a TA. The instructor will announce when to leave the room.

8. Failure to follow instructions may result in forfeiture of your exam and will be handled according to UWS 14 Academic misconduct procedures.

ECE/CS 352 Final Exam May 12, 2002

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Problem Points Score

1 20

2 20

3 15

4 10

5 10

6 10

7 15

Total 100

1. (20 points) Review problems

(a) (4 points) If (10n01)2 = (33)r. Find both n and r.

Answer: n = r =

S02, ECE/CS 352 Quiz #4

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(b) (4 points) Let A, and B be two Boolean variables. Determine whether the following Boolean identity is true or false. If you decide it is true, briefly explain why in the space provided. If you claim it is false, give a counter example in the space provided. No credits will be given without the explanation or a counter example.

1=⋅+⋅ BABA

Answer: (circle one) TRUE FALSE Explanation or counter example (required):

(c) (4 points) Derive the Boolean function in SOP standard form of the following logic

diagram:

A

B C

D

F(A,B,C,D)

Answer: F(A, B, C, D) =

ECE/CS 352 Final Exam May 12, 2002

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(d) (3 points) Perform two’s complement subtraction (number of bits n = 5). Must show work to receive credit.

01010 − 01011 = Answer:

(e) (5 Points) A circuit shown below will be analyzed for maximum clock rate. Assume

that the circuit has been minimized.

C

D Q

Q'

C

D Q

Q'

C

D Q

Q'

C

D Q

Q'

CLOCKCLOCK

All gates and flip flops implementing the circuit have the following timing parameters:

Parameter Value (all times in nanoseconds)

Flip Flop Clock to output tpLH (min) = 4.0, tpLH (max) = 8.0 tpHL (min) = 2.0, tpHL (max) = 6.0

Flip-Flop Setup time tsu = 4.0 (min)

Flip-flop Hold time th = 1.0 (min)

Logic gate delay tpLH (min) = 2.0, tpLH (max) = 7.0 tpHL (min) = 1.0, tpHL (max) = 4.0

(2 points) What is the maximum number of logic levels (logic gate delay) through the circuit? Answer: (3 points) What is the minimum clock period for the circuit to ensure it will function properly? Answer: ns.

ECE/CS 352 Final Exam May 12, 2002

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2. (20 points) Review Problems (a) (3 points) Two n-bit signed binary numbers 1 2 1n nA A A A A− − 0= L and

1 2 1n n 0B B B B B− −= L are to be added using an n-bit parallel adder where Ai’s and Bi’s are Boolean variables. The sum is designated as 1 2 1 0n nS S S S S− −= L . A Boolean function V = 1 if overflow occurs, and V = 0 otherwise. Give the Boolean express for V in minimized sum of product (SOP) standard form as a function of Ai’s, Bi’s, and Si’s. Answer: V =

(b) (3 points) How many address lines and how many data lines a 32M × 8 DRAM chip has? Answer:

(2 points) number of address lines =

(1 point) number of data lines =

ECE/CS 352 Final Exam May 12, 2002

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(c) (4 points) Circle all the essential prime implicants (EPI) among the following list of product terms of a Boolean function f(a, b, c).

a b⋅ a c⋅ b c⋅ a b⋅

(d) (4 points) Find the Boolean function F(w,x,y) and express it in the simplified SOP format.

2-to-1 S MUX 0 1 x ⋅ y

x + y

w F(w,x,y)

Answer: F(w, x, y) =

ECE/CS 352 Final Exam May 12, 2002

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(e) (6 Points) The clock "CLOCK" signal shown graphically below is tied in common to five different, single-bit flip-flops (or latches). The "A" signal is tied to the "D", "T", "J" inputs of any D, T, or JK flip-flop (or latch) respectively. The "B" signal is tied to the "K" inputs of any JK flip-flop (or latch) respectively. The "Q" outputs of these different flip-flops (or latches) are shown as signals W1, W2 and W3 Assume that the clock period is MUCH LONGER than the clock to output delay of the flip-flops or latches.

For each row in the table below, mark an "X" in the column for the waveform if that waveform is possible for the flip-flop listed. If none of the waveforms fit the flip-flop type, mark an "X" in the column labeled "NONE".

Flip-Flop or Latch Type W1 W2 W3 NONE

Positive Edge-Triggered JK Flip-Flop

Positive Clock Gated (clock pulse triggered) D Latch

Negative Edge Triggered T Flip-Flop

ECE/CS 352 Final Exam May 12, 2002

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3. (15 Points) Register Transfers, bus

(a) (8 points) The following register transfer operations will be implemented where K1, K0 are two input Boolean variables:

01 KK ⋅ : R1 ← R2 01 KK ⋅ : R2 ← R3 01 KK ⋅ : R3 ← R2 01 KK ⋅ : R1 ← R4

All four n-bit registers R1, R2, R3, and R4 have three-state bi-directional input/output lines connecting to a single shared bus as shown in the figure below. Fill-in the control signals (Load and En(able)) to each of these four registers so that the above conditional register transfer operations can be realized.

R1

Load

EN

R2

Load

EN

R3

Load

EN

Load

R4

EN

Answer:

Load EN R1

R2

R3

R4

ECE/CS 352 Final Exam May 12, 2002

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(b) (7 points) The following is a list of register transfer micro-operations. They are originally written so that they can be executed from top to bottom in a sequential order.

R2 ← R1R3 ← R5R4 ← R1R1 ← R5R5 ← R6

In order to accelerate computation, it is possible to execute more than one micro-operations per clock cycle without altering the final results in each register. Consider two situations: (i) (4 points) Suppose that each register is connected to a single three-state bus via bi-

directional input/output lines. Execute above five micro-operations in no more than three clock cycles: Answer:

Clock cycle Register transfer operations

1

2

3

(ii) (3 points) Suppose that the number of buses has no limit. Can all these micro-

operations be implemented within a single clock cycle? Must give an explanation to the answer to receive credit.

YES NO

Explanation:

ECE/CS 352 Final Exam May 12, 2002

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4. (10 points) ALU

Full Adder X Sum Y Carry Carry out in

Ci

S1

S0

Cin AiBi Fi

Ci+1

Depicted above is an ALU bit slice which can perform both arithmetic and logic operations by choosing appropriate control signals Cin, S0 and S1 where C0 = Cin. Let F = Fn−1…F1F0 to be the output, A = An−1…A1A0 and B = Bn−1…B1B0. Complete the function table below. Answer:

S1 S0 Cin = 0 Cin = 1

0 0 A ⊕ B A

0 1

1 0 A + B

1 1

ECE/CS 352 Final Exam May 12, 2002

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5. (10 Points) Seq

(a) (3 points) Theinput sequence

Answer:

(b) (2 points) Thestate diagram i

MOORE

(c) (5 points) In thabove. LABLE

ECE/CS 352 Final Ex

uenc

Stat pat

sequs (cir

e spa all

am

e Recognizers, Moore and Mealy Models and ASM Charts.

e Diagram to the right recognizes an tern. What is it?

a

b c

x=1/y=0x=0/y=0

x=0/y=0

x=0/y=0

x=1/y=1

x=1/y=0

ential machine model described by the cle the CORRECT one):

MEALY

ce below, draw an ASM chart EQUIVALENT to the State Diagram states, inputs, and outputs consistent with the above State Diagram.

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6. (10 points) One-flip-flop-per-state implementation Below is an ASM chart of a certain controller. Implement this ASM chart using one-state-per-state method. Using positive edge triggered flip-flops, AND, OR, NOT gates. Simplify the design to use as few logic gates as possible.

Idle S0

G 0

1

check S1

Q

0

K ← n − 1, Acc ← 0

Rc ← 1 1

Answer:

ECE/CS 352 Final Exam May 12, 2002

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7. (15 Points) Datapath (a) (10 points) The simple datapath studied in Chapter 7 is used for this question. The

detailed description of the micro-operations and control bits is attached to the end of this exam. Use it to help answer the following questions. FILL IN the table below with the appropriate missing entry. If the field is unused, denote it by placing a dash " -- " in the field. All microinstruction values are BINARY.

Operation DA AA BA MB FS MD WR

R0 ← R0 ⊕ R0

R3 ← M[R0]

011 001 -- -- 1 0 1 0 0 0 1

M[R0] ← R2

R3 ← R3 + 1

(b) (5 points) Registers R1 and R2 have the values shown in the table below. Fill in the

VALUE of Register R0 AFTER the instruction executes. Also fill in the C, Z, N, and V bits that change based on the operations. NOTE: Assume N and Z status bits change for all ALU or shift operations and C and V bits do not change for logical or shift operations (as indicated by " -- " in the table below).

Operation R0(t+1) R1(t) R2(t) C V Z N

R0 ← R1 ⊕ R2 11110000 00110011 -- --

R0 ← R1 + R2 11111111 00000001

R0 ← sl R2 00010000 11101111 -- --

R0 ← R1+ 2R +1 11111111 00000001

ECE/CS 352 Final Exam May 12, 2002

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ECE/CS 352 Final Exam May 12, 2002

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Flip-Flop Excitation Tables JK Flip-Flop SR Flip-Flop Q(t) Q(t+1) J K Q(t) Q(t+1) S R

0 0 0 X 0 0 0 X 0 1 1 X 0 1 1 0 1 0 X 1 1 0 0 1 1 1 X 0 1 1 X 0

D Flip-Flop T Flip-Flop

Q(t) Q(t+1) D Q(t) Q(t+1) T 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 1 0 1 1 1 1 1 1 0