1

Abstract— The Fast Fourier Transform has long been

one of the most vital signal processing tools with prominent roles in many simulation packages such as Matlab. This report details the simulation, synthesis, and physical layout of a 64 point FFT block using ModelSim, Design XG, and Cadence Encounter in the 90nm CMOS process. This document also serves as a reference for future projects requiring digital layout techniques.

I. INTRODUCTION One of the most important signal processing tools available

to the modern day circuit designer or systems analyst is the Fast Fourier Transform or FFT. The FFT is an efficient means of determining the frequency content of a given waveform and has been used in calculations ranging from correlation studies, mechanical oscillatory behavior, and the more common electrical circuits frequency domain analysis. While the current from of the FFT was derived from formulation done by J. W. Cooley and J. W. Turkey in the late 1950’s, the Discrete Fourier Transform’s roots (from which the FFT is derived) date back to the early 1700’s with Euler and Gauss [1].

The 64 point FFT simulated used a design based off of the Cooley Turkey FFT algorithm. This algorithm uses small, premade Discrete Fourier Transform blocks (8 in our case) and divides the input up into smaller, orthogonal sets for computation before combining back into a larger numerical string [2]. The numerical combinations are done with the use of a butterfly processor for efficient computation [3]. While fairly complex to design in its entirety, the simulation of a premade core can be an efficient option for many modern day integrated circuit designers as shall be described in this paper.

For this project, our team used a 64 point, 32 bit input FFT core from Opencores.com. The lead designer of the core was Arish Alreja from Georgia Tech for use in an orthogonal division multiplexing device. The source code for the project can be found at the open cores website located here: http://www.opencores.org/cvsweb.shtml/fftprocessor/. 90nm standard libraries provided by Jacob Postman.

II. FFT SIMULATION

The simulation of the FFT block was completed in ModelSim and was validated with test data provided in

Manuscript submitted December 12, 2008. M. Nasroullahi and J. Guerber are students at Oregon State University,

Corvallis, Oregon. They are members of the Analog and Mixed Signal Group in the School of Electrical Engineering and Computer Science. (For email: M. Nasroullahi – nasroulm@onid.orst.edu; J. Guerber: guerberj@engr.orst.edu).

Matlab. The time domain input waves for the FFT have been created with Matlab M-files, and imported to ModelSim for generating the frequency domain output files. The output files were then imported back into Matlab and compared with processed data from the Matlab FFT function. The result from the Verilog simulated FFT was reasonably close to the actual result, thus allowing our team to be satisfied with the functionality of the FFT processer we were to synthesize.

III. SYNTHESIS AND SCHEMATIC GENERATION After an acceptable simulation, all developed digital ASIC

chips must be synthesized to the schematic level. For the digital process used in this project, the synthesis tool was Design Vision. The process of generating a full schematic view of Verilog input code is simple, only requiring the modification of the “dc_syn” input file, and making a top level file, which we called “FFT.” The result yields a gate level output file which can then be ported to place and route tools such as Cadence Encounter. For a step by step explanation of the synthesis procedure, see Appendix A.

Figure 1: Sample Design Vision Schematic

IV. PHYSICAL LAYOUT

With full schematics, the physical layout of the FFT block was completed using Cadence Encounter. To initialize the process, all configuration and input files must first be loaded into the tool. In the graphical user interface, a blank chip of the correct size appears and outer power rails must then be added. For this design, our rails were laid out to be 10 microns wide in metals 1 and 2 for least via losses but it would have been preferable in retrospect to use metals 5 and 6 for highest conductivity. Inner power rails were then added for supporting each of the individual cells.

Simulation and Synthesis of a 64 Point FFT Mohsen Nasroullahi and Jon Guerber, Oregon State University, EECS

2

After adding power support, pins were placed around that outside of the chip with their location based on functionality. The data input and output lines were placed on the top and bottom respectively, while the address line pins were placed on the left side. Control signal IOs were placed in the top left corner for the chip. Following pin placement, cells were automatically laid down based on timing and grouping optimization algorithms. Due to the specified density requirements and floorplan specifications, spaces are present between cells which can be filled with dummy fillers of varying lengths. With all the cells present, routing wires can be automatically generated with the “WRoute” algorithm provided by encounter. The final digital FFT layout can be seen in Figure 2 with a closeup of routing in Figure 3. For a detailed explanation of how to port synthesized designs to an encounter layout, see the AMS wiki page at https://secure.engr.oregonstate.edu/wiki/ams/index.php/Cadence/DigitalSynthesisAndLayout.

V. RESULTS Below is a table of simulated results for the FFT core laid

out in Cadence Encounter.

VI. CONCLUSION This project has familiarized our team with the tools of

digital layout and the process of transferring information from code level data, to gate level extraction, layout, and further fabrication and chip tapeout. Our team has been introduced to the FFT functionality however, not to the extent of being able to write code from the mathematical models, which is outside the scope of this class. This useful 64 point FFT can be extended to a 1024 point FFT by modifying the Verilog code by computer science developers.

VII. REFERENCES [1] Heideman, M.; Johnson, D.; Burrus, C. “Gauss and the history of the

fast fourier transform,” ASSP Magazine, IEEE Volume 1, Issue 4, Oct 1984 Page(s):14 - 21

[2] S. Mitra, “Digital Signal Processing: A Computer Based Approach,” McGraw Hill, NY, NY, pp. 610-620, 2006.

[3] A. Alreja; “Real Time OFDM engine for High Speed Wireless Applications” Georgia Institute of Technology, www.opencores.com created Feb 2006, retrieved, Dec, 2008.

Figure 2: 64 Point FFT Digital Layout

Figure 3: Routing wires seen in Cadence Encounter Layout

TABLE I FFT SYNTHESIS AND LAYOUT RESULTS

Parameter Value

Area Total Die Area

≈ 50,000 µm²

Cell and Filler Area 26,000 µm² Cell Area 19,000 µm² Number of Cells 2745

Parasitics Total Capacitance Power Estimated Static Power Loss (From Vdd) Estimated Dynamic Power (100MHz)¹

21.15 pF 2.4 mW 1.93mW

Values were found from Cadence Encounter. (¹)Dynamic power estimates made from P = C(V^2)f.

3

VIII. APPENDIX A: DESIGN VISION PROCESS The process of generating schematic representations of our

chip using Design Vision are detailed in the following table.

Mohsen Nasroullahi (S’05) received the B.S. degree in Electrical Engineering from Oregon State University in 2008 and is currently working towards a Masters in Electrical and Computer Engineering at the same institution. He is currently a research member of the Analog Mixed Signal group at Oregon State University in Corvallis, Oregon with a focus on the low power and battery free RF Transceivers for aerospace or military application. During summer 2007, he was with Cassini Instrument Operation Team, at Jet Propulsion Laboratory, Pasadena California as software engineer.

Jon Guerber (S’05) received the B.S. degree in Electrical Engineering from Oregon State University in 2008 and is currently working towards a Masters in Electrical Engineering from Oregon State University. He is currently a research member of the Analog and Mixed Signal group at Oregon State University in Corvallis, Oregon with a focus in the area of Submicron Analog to Digital Conversion. During the summer of 2008, he was with Terdayne in their Semiconductor Test design team. Mr. Guerber is a life member of the Eta Kappa Nu

Electrical Engineering Society, an active Wikipedia contributor, long distance runner, and active in his church.

DESIGN VISION IC SYNTHESIS STEPS

Step Description

1. Place Input Files The input verilog code files should be copied into a new folder where Design Vision will later be run. Ensure that all the related files are also included in this folder.

2. Modify “dc_sync” 3. Modify “.synopsis_dc.setup” 4. Run Design Vision 5. Verify Synthesized

Output

In the downloaded kit, open the dc_sync file for modification in the synthesis folder. Change all of the input file names to match your .v or .vhd file names, change the “Current Design” input to your top level name, modify “set current design” to the top level name, and verify all path locations. Set the design library to the location of the libraries for the process being used and verify the location of the work directory. Run Design Vision using the command “design_vision-xg –f dc_syn” in the directory where your dc_sync file is located. Watch the terminal for possible errors and warnings as the device may not function if fabricated. Import “[filename].gate.v” file into ModelSim and re-run the simulations to verify the functionality of the synthesized file (this file can included timing and delay information).