1/12

ECE4116 – Digital Computer Design

Lab Experiment Duration: 3 hours

Introduction to VHDL Design on Quartus II and DE2 Board

Objective To learn how to create projects using Quartus II, design circuits and simulate them in the software.

To implement the designed circuits on the DE2 Board.

Introduction The Quartus II is a Computer Aided Design (CAD) system by Altera Corporation which includes

full support for all of the popular methods of entering a description of the desired circuit into a

CAD system. CAD software makes it easy to implement a desired logic circuit by using a

programmable logic device, such as a field-programmable gate array (FPGA) chip. The CAD flow

involves the following steps:

- Design Entry

The desired circuit is specified either by means of a schematic diagram, or by using a

hardware description language, such as VHDL or Verilog

- Synthesis

The entered design is synthesized into a circuit that consists of the logic elements (LEs)

provided in the FPGA chip

- Functional Simulation

The synthesized circuit is tested to verify its functional correctness; this simulation does

not take into account any timing issues

- Fitting

The CAD Fitter tool determines the placement of the LEs defined in the netlist into the LEs

in an actual FPGA chip; it also chooses routing wires in the chip to make the required

connections between specific LEs

- Timing Analysis

Propagation delays along the various paths in the fitted circuit are analyzed to provide an

indication of the expected performance of the circuit

- Timing Simulation

The fitted circuit is tested to verify both its functional correctness and timing

- Programming and Configuration

The designed circuit is implemented in a physical FPGA chip by programming the

configuration switches that configure the LEs and establish the required wiring connections

2/12

Figure 1 shows a typical FPGA CAD flow.

Figure 1

Each logic circuit, or subcircuit, being designed with Quartus II software is called a project. The

software works on one project at a time and keeps all information for that project in a single

directory in the file system. Once a circuit design is completed, it can be compiled and a

compilation report is produced. The Quartus II software provides a means to simulate the behavior

of the designed circuit for ascertaining its correctness. This step is crucial, before implementing

the circuit on the FPGA. A designed circuit can be simulated in two ways: functional and timing.

Functional simulation assumes that logic elements and interconnection

wires in the FPGA are perfect, thus causing no delay in propagation of signals through the circuit.

Timing simulation takes all propagation delays into account. Typically, functional simulation is

used to verify the functional correctness of a circuit as it is being designed.

The Altera DE2 board features the Cyclone® II 2C35 FPGA in a 672-pin package. All the components on

the board are connected to pins of this chip, allowing the user to control all aspects of the board’s

operation.

3/12

The specifications:

FPGA - Cyclone II EP2C35F672C6 FPGA

- EPCS16 serial configuration device

I/O Devices - Built-in USB Blaster for FPGA configuration

- 10/100 Ethernet, RS-232, Infrared port

- Video Out (VGA 10-bit DAC)

- Video In (NTSC/PAL/Multi-format)

- USB 2.0 (type A and type B)

- PS/2 mouse or keyboard port

- Line-in, Line-out, microphone-in

- (24-bit audio CODEC)

- Expansion headers (76 signal pins)

Memory - 8-MB SDRAM, 512-KB SRAM, 4-MB Flash

- SD memory card slot

Switches, LEDs, Displays, and Clocks - 18 toggle switches

- 4 debounced pushbutton switches

- 18 red LEDs, 9 green LEDs

- Eight 7-segment displays

- 16 x 2 LCD display

- 27-MHz and 50-MHz oscillators, external SMA clock input

The DE2 board can be used to implement circuits designed using the Quartus II CAD system.

4/12

Exercises

Exercise 1: Getting Started with the Switches

The DE2 board provides 18 toggle switches, called SW17−0, which can be used as inputs to a

circuit, and 18 red lights, called LEDR17−0, that can be used to display output values.

Figure 2

Steps:

1. Start the Quartus II program and create a new project using the New Project. Follow each step

of the wizard and select Cyclone II EP2C35F672C6 as the target chip, which is the FPGA

chip on the Altera DE2 board (see Figure 2).

2. Create a VHDL entity (a new VHDL file) and enter the following code:

LIBRARY ieee;

USE ieee.std_logic_1164.all;

- - Simple module that connects the SW switches to the LEDR lights

5/12

ENTITY part1 IS

PORT ( SW : IN STD LOGIC VECTOR(17 DOWNTO 0);

LEDR : OUT STD LOGIC VECTOR(17 DOWNTO 0)); - - red LEDs

END part1;

ARCHITECTURE Behavior OF part1 IS

BEGIN

LEDR <= SW;

END Behavior;

Save the file as part1.vhd in the project directory and include it in the project (see Figure 3).

Figure 3

6/12

Figure 4

Figure 5

3. Set the pin assignments by importing the file DE2_pin_assignments.csv. Select

AssignmentsImport Assignments, then, load the csv file. (see Figures 4)

4. Compile the project by selecting ProcessingStart Compilation.

5. Download the compiled circuit into the FPGA chip:

a) Connect the DE2 board to the computer using the USB cable. Turn the power on.

7/12

b) Select ToolsProgrammer to view the Programmer window (see Figure 5). Ensure the

hardware selected is USB-Blaster and the mode is JTAG.

(Note: If the USB-Blaster hardware option is not available, install/update the driver, which

is available in …\quartus\drivers)

c) Click “Start”.

6. Test the functionality of the circuit by toggling the switches and observing the LEDs.

Observe the behaviour of the LEDs when the switches are toggled.

Exercise 2: Multiplexers

Part (a) of Figure 6 shows a sum-of-products circuit that implements a 2-to-1 multiplexer with a

select input s. If s = 0 the multiplexer’s output m is equal to the input x, and if s = 1 the output is

equal to y. Part (b) shows the truth table for this multiplexer, and part (c) its circuit symbol.

Figure 6

The multiplexer can be described by the following VHDL statement:

m <= ( NOT (s) AND x ) OR (s AND y);

Figure 7 shows an 8-bit wide 2-to-1 multiplexer. The circuit has two 8-bit inputs X and Y and

produces the 8-bit output M. If s = 0 then M = X, while if s = 1 then M = Y.

Steps:

1. Create a new Quartus II project for the multiplexer circuit.

8/12

2. Write VHDL code to describe the 8-bit wide 2-to-1 multiplexer in the project. Use switch SW

17 on the DE2 board as the s input, switches SW7−0 as the X input and SW15−8 as the Y input.

Connect the SW switches to the red lights LEDR and connect the output M to the green lights

LEDG7−0.

3. Import the required pin assignments for the DE2 board as per step 3 of Exercise 1.

4. Compile the project.

5. Download the compiled circuit into the FPGA chip. Test the functionality of the 8-bit wide 2-

to-1 multiplexer by toggling the switches and observing the LEDs.

Figure 7

Task 1:

Describe the behaviour of the LEDs when the switches are toggled. Explain how the observed

behaviour verifies the functionality of the circuit.

9/12

Exercise 3: Latches and Flip-flops

Part A

Altera FPGAs include flip-flops that are available for implementing a user’s circuit. However,

storage elements can be created in an FPGA without using its dedicated flip-flops. Figure 8 depicts

a gated RS latch circuit. A style of VHDL code that uses logic expressions to describe this circuit

is given is as follows:

- - A gated RS latch

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY ls_latch IS

PORT (Clk, R, S : IN STD_LOGIC;

Q : OUT STD_LOGIC);

END ls_latch;

ARCHITECTURE Structural OF ls_latch IS

SIGNAL R_g, S_g, Qa, Qb : STD_LOGIC ;

ATTRIBUTE keep : boolean;

ATTRIBUTE keep of R_g, S_g, Qa, Qb : SIGNAL IS true;

BEGIN

R_g <= R AND Clk;

S_g <= S AND Clk;

Qa <= NOT (R_g OR Qb);

Qb <= NOT (S_g OR Qa);

Q <= Qa;

END Structural;

Figure 8

To preserve internal signals such as R-g and S_g in the implemented circuit, it is necessary to

include a compiler directive in the code. The directive keep is included by using a VHDL

ATTRIBUTE statement. It instructs the Quartus II compiler to use separate logic elements for each

of the signals R_g, S_g,Qa, and Qb. Compiling the code produces the circuit with four 4-input

lookup tables (LUTs) as shown in Figure 9.

10/12

Figure 9

Figure 10 shows the circuit for a gated D latch.

Figure 10

Steps:

1. Create another new Quartus II project to the gated D latch on the DE2 board. Use SW0 to drive

the D input and SW1 for the Clk input. Connect SW1−0 to LEDR1−0. Connect the Q to LEDG0

and �̅� LEDG1.

2. Recompile the project and download the compiled circuit onto the DE2 board. Test the

functionality of your circuit by toggling the D and Clk switches and observing the Q output.

Task 2:

Describe the Q output when D and Clk switches are toggled. Explain how the observed behaviour

verifies the functionality of the circuit.

11/12

Part B Figure 11 shows the circuit for a master-slave D flip-flop. To simulate the circuit, perform the

following steps.

Steps:

1. Create a new Quartus II project. Generate a VHDL file that instantiates two copies of your

gated D latch entity from Part A to implement the master-slave flip-flop. For the D latch, use

D, Clk and Q as the entity ports (instead of SW, LEDR, and LEDG).

2. Use SW0 to drive the D input of the flip-flop and SW1 as the Clock input. Connect SW1−0 to

LEDR1−0. Connect the Q to LEDG0 and �̅� LEDG1.

3. Compile your project and use the RTL Viewer to examine the D flip-flop circuit.

4. Download the circuit onto the DE2 board and test its functionality by toggling the D and Clock

switches and observing the Q output.

Figure 11

Task 3:

Describe the Q output when D and Clock switches are toggled. Explain how the observed

behaviour verifies the functionality of the circuit.

12/12

Report writing guidelines Your lab report must be typed and must contain the following:

Report cover page

Use the report cover page format in the FOE lab website. Download the template at

http://foe.mmu.edu.my/lab/sr.htm

Results and discussion Provide the VHDL codes for Exercises 2, 3A, and 3B. For each circuit, write a short discussion on

how its functionality is verified using the DE2 board.

Conclusion Conclude your report with a brief summary on the knowledge and skills that you have acquired

from this lab.

Exercises are adapted from Altera’s support documents for Quartus II and DE2 Boards.