ECE260B – CSE241A Winter 2007 Floorplanning, Partitioning ...vlsicad.ucsd.edu/courses/ece260b-w07/slides/ece260b-w07-floorplan... · ECE 260B – CSE 241A Floorplanning, Partitioning

ECE 260B CSE 241A Floorplanning, Partitioning and Placement Andrew B. Kahng, UCSD

ECE260B CSE241AWinter 2007

Floorplanning, Partitioning and Placement

Website: http://vlsicad.ucsd.edu/courses/ece260b-w07



Floorplanning


Floorplanning Input

Design netlist (required)

Area requirements (required)

Power requirements (required)

Timing constraints (required)

Physical partitioning information (required)

Die size vs. performance vs. schedule trade-off (required)

I/O placement (optional)

Macro placement information (optional)


Floorplanning Output

Die/block area

I/Os placed

Macros placed

Power grid designed

Power pre-routing

Standard cell placement areas

Design ready for standard cell placement


Floorplanning Output


Floorplan

data path

RAMstd cell

blocks

I/O pads

Routing channels

Blocks inside a pad frame

Routing inside, between blocks

Different-sized blocks more difficult than standard cells to place and route

BlocksHard, soft, semi-softRectangular, L-shaped, T-shaped, rectilinearCan rotate, mirror,

Courtesy K. Yang, UCLA


Size Estimation

Why we care: If area is too small: P&R will not finish or meet timing, will run too longSchedule and die size inversely relatedPerformance and die size have complex relationship

Rule of thumb (must correct for power, clock, etc.):- 3LM: Cell utilization 65 percent // what is utilization?- 3LM: Cell utilization 70 percent- 5LM: Cell utilization 75 percent- 6LM: Cell utilization 80 percent

Floorplan metricsLow interconnect density Cell util (standard cell area/standard cell row area)High interconnect density Net util (number of nets/standard cell area)

Die size

Physical DesignSchedulePerf

Die size


Channels

Channels end at block boundaries

Alternate channel definitions possible, depending on position of blocks

A

B C

channel 1

ch 2

ch 1 ch 2ch 3

A

B C

A

B C



Channel Intersection Graph

Nodes are channels, edges correspond to pairs of channels that touch

Channel graph shows paths between channels

Channel graph can be used to guide global routing

A BC

D

E



Slicing Floorplan Represented by Binary Tree

A slicing floorplan can be recursively cut in two without cutting any blocks

A slicing floorplan is guaranteed to have no wheels, therefore guaranteed to have a feasible order of routing for the channels

A slicing floorplan can be represented as a binary tree, with internal nodes representing slices in the floorplan and leaves representing blocks.


A

B

C

D

E

1

23

4

12 3

4CA B

D E


O-Tree

Partial ordering based on projection overlapping (with given physical locations)

Transforming into binary trees by pivoting, etc.

Coded in a node sequence given a tree traversal algorithm

E.g., OACBDEF for DFS

Condensed solution spaceB

C

D E

F


A

O


Sequence Pair

Based on layout partitions by non-overlapping ascending/descending staircases

Coded in two node sequences E.g., CEDFAB for descending staircases and ABCDEF for ascending staircases

Larger solution space, finer representation

B

C

D E

F

A




Partitioning


Hypergraphs in VLSI CAD

Circuit netlist represented by hypergraph



Hypergraph Partitioning in VLSI

Circuit netlist represented by hypergraphVariants

- directed/undirected hypergraphs- weighted/unweighted vertices, edges- constraints, objectives,

Human-designed instancesBenchmarks

- up to 4,000,000 vertices- sparse (vertex degree 4, hyperedge size 4)- small number of very large hyperedges

Efficiency, flexibility: KL-FM style preferred



Example: Partitioning of a Circuit


Input size: 48

Cut 1=4Size 1=15

Cut 2=4Size 2=16 Size 3=17


Hierarchical Partitioning

Levels of partitioning:System-level partitioning:Each sub-system can be designed as a single PCBBoard-level partitioning:Circuit assigned to a PCB is partitioned into sub-circuitseach fabricated as a VLSI chipChip-level partitioning:Circuit assigned to the chip is divided into manageable sub-circuitsNOTE: physically not necessary


Delay at Different Levels of Partitions

AB

C

PCB1

D

x

10x

20xPCB2


Delay at Different Levels of Partitions

etc


Context: Top-Down Placement

Speed- 6,000 cells/minute to final detailed placement- partitioning used only in top-down global placement- implied partitioning runtime: 1 second for 25,000 cells, < 30

seconds for 750,000 cells

Structure- tight balance constraint on total cell areas in partitions- widely varying cell areas- fixed terminals (pads, terminal propagation, etc.)


Fiduccia-Mattheyses (FM) Approach

Pass:start with all vertices free to move (unlocked)label each possible move with immediate change in cost that it causes (gain)iteratively select and execute a move with highest gain, lock the moving vertex (i.e., cannot move again during the pass), and update affected gainsbest solution seen during the pass is adopted as starting solution for next pass

FM:start with some initial solutionperform passes until a pass fails to improve solution quality


Cut During One Pass (Bipartitioning)

Moves

Cut


Multilevel Partitioning

RefinementClustering



Placement


VLSI Design Flow and Physical Design Stage

Global Placement

Detail Placement

Clock Tree Synthesisand Routing

Global Routing

Detail Routing

Power/Ground Stripes, Rings Routing

Extraction and Delay Calc.

Timing Verification

IO Pad Placement

Definitions:

Cell: a circuit component to be placed on the chip area. In placement, the functionality of the component is ignored.

Net: specifying a subset of terminals, to connect several cells.

Netlist: a set of nets which contains the connectivity information of the circuit.


Placement Problem

Input:A set of cells and their complete information (a cell library).Connectivity information between cells (netlist information).

Output:A set of locations on the chip; one location for each cell

Goal:The cells are placed to produce a routable chip that meets

timing and other constraints (e.g., low-power, noise, etc.)

Challenge:The number of cells in a design is very large (> 1 million)The timing constraints are very tight


Optimal Relative Order:

A B C


To spread ...

A B C


.. or not to spread

A B C


Place to the left

A B C


or to the right

A B C


Optimal Relative Order:

A B C

Without free space, the placement problem is dominated by order


Placement Problem

A bad placement A good placement


Global and Detailed Placement

In global placement, we decide the approximate locations for cells by placing cells in global bins.

In detailed placement, we make some local adjustment to obtain the final non-overlapping placement.

Global Placement

Detailed Placement


Placement Footprints:Standard Cell:

Data Path:

IP - Floorplanning


Placement Footprints:

Core

ControlIO

Reserved areas

Mixed Data Path &sea of gates:


Placement Footprints:

Perimeter IO

Area IO


Placement objectives are subject to user constraints / design style

Hierarchical Design Constraintspin locationpower rail reserved layers

Flat Design with Floorplan Constraints

Fixed Circuits

I/O Connections


Standard Cells


Standard Cells

Power connected by abutment, placed in sea-of-rowsRarely rotatedDRC clean in any combinationCircuit clean (I.e. no naked T-gates, no huge input capacitances)8,9,10+ tracks in heightMetal 1 only used (hopefully)Multi-height stdcells possibleBuffers: sizes, intrinsic delay steps, optimal repeater selectionSpecial clock buffers + gates (balanced P:N)Special metastability hardened flopsCap cells (metal1 used?)Gap fillers (metal1 used?)Tie-high, tie-low


UnconstrainedPlacement


Floor plannedPlacement


Traditional Placement Algorithms

Quadratic Placement

Simulated Annealing

Bi-Partitioning / Quadrisection

Force Directed Placement

Hybrid Algorithm

Cost Function

Netlis

t Gran

ularity

Layo

ut C

oars

enes

s


Quadratic Placement

Quadratic Placement

x4x4

x3x3x1x1

x2x2

Min Min [(x1[(x1--x3)x3)22 + (x1+ (x1--x2)x2)2 2 + (x2+ (x2--x4)x4)22] : ] : FF

F/F/x1 = 0; x1 = 0;

F/F/x2 = 0;x2 = 0;Ax = BAx = B

2 2 --11--1 2 1 2 x =

x = x1x1x2x2A = A = B = B =

x3x3x4x4


Analytical Placement

Get a solution with lots of overlaps

What do we do with the overlap?


Pros and Cons of QP

ProsVery fast analytical solutionCan handle large design sizesCan be used as an initial seed placement engine

ConsCan generate overlapped solutions: post-processing neededNot suitable for timing-driven placementNot suitable for simultaneous optimization of other aspects of physical design (clocks, crosstalk, )Gives trivial solutions without pads (and close to trivial with pads)


Simulated Annealing Placement

Initial Placement Improved through Initial Placement Improved through Swaps and MovesSwaps and Moves

Accept a Swap/Move if it improves Accept a Swap/Move if it improves costcost

Accept a Swap/Move that degrades Accept a Swap/Move that degrades cost under some probability cost under some probability conditionsconditions

TimeTime

CostCost


Pros and Cons of SA

Pros:Can Reach Globally Optimal Solution (given enough time)Open Cost Function.Can Optimize Simultaneously all Aspects of Physical DesignCan be Used for End Case Placement

Cons:Extremely Slow Process of Reaching a Good Solution


Bi-Partitioning / Quadrisection


Pros and Cons of Partitioning Based Placement

Pros:More Suitable to Timing Driven Placement since it is Move BasedNew Innovation (hMetis) in Partitioning Algorithms have made this Extremely FastOpen Cost FunctionMove Based means Simultaneous Optimization of all Design Aspects Possible

Cons:Not Well UnderstoodLots of indifferent movesMay not work well with some cost functions.


Cost Functions of Placement

Net-cut

Linear wirelength

Quadratic wirelength

Congestion

Timing

Coupling

Other performance related cost functions

Undiscovered: crossing

Algorithm

Cost Function

Netlis

t

Gran

ularity

Layo

ut C

oars

enes

s


Net-cut Cost for Global Placement

The netThe net--cut cost is defined as cut cost is defined as the number of external nets the number of external nets between different global binsbetween different global bins

Minimizing netMinimizing net--cut in global cut in global placement tends to put highly placement tends to put highly connected cells close to each connected cells close to each other.other.


Linear Wirelength Cost

The linear length of a net The linear length of a net between cell 1 and cell 2 isbetween cell 1 and cell 2 is

l12 = l12 = |x1|x1--x2| +|y1x2| +|y1--y2|y2|

The linear The linear wirelengthwirelength cost is cost is the summation of the linear the summation of the linear length of all nets.length of all nets.

(x1,y1)(x1,y1)

(x2,y2)(x2,y2)

11

22


Quadratic Wirelength Cost

The quadratic length of a net The quadratic length of a net between cell 1 and cell 2 isbetween cell 1 and cell 2 is

l12 = l12 = (x1(x1--x2)2 +(y1x2)2 +(y1--y2)2y2)2

The quadratic The quadratic wirelengthwirelength cost cost is the summation of the is the summation of the quadratic length of all nets.quadratic length of all nets.

(x1,y1)(x1,y1)

(x2,y2)(x2,y2)

11

22


Timing Cost

Delay of the circuit is defined as the longest delay among all possible paths from primary inputs to primary outputs.

Interconnection delay becomes more and more important in deep sub-micron regime.

Critical Path


Timing Analysis

How do we get the delay numbers on the gate/interconnect?

5 5 5

4 4 4

2

LATCH

LATCH

3 2 1 1

2 1 3 2

1

2222

1919


Approaches

BudgetingIn accurate informationFast

Path AnalysisMost accurate informationVery slow

Path analysis with infrequent path substitutionSomewhere in between


Timing Metrics

How do we assess the change in a delay due to a potential move during physical design?

Whether it is channel routing or area routing, the problem is the same

translate geometrical change into delay change


Other costs: Coupling Cost

Hard to model during placement

Can run a global router in the middle of placement

Even at the global routing level it is hard to model it

Avoid it


Coupling Solutions

Once we have some metrics for coupling, we can calculate sensitivities, and optimize the physical design...

Spacing

Extra space

Segregation

Noisy region

Quiet region

Shielding

Grounded Shields


Other Performance Costs

Power usage of the chip.Weighted netsDual voltages (severe constraint on placement)

Very little known about these cost functions and their interaction with other cost functions

Fundamental research is needed to shed some light on the structure of them


Placement ReferencesC. J. Alpert, T. Chan, D. J.-H. Huang, I. Markov, and K. Yan, Quadratic Placement Revisited,Proc. 34th IEEE/ACM Design Automation Conference, 1997, pp. 752-757

C. J. Alpert, J.-H Huang, and A. B. Kahng, Multilevel Circuit Partitioning, Proc. 34th IEEE/ACM Design Automation Conference, 1997, pp. 530-533

U. Brenner, and A. Rohe, An Effective Congestion Driven Placement Framework, International Symposium on Physical Design 2002, pp. 6-11

A. E. Caldwell, A. B. Kahng, and I.L. Markov, Can Recursive Bisection Alone Produce Routable Placements,Proc. 37th IEEE/ACM Design Automation Conference, 2000, pp 477-482

M.A. Breuer, Min-Cut Placement, J. Design Automation and Fault Tolerant Computing, I(4), 1997, pp 343-362

J. Vygen, Algorithms for Large-Scale Flat Placement, Proc. 34th IEEE/ACM Design Automation Conference, 1988,pp 746-751

H. Eisenmann and F. M. Johannes, Generic Global Placement and Floorplanning, Proc. 35th IEEE/ACM Design Automation Conference, 1998, pp. 269-274

S.-L. Ou and M. Pedram, Timing Driven Placement Based on Partitioning with Dynamic Cut-Net Control, Proc. 37th IEEE/ACM Design Automation Conference, 2000, pp. 472-476

C.M. Fiduccia and R.M. Mattheyses, A linear time heuristic for improving network partitions, Proc. ACM/IEEE Design Automation Conference. (1982) pp. 175 - 181.


Reading Assignment (Posted on the web)

C.M. Fiduccia and R.M. Mattheyses, A linear time heuristic for improving network partitions, Proc. ACM/IEEE Design Automation Conference. (1982) pp. 175 - 181.

A. E. Caldwell, A. B. Kahng and I. L. Markov. Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning. Proc. Workshop on Algorithm Engineering and Experimentation (ALENEX), January, 1999

(Optional): C. J. Alpert and A. B. Kahng, "Recent Directions in Netlist Partitioning: A Survey, Integration: The VLSI Journal 19 (1995), pp. 1-81.


Homework Friday 1/19

If I model one wire segment with R, C = Rw, Cw by two segments in series, each with R, C = Rw/2, Cw/2, how does Elmore delay change?

What are the differences between Kernighan-Lin and Fiduccia-Mattheyses?

ECE260B CSE241AWinter 2007Floorplanning, Partitioning and PlacementECE260B CSE241AWinter 2007FloorplanningFloorplanning InputFloorplanning OutputFloorplanning OutputFloorplanSize EstimationChannelsChannel Intersection GraphSlicing Floorplan Represented by Binary TreeO-TreeSequence PairECE260B CSE241AWinter 2007PartitioningHypergraphs in VLSI CADHypergraph Partitioning in VLSIHypergraph Partitioning in VLSIExample: Partitioning of a CircuitHierarchical PartitioningDelay at Different Levels of PartitionsDelay at Different Levels of PartitionsDelay at Different Levels of PartitionsContext: Top-Down PlacementFiduccia-Mattheyses (FM) ApproachCut During One Pass (Bipartitioning)Multilevel PartitioningECE260B CSE241AWinter 2007PlacementVLSI Design Flow and Physical Design StagePlacement ProblemOptimal Relative Order:To spread ..... or not to spreadPlace to the left or to the rightOptimal Relative Order:Placement ProblemGlobal and Detailed PlacementPlacement Footprints:Placement Footprints:Placement Footprints:Placement objectives are subject to user constraints / design styleStandard CellsStandard CellsTraditional Placement AlgorithmsQuadratic PlacementAnalytical PlacementPros and Cons of QPSimulated Annealing PlacementPros and Cons of SABi-Partitioning / QuadrisectionPros and Cons of Partitioning Based PlacementCost Functions of PlacementNet-cut Cost for Global PlacementLinear Wirelength CostQuadratic Wirelength CostTiming CostTiming AnalysisApproachesTiming MetricsOther costs: Coupling CostCoupling SolutionsOther Performance CostsPlacement ReferencesReading Assignment (Posted on the web)Homework Friday 1/19

Documents

ECE260B – CSE241A Winter 2007 Floorplanning, Partitioning ...vlsicad.ucsd.edu/courses/ece260b-w07/slides/ece260b-w07-floorplan... · ECE 260B – CSE 241A Floorplanning, Partitioning