EE1411

ECE 667 - Synthesis and Verification

ECE 697B (667)ECE 697B (667)Fall 2004Fall 2004

Synthesis and Verificationof Digital Circuits

Design Styles and Methodologies

Slides adopted (with permission) from A. Kuehlmann, UC Berkeley 2003Slides adopted (with permission) from A. Kuehlmann, UC Berkeley 2003

EE1412

ECE 667 - Synthesis and Verification

Implementation ChoicesImplementation Choices

Custom

Standard CellsCompiled Cells Macro Cells

Cell-based

Pre-diffused(Gate Arrays)

Pre-wired(FPGA's)

Array-based

Semicustom

Digital Circuit Implementation Approaches

EE1413

ECE 667 - Synthesis and Verification

The Custom Approach The Custom Approach

Intel 4004

Courtesy Intel

EE1414

ECE 667 - Synthesis and Verification

Transition to Automation and Regular StructuresTransition to Automation and Regular Structures

Intel 4004 (‘71)Intel 4004 (‘71)Intel 8080Intel 8080 Intel 8085Intel 8085

Intel 8286Intel 8286 Intel 8486Intel 8486Courtesy Intel

EE1415

ECE 667 - Synthesis and Verification

Cell-based Design (or standard cells)Cell-based Design (or standard cells)

Routing channel requirements arereduced by presenceof more interconnectlayers

Functionalmodule(RAM,multiplier,…)

Routingchannel

Logic cellFeedthrough cellR

ow

s o

f ce

lls

EE1416

ECE 667 - Synthesis and Verification

Standard Cell — ExampleStandard Cell — Example

[Brodersen92]

EE1417

ECE 667 - Synthesis and Verification

Standard Cell – The New GenerationStandard Cell – The New Generation

Cell-structurehidden underinterconnect layers

EE1418

ECE 667 - Synthesis and Verification

Standard Cell - ExampleStandard Cell - Example

3-input NAND cell(from ST Microelectronics):C = Load capacitanceT = input rise/fall time

EE1419

ECE 667 - Synthesis and Verification

Automatic Cell GenerationAutomatic Cell Generation

Courtesy Acadabra

Initial transistorgeometries

Placedtransistors

Routedcell

Compactedcell

Finishedcell

EE14110

ECE 667 - Synthesis and Verification

A Historical Perspective: the PLAA Historical Perspective: the PLA

x0 x1 x2

ANDplane

x0x1

x2

Product terms

ORplane

f0 f1

EE14111

ECE 667 - Synthesis and Verification

Two-Level LogicTwo-Level Logic

Inverting format (NOR-NOR) more effective

Every logic function can beexpressed in sum-of-productsformat (AND-OR)

minterm

EE14112

ECE 667 - Synthesis and Verification

Programmable Logic ArrayProgrammable Logic Array

GND GND GND GND

GND

GND

GND

VDD

VDD

X0X0 X1 f0 f1X1 X2X2

AND-plane OR-plane

Pseudo-NMOS PLA

EE14113

ECE 667 - Synthesis and Verification

Dynamic PLADynamic PLA

GND

GNDVDD

VDD

X0X0 X1 f0 f1X1 X2X2

ANDf

ANDf

ORf

ORf

AND-plane OR-plane

EE14114

ECE 667 - Synthesis and Verification

PLA Layout – Exploiting RegularityPLA Layout – Exploiting Regularity

f0 f1x0 x0 x1 x1 x2 x2

Pull-up devices Pull-up devices

VDD GNDAnd-Plane Or-Plane

EE14115

ECE 667 - Synthesis and Verification

Breathing Some New Life in PLAsBreathing Some New Life in PLAsRiver PLAs A cascade of multiple-output PLAs. Adjacent PLAs are connected via river routing.

PRE-CHARGE

PR

E-

CH

AR

GE

PRE-CHARGE

PR

E-C

HA

RG

E

BUFFER

BUFFER

BU

FF

ER

BU

FF

ER

PRE-CHARGE

PR

E-C

HA

RG

E

BUFFER

BU

FF

ER

PRE-CHARGE

PR

E-

CH

AR

GE

BUFFERB

UF

FE

R

• No placement and routing needed. • Output buffers and the input buffers

of the next stage are shared.

Courtesy B. Brayton

EE14116

ECE 667 - Synthesis and Verification

Experimental ResultsExperimental Results

Layout of C2670

Network of PLAs, 4 layers OTC

River PLA,2 layers no additional routing

Standard cell, 2 layers channel routing

Standard cell,3 layers OTC

0.2

0.6

1

1.4

0 2 4 6 area

dela

y

SC N PLA R PLA

Area: RPLAs (2 layers) 1.23 SCs (3 layers) - 1.00, NPLAs (4 layers) 1.31 DelayRPLAs 1.04SCs 1.00 NPLAs 1.09 Synthesis time: for RPLA , synthesis time equals design time; SCs and NPLAs still need P&R.

Also: RPLAs are regular and predictable

EE14117

ECE 667 - Synthesis and Verification

MacroModulesMacroModules

25632 (or 8192 bit) SRAMGenerated by hard-macro module generator

EE14118

ECE 667 - Synthesis and Verification

““Soft” MacroModulesSoft” MacroModules

Synopsys DesignCompiler

EE14119

ECE 667 - Synthesis and Verification

““Intellectual Property”Intellectual Property”

A Protocol Processor for Wireless

EE14120

ECE 667 - Synthesis and Verification

Semicustom Design FlowSemicustom Design Flow

HDLHDL

Logic SynthesisLogic Synthesis

FloorplanningFloorplanning

PlacementPlacement

RoutingRouting

Tape-out

Circuit ExtractionCircuit Extraction

Pre-Layout Simulation

Pre-Layout Simulation

Post-Layout Simulation

Post-Layout Simulation

StructuralStructural

PhysicalPhysical

BehavioralBehavioralDesign Capture

Des

ign

Iter

atio

nD

esig

n It

erat

ion

EE14121

ECE 667 - Synthesis and Verification

The “Design Closure” ProblemThe “Design Closure” Problem

Courtesy Synopsys

Iterative Removal of Timing Violations (white lines)

EE14122

ECE 667 - Synthesis and Verification

Integrating Synthesis with Integrating Synthesis with Physical DesignPhysical Design

Physical SynthesisPhysical Synthesis

RTL (Timing) Constraints

Place-and-RouteOptimization

Place-and-RouteOptimization

Artwork

Netlist with Place-and-Route Info

MacromodulesFixed netlists