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ECE 555 Digital Circuits & Components
ECE555ECE555Lecture 8/9Lecture 8/9
Nam Sung KimUniversity of Wisconsin – Madison
Dept. of Electrical & Computer Engineering
1
ECE 555 Digital Circuits & Components
OutlineOutline Adder
• Carry Ripple
• Manchester Carry
• Carry Bypass (or Skip)
• Carry Select
• Paralle Prefix Brent-Kung Kogge-Stone
• Delay and Power Comparisons
2
ECE 555 Digital Circuits & Components
Single-Bit AdditionSingle-Bit Addition
3
Half Adder Full Adder
A B Cout S
0 0
0 1
1 0
1 1
A B C Cout S
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
A B
S
Cout
A B
C
S
Cout
out
S
C
out
S
C
ECE 555 Digital Circuits & Components
Single-Bit AdditionSingle-Bit Addition
4
Half Adder Full Adder
A B Cout S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
A B C Cout S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
A B
S
Cout
A B
C
S
Cout
out
S A B
C A B
out ( , , )
S A B C
C MAJ A B C
ECE 555 Digital Circuits & Components
PGKPGK For a full adder, define what happens to carries
• Generate: Cout = 1 independent of C G =
• Propagate: Cout = C P =
• Kill: Cout = 0 independent of C K =
5
ECE 555 Digital Circuits & Components
PGKPGK For a full adder, define what happens to carries
• Generate: Cout = 1 independent of C G = A • B
• Propagate: Cout = C P = A B
• Kill: Cout = 0 independent of C K = ~A • ~B
• Co(G,P) = G+PCi
• S(G,P) = P Ci
6
ECE 555 Digital Circuits & Components
Full Adder Design IFull Adder Design I Brute force implementation from eqns
• S=ABCi+ABCi+ABCi+ABCi = Ci (AB+AB)+Ci (AB+AB)
• Co=AB+BCi+ACi=(AB+BCi+Aci)
7
ABC
S
Cout
MA
J
ABC
A
B BB
A
CS
C
CC
B BB
A A
A B
C
B
A
CBA A B C
Cout
C
A
A
BB
ECE 555 Digital Circuits & Components
Full Adder Design IIFull Adder Design II Factor S in terms of Co
• S = ABCi + (A + B + Ci)(~Co)
Critical path is usually Ci to Co in ripple adder
8
B
B B
B B
B
B
B
A
A
A
A
A
A A
A
Ci
Ci
Ci
Ci
Ci
!Co !S
4 4
4 4
4
8
888
8
2 2 2
3
3
3
6
6
6
444
4
2
Co S
ECE 555 Digital Circuits & Components
Full Adder Design IIIFull Adder Design III
9
B !B
Identical Delays for Carry and Sum
P !P
Signal set-up
B
A
!B
PA
Carry generation
Sum generation
Cin
!P
!Cout
!P
P
Cin
P
A
!Cout
P
!P
SCin Cin
ECE 555 Digital Circuits & Components
Carry-Ripple AdderCarry-Ripple Adder Simplest design: cascade full adders
• Critical path goes from Ci to Co
• Design full adder to have fast carry delay
• Worst case delay linear with the number of bits td = O(N)
tadder = (N-1)tcarry + tsum
10
CinCout
B1A1B2A2B3A3B4A4
S1S2S3S4
C1C2C3
ECE 555 Digital Circuits & Components
Inversion PropertyInversion Property
11
A B
S
CoCi FA
A B
S
CoCi FA
S A B Ci S A B Ci
=
Co A B Ci Co A B Ci
=
ECE 555 Digital Circuits & Components
Mirror AdderMirror Adder Critical path passes through majority gate
• Built from minority + inverter• Eliminate inverter and use inverting full adder
12
Cout Cin
B1A1B2A2B3A3B4A4
S1S2S3S4
C1C2C3
ECE 555 Digital Circuits & Components
Mirror Adder CellMirror Adder Cell
13
B
B B
B B
B
B
B
A
A
A
A
A
A A
A
Ci
Ci
Ci
Ci
Ci
!Co !S
4 4
4 4
4
8
888
8
2 2 2
3
3
3
6
6
6
444
4
2
ECE 555 Digital Circuits & Components
Fast Carry Chain DesignFast Carry Chain Design
14
The key to fast addition is a low latency carry network
What matters is whether in a given position a carry is• generated Gi = Ai & Bi = AiBi
• propagated Pi = Ai Bi (sometimes use Ai | Bi)
• annihilated (killed) Ki = !Ai & !Bi
Giving a carry recurrence of
Ci+1 = Gi | PiCiC1 =
C2 =
C3 =
C4 =
ECE 555 Digital Circuits & Components
Fast Carry Chain DesignFast Carry Chain Design
15
The key to fast addition is a low latency carry network
What matters is whether in a given position a carry is• generated Gi = Ai & Bi = AiBi
• propagated Pi = Ai Bi (sometimes use Ai | Bi)
• annihilated (killed) Ki = !Ai & !Bi
Giving a carry recurrence of
Ci+1 = Gi | PiCiC1 = G0 | P0C0
C2 = G1 | P1G0 | P1P0 C0
C3 = G2 | P2G1 | P2P1G0 | P2P1P0 C0
C4 = G3 | P3G2 | P3P2G1 | P3P2P1G0 | P3P2P1P0 C0
ECE 555 Digital Circuits & Components
Manchester Carry ChainManchester Carry Chain
16
Switches controlled by Gi and Pi
Total delay of• time to form the switch control signals Gi and Pi
• setup time for the switches
• signal propagation delay through N switches in the worst case
Gi Pi
!Ci!Ci+1
clk
ECE 555 Digital Circuits & Components
4-bit Sliced MCC Adder4-bit Sliced MCC Adder
17
G P
!C0
clk
G PG PG P
& & & &
A0 B0A1 B1A2 B2A3 B3
S0S1S2S3
!C1!C2!C3
!C4
ECE 555 Digital Circuits & Components
Domino Manchester Carry Chain CircuitDomino Manchester Carry Chain Circuit
18
Ci,0G0
clk
clkP0P1P2P3
G1G2G3
Ci,41 2 3 4
5
6
3 3 3 3 3
1
2
2
3
3
4
4
5
!(G0 | P0 Ci,0)
!(G1 | P1G0 | P1P0 Ci,0)
!(G2 | P2G1 | P2P1G0 | P2P1P0 Ci,0)
!(G3 | P3G2 | P3P2G1 | P3P2P1G0 | P3P2P1P0 Ci,0)
ECE 555 Digital Circuits & Components
Carry-Skip (Carry-Bypass) AdderCarry-Skip (Carry-Bypass) Adder
19
If (P0 & P1 & P2 & P3 = 1) then Co,3 = Ci,0 otherwise the block itself kills or generates the carry internally
A0 B0
S0
Ci,0FA
A1 B1
S1
FA
A2 B2
S2
FA
A3 B3
S3
FACo,3
Co,3
BP = P0 P1 P2 P3 “Block Propagate”
ECE 555 Digital Circuits & Components
Carry-Skip Chain ImplementationCarry-Skip Chain Implementation
20
BPblock carry-in
block carry-outcarry-out
Cin
G0
P0P1P2P3
G1G2G3
!Cout
BP
ECE 555 Digital Circuits & Components
4-bit Block Carry-Skip Adder4-bit Block Carry-Skip Adder
21
Worst-case delay carry from bit 0 to bit 15 = carry generated in bit 0, ripples through bits 1, 2, and 3, skips the middle two groups (B is the group size in bits), ripples in the last group from bit 12 to bit 15
Ci,0
Sum
CarryPropagation
Setup
Sum
CarryPropagation
Setup
Sum
CarryPropagation
Setup
Sum
CarryPropagation
Setup
bits 0 to 3bits 4 to 7bits 8 to 11bits 12 to 15
Tadd = tsetup + B tcarry + ((N/B) -1) tskip +(B -1)tcarry + tsum
ECE 555 Digital Circuits & Components
Carry Select AdderCarry Select Adder
22
4-b Setup
“0” carry propagation
“1” carry propagation 1
0
multiplexer CinCout
Sum generation
P’s G’s
C’s
Precompute the carry out of each block for both carry_in = 0 and carry_in = 1 (can be done for all blocks in parallel) and then select the correct one
S’s
ECE 555 Digital Circuits & Components
Carry Select Adder: Critical Path Carry Select Adder: Critical Path
23
Setup
“0” carry
“1” carry 1
0
muxCin
Sum gen
P’s G’s
C’s
S’s
A’s B’s
Setup
“0” carry
“1” carry
mux
Sum gen
P’s G’s
C’s
S’s
A’s B’s
Setup
“0” carry
“1” carry
mux
Sum gen
P’s G’s
C’s
S’s
A’s B’s
Setup
“0” carry
“1” carry
muxCout
Sum gen
P’s G’s
C’s
S’s
A’s B’sbits 0 to 3bits 4 to 7bits 8 to 1bits 12 to 15
ECE 555 Digital Circuits & Components
Carry Select Adder: Critical Path Carry Select Adder: Critical Path
24
Setup
“0” carry
“1” carry 1
0
muxCin
Sum gen
P’s G’s
C’s
S’s
A’s B’s
Setup
“0” carry
“1” carry
mux
Sum gen
P’s G’s
C’s
S’s
A’s B’s
Setup
“0” carry
“1” carry
mux
Sum gen
P’s G’s
C’s
S’s
A’s B’s
Setup
“0” carry
“1” carry
muxCout
Sum gen
P’s G’s
C’s
S’s
A’s B’sbits 0 to 3bits 4 to 7bits 8 to 1bits 12 to 15
1
+4
+1+1+1+1
Tadd = tsetup + B tcarry + N/B tmux + tsum
ECE 555 Digital Circuits & Components
Square Root Carry Select Adder Square Root Carry Select Adder
25
Setup
“0” carry
“1” carry 1
0
muxCin
Sum gen
P’sG’s
C’s
S’s
A’s B’sA’s B’s
S’s
Setup
“0” carry
“1” carry
mux
Sum gen
P’s G’s
C’s
A’s B’s
Setup
“0” carry
“1” carry
muxCout
Sum gen
P’s G’s
C’s
S’s
A’s B’sbits 0 to 1bits 2 to 4bits 5 to 8bits 9 to 13
Setup
mux
Sum gen
P’s G’s
C’s
S’s
“1” carry
“0” carry
Setup
“0” carry
“1” carry
mux
Sum gen
P’s G’s
C’s
A’s B’sbits 14 to 19
S’s
ECE 555 Digital Circuits & Components
Square Root Carry Select Adder Square Root Carry Select Adder
26
Setup
“0” carry
“1” carry 1
0
muxCin
Sum gen
P’sG’s
C’s
S’s
A’s B’sA’s B’s
S’s
Setup
“0” carry
“1” carry
mux
Sum gen
P’s G’s
C’s
A’s B’s
Setup
“0” carry
“1” carry
muxCout
Sum gen
P’s G’s
C’s
S’s
A’s B’sbits 0 to 1bits 2 to 4bits 5 to 8bits 9 to 13
Setup
mux
Sum gen
P’s G’s
C’s
S’s
“1” carry
“0” carry
Setup
“0” carry
“1” carry
mux
Sum gen
P’s G’s
C’s
A’s B’sbits 14 to 19
S’s
Tadd = tsetup + 2 tcarry + √N tmux + tsum
1
+2
+1+1+1+1+1
+1
+3+4+5+6
ECE 555 Digital Circuits & Components
Adder Delays - Comparison Adder Delays - Comparison
27
Square root select
Linear select
Ripple adder
20 40N
t p(in
un
it de
lays
)
600
10
0
20
30
40
50
ECE 555 Digital Circuits & Components
Parallel Prefix Adders (PPAs)Parallel Prefix Adders (PPAs)
28
Define carry operator on (G,P) signal pairs
• is associative, i.e.,
[(g’’’,p’’’) (g’’,p’’)] (g’,p’) = (g’’’,p’’’) [(g’’,p’’) (g’,p’)]
(G’’,P’’) (G’,P’)
(G,P)
where G = G’’ P’’G’ P = P’’P’
ECE 555 Digital Circuits & Components
Parallel Prefix Adders (PPAs)Parallel Prefix Adders (PPAs)
29
(Gi:j,Pi:j) = (Gi:k+Pi:k∙Gk-1:j, Pi:k∙Pk-1:j)
i:j
i:j
i:k k-1:j
i:j
i:k k-1:j
i:j
Gi:k
Pk-1:j
Gk-1:j
Gi:j
Pi:j
Pi:k
Gi:k
Gk-1:j
Gi:j Gi:j
Pi:j
Gi:j
Pi:j
Pi:k
Black cell Gray cell Buffer
ECE 555 Digital Circuits & Components
Parallel Prefix Adders (PPAs)Parallel Prefix Adders (PPAs)
30
Co,0 = G0+P0Ci,0
Co,1 = G1+P1Co,0 = G1 +P1(G0+P0Ci,0)
= G1 +P1G0+P1P0Ci,0
= [G1+ P1G0]+[P1P0 ]Ci,0 = G1:0+P1:0 Ci,0
Co,2 = G2 +P2Co,1
Co,3 = G3 +P3Co,2 = G3 +P3(G2 +P2Co,1)
= G3 +P3G2 +P3P2Co,1)
= [G3 +P3G2 ]+ [P3P2]Co,1
= G3:2+P3:2 Co,1
= G3:2+P3:2 (G1:0+P1:0 Ci,0)
= [G3:2+P3:2 G1:0]+[P3:2 P1:0 ]Ci,0) = G3:0+P3:0Ci,0
ECE 555 Digital Circuits & Components
PPA General StructurePPA General Structure
Measures to consider• number of cells
• tree cell depth (time)
• tree cell area
• cell fan-in and fan-out
• max wiring length
• wiring congestion
• delay path variation (glitching)
31
Pi, Gi logic (1 unit delay)
Si logic (1 unit delay)
Ci parallel prefix logic tree (1 unit delay per level)
Given P and G terms for each bit position, computing all the carries is equal to finding all the prefixes in parallel
(G0,P0) ■ (G1,P1) ■ (G2,P2) ■ … ■ (GN-2,PN-2) ■ (GN-1,PN-1)
Since is associative, we can group them in any order • but note that it is not commutative
ECE 555 Digital Circuits & Components
Brent-Kung PPABrent-Kung PPA
32
Par
alle
l Pre
fix C
ompu
tatio
n
G0
P0
G1
P1
G2
p2
G3
P3
G4
P4
G5
P5
G6
P6
G7
P7
G8
P8
G9
p9
G10
P10
G11
p11
G12
P12
G13
p13
G14
p14
G15
p15
C1C2C3C4C5C6C7C8C9C10C11C12C13C14C15C16
Cin
T =
log 2
NT
= lo
g 2N
- 2
A =
2lo
g 2N
A = N/2
ECE 555 Digital Circuits & Components
Brent-Kung PPABrent-Kung PPA
33
Par
alle
l Pre
fix C
ompu
tatio
n
G0
P0
G1
P1
G2
p2
G3
P3
G4
P4
G5
P5
G6
P6
G7
P7
G8
P8
G9
p9
G10
P10
G11
p11
G12
P12
G13
p13
G14
p14
G15
p15
C1C2C3C4C5C6C7C8C9C10C11C12C13C14C15C16
Cin
T =
log 2
NT
= lo
g 2N
- 2
A =
2lo
g 2N
A = N/2
ECE 555 Digital Circuits & Components
Kogge-Stone PPF AdderKogge-Stone PPF Adder
34
Par
alle
l Pre
fix C
ompu
tatio
n
G0
P0
G1
P1
G2
P2
G3
P3
G4
P4
G5
P5
G6
P6
G7
P7
G8
P8
G9
P9
G10
P10
G11
P11
G12
P12
G13
P13
G14
P14
G15
P15
C1C2C3C4C5C6C7C8C9C10C11C12C13C14C15C16
Cin
T =
log 2
N
A =
log 2
N
A = N
Tadd = tsetup + log2N t + tsum
ECE 555 Digital Circuits & Components
More Adder ComparisonsMore Adder Comparisons
35
0
10
20
30
40
50
60
70
8 bits 16 bits 32 bits 48 bits 64 bits
RCA
CSkA
KS PPA
ECE 555 Digital Circuits & Components
Adder Speed ComparisonsAdder Speed Comparisons
36
10
20
30
40
50
60
70
16 bits 32 bits 64 bits
RCA
MCC
CCSkA
CCSlA
B&K
ECE 555 Digital Circuits & Components
Adder Average Power ComparisonsAdder Average Power Comparisons
37
0
5
10
15
20
25
30
35
16 bits 32 bits 64 bits
RCA
MCC
CCSkA
CCSlA
B&K
ECE 555 Digital Circuits & Components
PDP of Adder ComparisonsPDP of Adder Comparisons
38
0
20
40
60
80
100
8 bits 16 bits 32 bits 48 bits 64 bits
RCA
MCCA
CCSkA
CCSlA
BKA