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1

ECE 545—Digital System Design with VHDLLecture 1A

Digital Logic RefresherPart A – Combinational Logic Building Blocks

Cont.

Problem 20

What is a size of ROM with a 4-bit address input and an 8-bit data output?

What is a size of ROM with an m-bit address input and an n-bit data output?

2

3

Read Only Memory (ROM)

ROM

ADDR DOUTm n

4

Implementing Arbitrary Combinational LogicUsing ROM

X5 X4 X3 X2 X1 Y0 0 0 0 0 00 0 0 0 1 10 0 0 1 0 00 0 0 1 1 00 0 1 0 0 10 0 1 0 1 10 0 1 1 0 00 0 1 1 1 00 1 0 0 0 10 1 0 0 1 00 1 0 1 0 00 1 0 1 1 10 1 1 0 0 10 1 1 0 1 10 1 1 1 0 10 1 1 1 1 11 0 0 0 0 01 0 0 0 1 01 0 0 1 0 01 0 0 1 1 01 0 1 0 0 01 0 1 0 1 01 0 1 1 0 01 0 1 1 1 11 1 0 0 0 01 1 0 0 1 11 1 0 1 0 01 1 0 1 1 11 1 1 0 0 01 1 1 0 1 11 1 1 1 0 01 1 1 1 1 0

ROM

ADDR DOUT5 1

X4 X3 X2 X1 X0 Y

X Y

Problem 21

Show how to implement a 3x3 squarer,

implementing equation y = x2,

using ROM (diagram + contents of ROM).

5

Problem 22

Show how to implement Full Adder using ROM(diagram + contents of ROM)

6

2

7

Full-Adder

x

ycout

sFA x + y + cin = ( cout s )2

2 1

x y cout s

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

1

0

1

1

1

0

1

1

0

1

0

0

1

cin

0

1

0

1

0

1

0

1

cin x

y

cin

s

cout

Problem 23

What is a function of a tri-state buffer?

8

9

(b) Equivalent circuit

(c) Truth table

x f

e

(a) A tri-state buffer

0 0 1 1

0 1 0 1

Z Z 0 1

f e x

x f

e = 0

e = 1x f

Tri-state Buffer

10

x f

e

(b)

x f

e

(a)

x f

e

(c)

x f

e

(d)

Four types of Tri-state Buffers

Quotient and remainder

Given integers a and n, n>0

$! q, r Î Z such that

a = q× n + r and 0 £ r < n

q – quotient

r – remainder(of a divided by n)

q = an = a div n

r = a - q× n = a – an × n =

= amod n11

Rules of addition, subtraction and multiplicationmodulo n

a + bmod n = ((amod n) + (bmod n)) mod n

a - bmod n = ((amod n) - (bmod n)) mod n

a × bmod n = ((amod n) × (bmod n)) mod n

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3

Problem 24

Explain how to perform the following operationsA. Z = X+Y mod 24

B. Z = X*Y mod 24

using a 4-bit adder with carry in (cin) and carry out (cout), and a 4x4 multiplier, respectively, where X, Y, and Z are 4-bit variables.

13 14

Z = X+Y mod 24

15

Z = X*Y mod 24

16

Explain how to perform the following operation using simple arithmetic and logic circuits:

Y = (X*(2X + 1)) mod 24,where X and Y are 4-bit variables.

Problem 25

17

Y = (X*(2X + 1)) mod 24

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4

Problem 26

What is a difference between an adder, half-adder, and full-adder?

1920

Single-Bit Adders

• Half-adder• Adds two binary (i.e. 1-bit) inputs A and B

• Produces a sum and carryout

• Problem: Cannot use it alone to build larger adders• Full-adder

• Adds three binary (i.e. 1-bit) inputs A, B, and carryin• Like half-adder, produces a sum and carryout

• Allows building M-bit adders (M > 1)• Simple technique

• Connect Cout of one adder to Cin of the next• These are called ripple-carry adders

21

Half-Adder

x

y

c

sHA x + y = ( c s )2

2 1

x y c s

0

0

1

1

0

1

0

1

0

0

0

1

0

1

1

0

22

Full-Adder

x

ycout

sFA x + y + cin = ( cout s )2

2 1

cin

x y cout s

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

0

1

0

1

1

1

0

1

1

0

1

0

0

1

0

1

0

1

0

1

0

1

cin x

y

cin

s

cout

23

16-bit Unsigned Adder

16 16

X Y

16

CinCoutS+

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Multi-Bit Ripple-Carry AdderA 16-bit ripple-carry adder is composed of 16 (1-bit) full adders

Inputs: 16-bit A, 16-bit B, 1-bit carry in (set to zero in the figure below)Outputs: 16-bit sum S, 1-bit carry out

Other multi-bit adder structures can be studied in ECE 645—Computer Arithmetic

Called a ripple-carry adder because carry ripples from one full-adder to the next. Critical path is 16 full-adders.

5

Problem 27

Show how to implement Full Adder using8-to-1 multiplexers only

x y cout s

000

011

11

001

100

11

000

101

11

011

010

01

010

101

01

cin

25 26

Problem 27

Show how to implement Full Adder usingtwo 4-to-1 multiplexers and inverters only

x y cout s

000

011

11

001

100

11

000

101

11

011

010

01

010

101

01

cin

27 28

Problem 28Show how to implement Full Adder usingtwo 2-to-1 multiplexers and a minimum number of logic gates

x y cout s

000

011

11

001

100

11

000

101

11

011

010

01

010

101

01

cin

29 30

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Comparator

• Used two compare two M-bit numbers and produce a flag (M >1)• Inputs: M-bit input A, M-bit input B• Output: 1-bit output flag

• 1 indicates condition is met• 0 indicates condition is not met

• Can compare: >, >=, <, <=, ==, etc.

A > B?A

B

1 if A > B0 if A <= B

M

M

Problem 29Show how to implement 4-bit comparatorA==B using minimum number of logic gates

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4-bit comparator (A == B)

A == B?A

B

1 if A == B0 if A != B

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4

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ECE 545—Digital System Design with VHDLLecture 1B

Digital Logic RefresherPart B – Sequential Logic Building Blocks

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• Sequential Logic Building Blocks• Flip-Flops, Latches• Registers, Shift Registers• Counters• RAM

Lecture Roadmap – Sequential Logic

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Textbook References

• Sequential Logic Review• Stephen Brown and Zvonko Vranesic, Fundamentals of Digital

Logic with VHDL Design, 2nd or 3rd Edition• Chapter 7 Flip-flops, Registers, Counters, and a Simple

Processors(7.3-7.4, 7.8-7.11 only)

• OR your undergraduate digital logic textbook (chapters on sequential logic)

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Sequential Logic Building Blocks

some slides modified from:Brown and Vranesic, �Fundamentals of Digital Logic with VHDL Design, 2nd Edition�

S. Dandamudi, �Fundamentals of Computer Organization and Design�

Problem 1

What is a difference between combinational logic and sequential logic?

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Introduction to Sequential Logic

• Output depends on the current input and the internal state

• Past inputs effects the internal state• Sequential circuits consist typically of

• Storage elements (flip-flop, latch, register, RAM, etc.)• Combinational logic

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Introduction (cont�d)

Main components of a typical synchronous sequential circuit(synchronous = uses a clock to keep circuits in lock step)

COMBINATIONALLOGIC

STATE-HOLDING STORAGE ELEMENTS

(e.g. FLIP-FLOPS)

CLOCK

INPUT OUTPUT

NEXT STATES(t+1)

PRESENT STATES(t)

Problem 2

What is a difference between Latchesand Flip-flops?

4142

State-Holding Memory Elements

• Latch versus Flip Flop• Latches are level-sensitive: whenever clock is high, latch

is transparent• Flip-flops are edge-sensitive: data passes through (i.e.

data is sampled) only on a rising (or falling) edge of the clock

• Latches cheaper to implement than flip-flops• Flip-flops are easier to design with than latches

• In this course, primarily use D flip-flops

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D Latch vs. D Flip-Flop

Latch transparent when clock is high

�Samples� D on rising edge of clock

D Q

CLK

D Q

CLK

D

CLK

Q

D

CLK

Q

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Clock D 0 1 1

–0 1

0 1

Truth table Graphical symbol

t 1 t 2 t 3 t 4

Time

Clock

D Q

Timing diagram

Q(t+1)Q(t)

D latch

D Q

Clock

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Clk D ­­

0 1

0 1

Truth table

t 1 t 2 t 3 t 4

Time

Clock

D Q

Timing diagram

Q(t+1)

Q(t)

D flip-flop

D Q

Clock

Graphical symbol

0 –Q(t)1 –

Problem 3

What is a difference between:

a. Reset active high vs. Reset active lowb. Asynchronous Reset vs. synchronous Reset?

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D Flip-Flop with Asynchronous Set and Reset

• Bubble on the symbol means �active-low�

• When Set = 0, set Q to 1• When Set = 1, do nothing

• When Reset = 0, set Q to 0 • When Reset = 1, do nothing

• �Set� and �Reset� also known as �Preset� and �Clear�respectively

• In this circuit, Set and Reset are asynchronous

• Q changes immediately when preset or clear are active, regardless of clock

D Q

Q

Set

Reset

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D Flip-Flop with Synchronous Reset

• Asynchronous active-low Reset: Q immediately clears to 0 • Synchronous active-low Reset: Q clears to 0 on rising-edge

of clock

D

Clock Q

QClear

D Q

Q

D

CLK

Reset

Q(asynchronous Reset)

Q(synchronous Reset)

Reset

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Problem 4

What is a register?

4950

Register

• In typical nomenclature, a register is a name for a collection of flip-flops used to hold a bus

• All flip-flops of a register share the same clock and control signals

D Q

CLK

D Q

CLK

D Q

CLK

D Q

CLK

D(3)

D(2)

D(1)

D(0)

Q(3)

Q(2)

Q(1)

Q(0)

Clock

4 4

D Q

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Shift Register

D Q

Clk

D Q D Q D Q Sin Sout

t 0

t 1

t 2

t 3

t 4

t 5

t 6

t 7

1

0

1

1

1

0

0

0

0

1

0

1

1

1

0

0

0

0

1

0

1

1

1

0

0

0

0

1

0

1

1

1

0

0

0

0

1

0

1

1

Q 3 Q 2 Q 1 Sout=Q0Sin

Q 3 Q 2 Q 1 Q 0

Sin

Clk

Sout

Shift Register

Problem 5

Draw a symbol of a

a. 4-bit Shift Register with Enable, shifting to the right, with Serial Input and Serial Output only

a. 4-bit Shift Register with Enable, shiftingto the right, with Parallel Load, and Parallel Output

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4-bit Shift Registers: symbols

SoutEnable

Clk

Sin

a)

QEnable

Clk

4

D

Load

Sin

4

b)

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Problem 6

Draw a block diagram of a

a. 4-bit Shift Register with Enable, shifting to the right, with Serial Input and Serial Output only

a. 4-bit Shift Register with Enable, shiftingto the right, with Parallel Load, and Parallel Output

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Shift Register with Serial Input and Serial Output

D QSin

Clock

D Q D Q D Q

Q(3) Q(2) Q(1)

Enable

Sout=Q(0)

En En En En

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Shift Register with Parallel Load and Parallel Output

D(3)

D Q

Clock

Enable

SinD(2)

D Q

D(1)

D Q

D(0)

D Q

Q(0)Q(1)Q(2)Q(3)

Load

10 1

010

10

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Synchronous Up Counter

• Enable (synchronous): when high enables the counter, when low counter holds its value

• Load (synchronous) : when load = 1, load the desired value into the counter

• Output carry: indicates when the counter �rolls over�• D3 downto D0, Q3 downto Q0 is how to interpret MSB to LSB

enableloadD0D1D2D3

Q0Q1Q2Q3

clk

carry

Problem 7

Draw a block diagram of the digital circuit with the following interface and functionality:

Interface:Din – 8-bit data inputDout – 8-bit data outputAddr – 2-bit address of the location (register)

where input data is stored or output data is read from

RW – control signal, 0=read, 1=writeClk – clock

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Problem 7 (cont.)

Functionality:If RW = 1 (write), then the output Dout is set to the high impedance state, and at the next rising edge of the clock, data from the input Din is stored in the internal location given by the address Addr.If RW = 0 (read), data from the location given by the address Addr is transferred to the output Dout, and the contents of the internal memory (registers) does not change.

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Problem 7 (cont.)

Assume that the internal memory is implemented using registers.Use only medium scale components, such as registers, multiplexers, encoders, decoders, buffers, etc.

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Problem 8

What is a difference in terms of the requiredinputs and outputs between ROM and RAMof the same size (e.g. 2m x n)?

6162

Random Access Memory (RAM)

• More efficient than registers for storing large amounts of data

• Can read and write to RAM• Addressable memory• RAM dimensions are:

• (number of words) x (bits per word)

• Address is m bits, data is n bits• 2m x n-bit RAM

• Example: address is 5 bits, data is 8 bits• 32 x 8 RAM

• Write Enable (WE)• When set, writing takes place

at the next rising edge of the clock

RAM

DIN

ADDR

DOUT

WE

n n

m

CLK

Problem 9

Draw a block diagram showing how to build256x1 RAM out of four 64x1 RAMs.

63 64

65

Problem 10

What is a difference between a) RAM with asynchronous read and b) RAM with synchronous read?

66

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Problem 11

What is a value at the output of RAM with synchronous read during a write operation?

6768

Block RAM Waveforms – READ_FIRST mode

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Block RAM Waveforms – WRITE_FIRST mode

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Block RAM Waveforms – NO_CHANGE mode

Problem 12

What is a difference between a single-portand dual-port RAM?

What operations are allowed in the dual-port RAM?

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Dual-Port RAM

RAM

DINA

ADDRA

DOUTA

WEA

n n

m

CLK

DINB

ADDRB

DOUTB

WEB

n n

m

• Two sets of input ports{DINA, ADDRA, WEA}{DINB, ADDRB, WEB}

• Two corresponding outputsDOUTADOUTB

• One memory matrix

• Possible operations:• Read from two memory locations• Write to two different memory

locations• Read from a memory location

and write to a memory location(different or the same)