ECE 477 Design Review ECE 477 Design Review Team 6 Team 6 Spring 2009 Spring 2009

David Eslinger

CurtSchieler

AJ Hartnett

Ken Pesyna

OutlineOutline• Project overview Project overview • Project-specific success criteriaProject-specific success criteria• Block diagramBlock diagram• Component selection rationaleComponent selection rationale• Packaging designPackaging design• Schematic and theory of operationSchematic and theory of operation• PCB layoutPCB layout• Software design/development statusSoftware design/development status• Project completion timelineProject completion timeline• Questions / discussionQuestions / discussion

Project OverviewProject Overview

• GOAL: Measure performance of a lossless GOAL: Measure performance of a lossless compression algorithm in an FPGA compression algorithm in an FPGA

• Rice Coding is algorithm of interest, Rice Coding is algorithm of interest, generally used in FLACgenerally used in FLAC

• Project will be a small device thatProject will be a small device that– Compresses and stores audio inputCompresses and stores audio input– Measures latency of compression and Measures latency of compression and

decompressiondecompression

Project-Specific Success CriteriaProject-Specific Success Criteria

• An ability to encode streaming audio into a An ability to encode streaming audio into a FLAC format using the Rice compression FLAC format using the Rice compression algorithm algorithm

• An ability to decode FLAC for playbackAn ability to decode FLAC for playback• An ability to store data in external memoryAn ability to store data in external memory• An ability to compute latency between input An ability to compute latency between input

audio and playbackaudio and playback• An ability to display relevant information on An ability to display relevant information on

an LCDan LCD

Block DiagramBlock Diagram

Component Selection RationaleComponent Selection Rationale

• FPGA design constraintsFPGA design constraints– Enough logical elements for computational Enough logical elements for computational

requirementsrequirements– PLLs – 1 for SDRAM, 1 for internal clockPLLs – 1 for SDRAM, 1 for internal clock– Enough IO pins for peripherals and Enough IO pins for peripherals and

debuggingdebugging

Component Selection RationaleComponent Selection Rationale

• FPGA: Cyclone IIIFPGA: Cyclone III– 40,000 logical elements40,000 logical elements– 4 PLLs4 PLLs– 80 IO pins80 IO pins

– Dev. board available for Cyclone IIDev. board available for Cyclone II– Tools available (Quartus II)Tools available (Quartus II)– Less expensive than Cyclone IILess expensive than Cyclone II

Component Selection RationaleComponent Selection Rationale

• Microcontroller design constraintsMicrocontroller design constraints– SPI module (x2)SPI module (x2)– UART module (x2)UART module (x2)– No need for a large amount of memoryNo need for a large amount of memory

Component Selection RationaleComponent Selection Rationale

• Microcontroller: PIC24FMicrocontroller: PIC24F– 2 SPI/UART modules2 SPI/UART modules– 16kB memory16kB memory

– FamiliarityFamiliarity

Component Selection RationaleComponent Selection Rationale

• ADC and DAC design constraintsADC and DAC design constraints– Sampling rate of 44 kHzSampling rate of 44 kHz– 16 bits per sample16 bits per sample– Number of pins (SPI vs. parallel)Number of pins (SPI vs. parallel)

Component Selection RationaleComponent Selection Rationale

• Audio CODECAudio CODEC– Programmable sampling rate (8 kHz to 96 Programmable sampling rate (8 kHz to 96

kHz)kHz)– Programmable bits per sample Programmable bits per sample

(16/20/24/32)(16/20/24/32)– Internal A/D and D/AInternal A/D and D/A– Microphone input and line level outputMicrophone input and line level output– Used on Cyclone II dev. boardUsed on Cyclone II dev. board

Component Selection RationaleComponent Selection Rationale

• Memory design constraintsMemory design constraints– Enough for 30 seconds of audioEnough for 30 seconds of audio

– Rewriteable Rewriteable

30 seconds × 44000 samples1 second × 16 bits1 sample× 8 bits1 byte× 0.6 compression ratio ≈ 1.5 𝑀𝐵

Component Selection RationaleComponent Selection Rationale

• Memory: SDRAM from ISSIMemory: SDRAM from ISSI– 8 MB8 MB

– FLASH too slowFLASH too slow• Not meant for constant rewritesNot meant for constant rewrites

– SRAM doesn’t meet size requirementSRAM doesn’t meet size requirement

Packaging DesignPackaging Design• 1/8” plastic enclosure to provide insulation and 1/8” plastic enclosure to provide insulation and

protection for our componentsprotection for our components• 9V DC wall wart & power in port9V DC wall wart & power in port• LCD, pushbuttons, mic-in and line-out jacksLCD, pushbuttons, mic-in and line-out jacks• PCB: 5.2” x 4.7” Packaging: 7” x 5” x 2”PCB: 5.2” x 4.7” Packaging: 7” x 5” x 2”

Schematic/Theory of OperationSchematic/Theory of OperationAudio Input and OutputAudio Input and Output

AudioCODEC

Mic IN

Line OUT

Schematic/Theory of OperationSchematic/Theory of OperationMemoryMemory

FPGASDRAM

Schematic/Theory of OperationSchematic/Theory of OperationOscillatorOscillator

FPGA

VCO

Schematic/Theory of OperationSchematic/Theory of OperationConfiguration/Reset - FPGAConfiguration/Reset - FPGA

FPGA

USB Blaster

EEPROM

Reset

Schematic/Theory of OperationSchematic/Theory of OperationConfiguration/Reset - uCConfiguration/Reset - uC

MicrocontrollerPIC24

JTAG

nMCLR

Schematic/Theory of Operation Schematic/Theory of Operation FPGA DebugFPGA Debug

FPGA

RS-232 Driver

DB9

LevelTranslator

Schematic/Theory of OperationSchematic/Theory of OperationUser InterfaceUser Interface

Schematic/Theory of Operation Schematic/Theory of Operation Power Supply and Voltage RegulationPower Supply and Voltage Regulation

5V

9V DC IN

2.5V3.3V

1.2V

Schematic/Theory of OperationSchematic/Theory of OperationIsolated power for PLLsIsolated power for PLLs

FPGA

PCB Layout ConsiderationsPCB Layout Considerations

• Peripherals (Line-out, mic-in, power jack)Peripherals (Line-out, mic-in, power jack)– Near the edge of boardNear the edge of board

• SDRAM near FPGA (short traces)SDRAM near FPGA (short traces)• 4 layer board – high density around FPGA4 layer board – high density around FPGA

– Must be under 30 inMust be under 30 in22

PCB LayoutPCB Layout

PCB LayoutPCB Layout

FPGA

uC

5V1.2V

3.3V2.5V

Mic

Line out

VCO

pushbuttonsLCD

PWRJTAG

PCB – PowerPCB – Power

PCB – Power PlanePCB – Power Plane

PCB – Ground PlanePCB – Ground Plane

PCB – FPGAPCB – FPGA

PCB – FPGA Bypass CapsPCB – FPGA Bypass Caps

PCB – FPGA Bypass Caps (1.2 PCB – FPGA Bypass Caps (1.2 V)V)

PCB – FPGA Bypass Caps (3.3 PCB – FPGA Bypass Caps (3.3 V)V)

PCB – FPGA Bypass Caps PCB – FPGA Bypass Caps (1.2 V power island)(1.2 V power island)

PCB – FPGA Bypass Caps PCB – FPGA Bypass Caps (2.5 V power island)(2.5 V power island)

PCB Layout – Config devicesPCB Layout – Config devices

PCB Layout - SDRAMPCB Layout - SDRAM

PCB Layout – MicroPCB Layout – Micro

PCB Layout – Audio CODECPCB Layout – Audio CODEC

PCB Layout – DebugPCB Layout – Debug

PCB Layout – DebugPCB Layout – Debug

Software Design/Development StatusSoftware Design/Development Status

Software Design/Development StatusSoftware Design/Development Status

Project Completion TimelineProject Completion Timeline

Questions / DiscussionQuestions / Discussion

ReferencesReferencesWolfson Audio CODEC Block Diagram