ECE 477 Design Review Team 2 Fall 2007. Outline Project overviewProject overview Project-specific success criteriaProject-specific success criteria

ECE 477 Design Review ECE 477 Design Review Team 2 Team 2 Fall 2007 Fall 2007

OutlineOutline• Project overview Project overview • Project-specific success criteriaProject-specific success criteria• Block diagramBlock diagram• Component selection rationaleComponent selection rationale• Packaging designPackaging design• Schematic and theory of operationSchematic and theory of operation• PCB layoutPCB layout• Software design/development statusSoftware design/development status• Project completion timelineProject completion timeline• Questions / discussionQuestions / discussion

Project OverviewProject Overview

• The Hooked on Harmonix system is a learning tool The Hooked on Harmonix system is a learning tool intended to teach the user how to play the keyboard. intended to teach the user how to play the keyboard. The system consists of a midi keyboard, a processing The system consists of a midi keyboard, a processing unit, and a display with speakers. The user will choose a unit, and a display with speakers. The user will choose a song that he would like to learn. The song will then be song that he would like to learn. The song will then be played through the system speakers while the played through the system speakers while the corresponding notes are streamed on the display. The corresponding notes are streamed on the display. The user will then attempt to match the correct notes and user will then attempt to match the correct notes and timing using the keyboard to play the song. Hooked on timing using the keyboard to play the song. Hooked on Harmonix will provide dynamic feedback while the song Harmonix will provide dynamic feedback while the song is played to help the user improve his play.is played to help the user improve his play.

Project-Specific Success CriteriaProject-Specific Success Criteria

• An ability to (audibly) play and (internally) decode An ability to (audibly) play and (internally) decode note/timing information from a pre-existing note/timing information from a pre-existing song/data file.song/data file.

• An ability to decode/encode data output by a An ability to decode/encode data output by a standard MIDI keyboard into a format compatible standard MIDI keyboard into a format compatible with the aforementioned song/data file.with the aforementioned song/data file.

• An ability to display the notes the user should play An ability to display the notes the user should play based on data provided by the decoded song file (as based on data provided by the decoded song file (as mentioned above).mentioned above).

• An ability to compare user input from the MIDI An ability to compare user input from the MIDI keyboard with data generated by the decoded sound keyboard with data generated by the decoded sound file on the basis of note/timing accuracy.file on the basis of note/timing accuracy.

• An ability to calculate (and display) a performance An ability to calculate (and display) a performance score for the user based on the accumulated score for the user based on the accumulated note/timing accuracy.note/timing accuracy.

Block DiagramBlock Diagram

Flash (Config)

Component Selection RationaleComponent Selection Rationale

• MicrocontrollerMicrocontroller– FPGA For video outputFPGA For video output– SRAM, Flash, Clock can be externalSRAM, Flash, Clock can be external– DE2 Board availableDE2 Board available

• MemoryMemory– Video BufferingVideo Buffering– Graphic and Audio StorageGraphic and Audio Storage– FPGA ConfigurationFPGA Configuration

Packaging DesignPackaging Design

• 6 x 6 x 2 inch box6 x 6 x 2 inch box• Separate PeripheralsSeparate Peripherals

– MonitorMonitor– MIDI KeyboardMIDI Keyboard

Schematic/Theory of OperationSchematic/Theory of Operation

I/O SheetI/O Sheet Power SheetPower Sheet


Voltage Regulation (LD1117)Voltage Regulation (LD1117)


• FPGA receives clock signal from an 80 MHz oscillator

• FPGA internally divides input clock into 40 MHz and 13.333 MHz signals

Clock Frequencies (ASFL1)Clock Frequencies (ASFL1)


Serial Configuration Device (EPCS64)Serial Configuration Device (EPCS64)


SRAM (IS61LV5128AL)SRAM (IS61LV5128AL)


Cyclone II FPGA (EP2C20)Cyclone II FPGA (EP2C20)


DAC DAC – 8 Bit (– 8 Bit (ADV7123JST33ADV7123JST330)0)Converts digital RGB to analog VGA videoConverts digital RGB to analog VGA video


MIDI input through opto-isolator (6N1MIDI input through opto-isolator (6N137)37)


MIDI synthesizer LSI (BU879MIDI synthesizer LSI (BU87933KN)KN)

PCB Layout – PCB Layout – Overall ConsiderationsOverall Considerations

• Chip ArrangementChip Arrangement– SRAM: address and data bussesSRAM: address and data busses– DAC: RGB digital video dataDAC: RGB digital video data– MIDI synthesizer chipMIDI synthesizer chip

• EMI managementEMI management– Analog signals (DAC, MIDI out)Analog signals (DAC, MIDI out)– Clock signalsClock signals

• Power and Ground pin outPower and Ground pin out– Bypass capacitorsBypass capacitors– Power and ground planesPower and ground planes

PCB Layout – PCB Layout – FPGAFPGA

PCB Layout – PCB Layout – Voltage RegulatorsVoltage Regulators

PCB Layout - PCB Layout - SRAMSRAM

PCB Layout - PCB Layout - FlashFlash

PCB Layout - PCB Layout - OscillatorOscillator

PCB Layout – PCB Layout – MIDI SynthesizerMIDI Synthesizer

PCB Layout - PCB Layout - DACDAC

PCB Layout – PCB Layout – Optical IsolatorOptical Isolator

PCB Layout – PCB Layout – Headers/JacksHeaders/Jacks

Software Design/Development StatusSoftware Design/Development StatusLoad program from flash

Load sprites from flash to SRAM

Display song menu

Song chosen?

No

Yes

Software Design/Development StatusSoftware Design/Development Status

Load song from flash

Pass note info sequentially to FPGA

Watch MIDI input

Correct note in time

tolerance?

NoYes


NoYes

Increment score (show message)

Decrement score (show message)

End of song?

End of song?

Show final score

No No

Yes Yes


• Counter process used for song timingCounter process used for song timing• Pass pixel values from SRAM to DAC at Pass pixel values from SRAM to DAC at

appropriate pixel clock intervalsappropriate pixel clock intervals– 40 MHz pixel clock for 800 x 600 resolution 40 MHz pixel clock for 800 x 600 resolution

at 60 Hz refresh rateat 60 Hz refresh rate• Send HSYNC and VSYNC signals during Send HSYNC and VSYNC signals during

horizontal and vertical blanking periods, horizontal and vertical blanking periods, respectivelyrespectively

Project Completion TimelineProject Completion Timeline

Obtain AllParts

FinalizePCB

Populate PCB

Spriteson screen

ParseMIDI

Bars Scrolling

Bar Linked to MIDI Play Comparison SoftwareComplete

October NovemberWeek 3 Week 4 Week 1 Week 2 Week 3 Week 4 Week 5

VHDLTutorials

NIOS IITutorials Output MIDI

MenuScreens

Scoring and Timing

VHDLCompleteStatic Images Shown

Key: C++VHDLPCB

Debug PCB

HardwareComplete

Questions / DiscussionQuestions / Discussion

Documents

ECE 477 Design Review Team 2 Fall 2007. Outline Project overviewProject overview Project-specific success criteriaProject-specific success criteria