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ECE 448: Spring 11 Lab 3 Sequential Logic for Synthesis. Agenda for today. Introduction: Why are we here? Part 1: Pseudorandom Random Number Generators Part 2: Debouncing Circuit Part 3: Rising Edge Detector Part 4: Counter Part 5: Clock Divider Part 6: Basys II - PowerPoint PPT Presentation
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ECE 448: Spring 11Lab 3
Sequential Logic for Synthesis
Introduction: Why are we here?
Part 1: Pseudorandom Random Number Generators
Part 2: Debouncing Circuit
Part 3: Rising Edge Detector
Part 4: Counter
Part 5: Clock Divider
Part 6: Basys II
Part 7: FPGA Design Flow based on Aldec Active-HDL
Agenda for today
Introduction
• Purpose- Test basic circuits on the Basys II– Counter– Debouncing circuit– Rising edge detector
• Introduction to Pseudo-Random Number Generator (PRNG)
• Introduction to FPGA Design Flow based onAldec Active-HDL
Debouncer test
7-Seg Display Unit
15:8 7:0
Genericn=8
Counter
rst_i
step_i
clk_i
data_o
en_i
8
Genericn=8
Counter
rst_i
step_i
clk_i
data_o
en_i
8
REDbutton(0)
button(2) button(2)
sw(3:0)zeros(7:4)
8
REDDEBOUNCER button(1)
clk_50M
clk_1k
Notation: RED – Rising Edge Detector
Top-level Circuit for Lab 3
7-Seg Display Unit
15:8 7:0
rst_i
clk_i
data_o
en_i
8
PRNG
rst_i
clk_i
data_o
en_i
8
REDbutton(0)
button(2) button(2)
DEBOUNCER
clk_50M
clk_1k
Genericn=8
Counter
Notation: RED – Rising Edge Detector
Part 1
Pseudo-Random Number Generator
PRNG• Also known as Deterministic Random Bit Generator (DRBG)• Generates a sequence of numbers that
approximates the properties of random numbers.
• The sequence is fully deterministic, i.e., it can be repeated based on an initial state of PRNG.• The period of the sequence may be made very
large (typically, 2n-1, where n is an internal state size)
PRNG
• Random Numbers are often important– Testing of VLSI circuits– Cryptography– Monte Carlo simulations– Noise addition– Bit error detection, and many other applications
PRNG
Block Diagram of Lab 3 PRNG
Inputs of XOR gates
Three Initialization Options
Option 1 (required): Initialization to ALL ONES, using the signal SET common to all shift registers (connected to rst_i).Option 2 (required): Initialization to ALL ONES by shifting '1’ to all shift registers for 6 clock cycles after reset.Option 3: (bonus): Initialization to arbitrary value,by shifting in internal state serially, using special input sin, one bit per clock cycle.
PRNG Test VectorsClock Cycle Output
1 FF2 743 BD4 675 EA6 AE7 4E8 5B9 6A10 62
Clock Cycle Output
11 D912 3113 8714 3815 95 16 1917 5c18 CE19 7E20 52
Part 2
Debouncing Circuit
Debouncer
Capacitance in the button and contacts “bouncing” causes spurs that cause false positives. A debouncing circuit removes these spurs.
Debouncer
When the first change is detected, we ignore all subsequent changes for some period of time, preferably until all of the bouncing would have occurred. This is usually on the order of ms.
Debouncer
Debouncer
reset
input
clk
output
Debouncer
Part 3
Rising Edge Detector
Rising Edge Detector
• Turn a step function into an impulse• Allows a step to run a circuit for only one clock
cycle• Can also be used to cross clock domains
Rising Edge Detector
Rising Edge Detector
clk_i
data_i
data_o
data_i
clk_i
data_o
rising edge detector
Part 4
Counter
Counter
• Count whenever enable signal is high• Synchronous reset• Data out is valid after one clock cycle• Increment step size is configurable• Why use a generic?
– Generics make circuits reusable
Counter
Genericn
Counter
rst_i
step_i
clk_i
data_o
en_i
n
n
Counter
Register0
1
step_i
en_i clk_i
data_o
n
n
n
nrst_i
Part 5
Clock Divider
Clock Divider
Clock Divider
Counter = c n
rst_i
en
clk_i
clk_o
data_o
en_i
step_i
1
n
Part 6
Basys II
Basys II
Basys II
Switches (8)Buttons (4)
7 Segment Displays (4)
VGA connector
ON/OFF Switch
Expansion ports
LEDs (8)
Basys 2 I/O Circuits
Seven Segment Display
• By lighting different combinations of LEDs, different figures appear
• For Instance CA, CB, CC make ‘7’
• Common anode means that writing a ‘0’ to CA-DP illuminates the led, where a ‘1’ turns it off
Seven Segment Display
• SSRegCtrl has a 16 bit input that is divided into four 4-bit digits
• AN(0:3) select which 7 segment display to output to
• Digilent recommends a digit period of between 1kHz and 60Hz
Part 7
FPGA Design Flow based on Aldec Active-HDL
FPGA Design process (1)Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds…..
Library IEEE;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;
entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; );end AES_core;
Specification (Lab Assignments)
VHDL description (Your Source Files)
Functional simulation
Post-synthesis simulationSynthesis
On-paper hardware design (Block diagram & ASM chart)
FPGA Design process (2)
Implementation
Configuration
Timing simulation
On chip testing
Design Process control from Active-HDL