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ECE 448: Spring 11Lab 3
Part 2
Finite State Machines
Introduction: What’s new with version 3a?
Part 1: Finite State Machines
Part 2: Debouncing Circuit (FSM Style)
Part 3: Digital Clock Managers
Part 4: User Constraints File
Part 5: Introduction to FPGA Design Flow based on Xilinx ISE
Agenda for today
Introduction
• Purpose – To learn about Finite State Machines and Clock Management.
• FSM – One of the single, most important lessons to be learned this year. FSMs can be found in the following:– Everything!
• DCM – The other, most important lesson to be learned this year. DCMs (and the related clock buffers) are very important for creating, cleaning, and distributing clocks.
• UCF – How the circuit interfaces with the outside world. Also very important.
Part 1
Finite State Machines
Finite State Machines
• Two types– Moore Machine – The state machine outputs are a
function of only the current state– Mealy Machine – The state machine outputs are a
function of the current state and the current inputs
• Every design can be described in either a Moore machine or a Mealy machine. Different designs can be used depending on speed, size, and routing requirements.
Moore FSM - Example 1• Moore FSM that Recognizes Sequence “10”
S0 / 0 S1 / 0 S2 / 1
00
0
1
11
reset
Moore FSM in VHDL (1) TYPE state IS (S0, S1, S2); SIGNAL Moore_state: state;begin U_Moore: PROCESS (clock, reset) BEGIN IF reset = ‘1’ THEN Moore_state <= S0; ELSIF rising_edge(clock) THEN CASE Moore_state IS WHEN S0 => IF input = ‘1’ THEN Moore_state <= S1; ELSE Moore_state <= S0; END IF; WHEN S1 => IF input = ‘0’ THEN Moore_state <= S2; ELSE Moore_state <= S1; END IF; WHEN S2 => IF input = ‘0’ THEN Moore_state <= S0; ELSE Moore_state <= S1; END IF; END CASE; END IF; END PROCESS; Output <= ‘1’ WHEN Moore_state = S2 ELSE ‘0’;
Mealy FSM - Example 1
• Mealy FSM that Recognizes Sequence “10”
S0 S1
0 / 0 1 / 0 1 / 0
0 / 1reset
Mealy FSM in VHDL (1) TYPE state IS (S0, S1); SIGNAL Mealy_state: state;begin U_Mealy: PROCESS(clock, reset) BEGIN IF reset = ‘1’ THEN Mealy_state <= S0; ELSIF rising_edge(clock) THEN CASE Mealy_state IS WHEN S0 => IF input = ‘1’ THEN Mealy_state <= S1; ELSE Mealy_state <= S0; END IF; WHEN S1 => IF input = ‘0’ THEN Mealy_state <= S0; ELSE Mealy_state <= S1; END IF; END CASE; END IF; END PROCESS; Output <= ‘1’ WHEN (Mealy_state = S1 AND input = ‘0’) ELSE ‘0’;
Part 2
Debouncing Circuit
Debounce
Capacitance in the button and contacts “bouncing” causes spurs that cause false positives. A debouncing circuit removes these spurs.
Debounce
When the first change is detected, we ignore all subsequent changes for some period of time, preferably until all of the bouncing would have occurred. This is usually on the order of ms.
Debounce
Debouncer
reset
input
clk
output
Debounce
S0output=0c_rst=1
S2output=1c_rst=1
S3output=0c_rst=0
S1output=1c_rst=0
input==1
input==0
count==DD-1
count==
DD
-1
reset==1
count is the state of the n-bit counter.c_rst is the reset to this counter.
DD is the maximum number of clock cycles required for bouncing to stop. All resets are synchronous.
Part 3
Clock Management
Clock Management
• Clock sources are generated off of the FPGA• Clock source needs to enter the FPGA• Clock needs to be “de-jittered”
– Clock naturally has non-constant duty cycle and period
• Clock needs to reach the rest of the chip
Clock Management
• Ideal clock is 1 frequency.
• Clock jitter is many frequencies around desired frequency.
• We can see the jitter in the yellow clock.
• Blue clock is de-jittered.
Clock Management
• Clock Enters FPGA and enters IBUFG• Output of BUFG goes to the rest of the FPGA• Invert of LOCKED signal is reset for all circuits on domain• To simulate, include the following lines in the library section
– Library UNISIM;– use UNISIM.vcomponents.all;
• Reset can be ORed with other resets (as from buttons)
DCM Primitive
IBUFG BUFGclk_50
locked
clk_ibufg clk0
reset
clkin
clkfb
clk0
resetbutton(2)
Clock Management
• DCM also changes clock frequency
• CLK2X doubles frequency
• CLKDV and CLKFX change the frequency based on the generics (see instantiation)
DCM_SP
Clock Management generic map (
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
CLKFX_DIVIDE => 1, -- Can be any integer from 1 to 32
CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
CLKIN_PERIOD => 0.0, -- Specify period of input clock
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
-- an integer from 0 to 15
DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
FACTORY_JF => X"C080", -- FACTORY JF Values
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
Clock Management port map (
CLK0 => CLK0, -- 0 degree DCM CLK ouptput
CLK180 => CLK180, -- 180 degree DCM CLK output
CLK270 => CLK270, -- 270 degree DCM CLK output
CLK2X => CLK2X, -- 2X DCM CLK output
CLK2X180 => CLK2X180, -- 2X, 180 degree DCM CLK out
CLK90 => CLK90, -- 90 degree DCM CLK output
CLKDV => CLKDV, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => CLKFX, -- DCM CLK synthesis out (M/D)
CLKFX180 => CLKFX180, -- 180 degree CLK synthesis out
LOCKED => LOCKED, -- DCM LOCK status output
PSDONE => PSDONE, -- Dynamic phase adjust done output
STATUS => STATUS, -- 8-bit DCM status bits output
CLKFB => CLKFB, -- DCM clock feedback
CLKIN => CLKIN, -- Clock input (from IBUFG, BUFG or DCM)
PSCLK => PSCLK, -- Dynamic phase adjust clock input
PSEN => PSEN, -- Dynamic phase adjust enable input
PSINCDEC => PSINCDEC, -- Dynamic phase adjust increment/decrement
RST => RST); -- DCM asynchronous reset input
Clock Management
IBUFG_inst : IBUFG
generic map (
IOSTANDARD => "DEFAULT")
port map (
O => O,
I => I);
•Dedicated clock route for reaching a DCM and the rest of the chip•Should be used for all clock ports
BUFG_inst : BUFG
port map (
O => O,
I => I);
•Dedicated clock route for reaching the rest of the chip at the same time•Should be used for all generated clocks
– Output from DCM– Output from clock divider circuits
Part 4
User Constraint File (UCF)
User Constraint File (UCF)
• File contains various constraints for Xilinx– Clock Periods– Clock Boundary Crossings (hard to do! That’s why
we use a CoreGen’ed FIFO)– Circuit Locations– Pin Locations
• Every pin in the top unit needs to have a pin in the UCF
Basys 2 I/O Circuits
User Constraint File (UCF)
Top Level Unit (VHDL)entity top_level is
port(
-- LEDs
led : out std_logic_vector(7 downto 0);
-- Seven Segment Display
seg : out std_logic_vector(7 downto 0);
an : out std_logic_vector(3 downto 0);
-- Rotary button and switches
sw : in std_logic_vector(7 downto 0);
btn : in std_logic_vector(3 downto 0));
end entity top_level;
UCF# Pin assignment for LEDs
NET “led<7>" LOC = "G1" ; # Bank = 3, Signal name = LD7
NET “led<6>" LOC = "P4" ; # Bank = 2, Signal name = LD6
NET “led<5>" LOC = "N4" ; # Bank = 2, Signal name = LD5
NET “led<4>" LOC = "N5" ; # Bank = 2, Signal name = LD4
NET “led<3>" LOC = "P6" ; # Bank = 2, Signal name = LD3
NET “led<2>" LOC = "P7" ; # Bank = 3, Signal name = LD2
NET “led<1>" LOC = "M11"; # Bank = 2, Signal name = LD1
NET “led<0>" LOC = "M5" ; # Bank = 2, Signal name = LD0
# Connected to Basys2 onBoard 7seg display
NET "seg<0>" LOC = "L14"; # Bank = 1, Signal name = CA
NET "seg<1>" LOC = "H12"; # Bank = 1, Signal name = CB
NET "seg<2>" LOC = "N14"; # Bank = 1, Signal name = CC
NET "seg<3>" LOC = "N11"; # Bank = 2, Signal name = CD
NET "seg<4>" LOC = "P12"; # Bank = 2, Signal name = CE
NET "seg<5>" LOC = "L13"; # Bank = 1, Signal name = CF
NET "seg<6>" LOC = "M12"; # Bank = 1, Signal name = CG
NET “seg<7>" LOC = "N13"; # Bank = 1, Signal name = DP
NET "an<3>" LOC = "K14"; # Bank = 1, Signal name = AN3
NET "an<2>" LOC = "M13"; # Bank = 1, Signal name = AN2
NET "an<1>" LOC = "J12"; # Bank = 1, Signal name = AN1
NET "an<0>" LOC = "F12"; # Bank = 1, Signal name = AN0
# Pin assignment for SWs
NET "sw<7>" LOC = "N3"; # Bank = 2, Signal name = SW7
NET "sw<6>" LOC = "E2"; # Bank = 3, Signal name = SW6
NET "sw<5>" LOC = "F3"; # Bank = 3, Signal name = SW5
NET "sw<4>" LOC = "G3"; # Bank = 3, Signal name = SW4
NET "sw<3>" LOC = "B4"; # Bank = 3, Signal name = SW3
NET "sw<2>" LOC = "K3"; # Bank = 3, Signal name = SW2
NET "sw<1>" LOC = "L3"; # Bank = 3, Signal name = SW1
NET "sw<0>" LOC = "P11"; # Bank = 2, Signal name = SW0
# Pin assignments for the Buttons
NET "btn<3>" LOC = "A7"; # Bank = 1, Signal name = BTN3
NET "btn<2>" LOC = "M4"; # Bank = 0, Signal name = BTN2
NET "btn<1>" LOC = "C11"; # Bank = 2, Signal name = BTN1
NET "btn<0>" LOC = "G12"; # Bank = 0, Signal name = BTN0
Part 5
Introduction to FPGA Design Flow
based on Xilinx ISE