ECE 447 - Lecture 2

Internal Input/OutputDevices (I/O Subsystems)

CPU RAM

ROM

EEPROM

TIMER

A/DSPI

SCI

PORT A PORT B PORT C PORT D PORT E

Organization of MC68HC11 in the Single-Chip Mode

8 8 (4)8

24

6

8 (4)8

3 3 2

Abbreviations

CPU - Central Processing Unit := ALU (Arithmetic Logic Unit) + Control

RAM - Random Access Memory := Read/Write Memory

ROM - Read Only Memory (non-volatile)

EPROM - Erasable Programmable ROM

EEPROM - Electrically Erasable ROM

SCI - Serial Communication Interface (asynchronous serial communication interface)

SPI - Serial Peripheral Interface (synchronous serial communication interface)

A/D - analog-to-digital converter

Input/Output Ports

PortInput Pins

Output Pins

Bidirectional Pins

SharedFunctions

Port A

Port B

Port C

Port D

Port E

3

–

–

–

8

3

8

–

–

–

2

–

8

6

–

Timer

High Order Address

Low Order Address and Data Bus

SCI and SPI

A/D Converter

Capabilities of the A/D converter

VRH 6 V

> 2.5 V

VRL 0 V

ADC

• successive approximation • minimum 4 conversions• single-channel or four-channel conversions• one-time or continuous conversions

10010010100100111001001110010100

Capabilities of the 68HC11 timer (1)

label 1

label2

instr1instr2

instrN

1. Generating delays - imposing a specific delay between two points in the program

delay

2. Pulse accumulation - counting the number of pulses

Capabilities of the 68HC11 timer (2)

3. Input capture - measuring the time between signal edges

4. Output compare - generating signals with the given timing characteristics

start stop

start stop

pulse width

single pulse periodical signal

period

I/O Device Architecture

…..

Control registersinstructions

…..

Status registersstatus of the device

Data registers

…..

I/O device

address1/name1

addressN/nameN

. . . . .

inputs (operands)

outputs (results)

Input/Output Register Types

1. Control registers - hold instructions that regulate the operation of internal I/O devices

2. Status registers - indicate the current status of internal I/O devices

3. Data registers - hold the input data sent to the I/O device and output data generated by this device

4. Data direction registers - control the direction (in or out) of the data flow to/from bidirectional data registers

Memory mapped I/O

(e.g., Motorola)

0

MAX

I/O

Control lines: read/write

Separate I/O

(e.g., Intel)

0

MAX

I/O0

max

Control lines: read/write memory/io

Memory map of MC68HC11E9

$0000

$1000

$B600

$D000

$FFFF

$0000-$01FF 512 bytes RAM

$1000-$103F 64 bytes I/O registers

$B600-$B7FF 512 bytes EEPROM

$D000-$FFFF12 kbytes ROM

Single-chip mode

Memory map of MC68HC11E1

$0000

$1000

$B600

$FFFF

$0000-$01FF 512 bytes RAM

$1000-$103F 64 bytes I/O registers

$B600-$B7FF 512 bytes EEPROM

Single-chip mode

CPU RAM

ROM

EEPROM

TIMERA/D

SPI

SCI

PORT A PORT D PORT E

Organization of MC68HC11 in the Expanded Bus Mode

8 (4)

24

6

8 (4)8

3 3 2

EXTERNAL RAM

EXTERNAL ROM

EXTERNAL EPROM

EXTERNAL I/O

Memory map of MC68HC11E1

$0000

$1000

$B600

$FFFF

$0000

$1000

$B600

$FFFF

EXT

EXT

EXT

$0000-$01FF 512 bytes RAM

$1000-$103F 64 bytes I/O registers

$B600-$B7FF 512 bytes EEPROM

Single-chip mode Expanded bus mode

Evaluation Board Configuration

68HC11E9

68HC24 - Port Replacement Unit

RAM (e.g. 5164)

ROM(e.g., 2764)

50 kB$2000-$B5FF

12 kB$D000-$FFFF

Program & data

Buffalomonitor

B

C

B

C

A

DE

RAM512B

EEPROM 512B

Memory map of MC68HC11E9 with an external RAM

$0000

$1000

$B600

$FFFF

$0000-$01FF 512 bytes RAM

$1000-$103F 64 bytes I/O registers

$B600-$B7FF 512 bytes EEPROM

Expanded bus mode

$D000

$0000-$B5ff 32 kbytes RAM

$D000-$FFFF 12 kbytes ROM

$A5ff