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ECE 3450 M. A. Jupina, VU, 2010
MemoryIntroductionRead Only Memory (ROM)
MROM PROM EPROM EEPROM Flash Memory
Random Access Memory (RAM) SRAM DRAM
Memory Expansion using Multiple ICs
ECE 3450 M. A. Jupina, VU, 2010
Lecture Objectives Understand and correctly use the terminology associated with memory
systems. Describe the difference between read/write memory and read-only
memory (and between volatile and nonvolatile memory). Determine the capacity of a memory device from its inputs and outputs. Understand the differences between EPROM, EEPROM, and FLASH
memory Understand the basic operation of and the differences between SRAMs
and DRAMs. Understand how data is written to and read from a SRAM device. Combine memory ICs to form memory modules with larger word size
and/or capacity.
References:1. Memory reference at the course web site. 2. Fundamentals of Digital Logic, sections 3.10 (EEPROMs), 3.10.1,
10.1.3, 10.1.4, and 10.2.5, and appendix D.2.
ECE 3450 M. A. Jupina, VU, 2010
Vocabulary• Memory Cell – A device or an electrical circuit used to store a single
bit (0 or 1)• Memory Word – A group of bits in a memory (word sizes typically
range from 4 to 64).• Byte – a group of 8 bits• Capacity or Density – A way of specifying how many bits can be
stored in a particular memory device or system.– Example: 4096 20-bit words
• total capacity = 81,920 bits or simply 4096 X 20 or 4K X 20 since 1K = 1024 =210
– 1M or 1 meg = 1,048,576 = 220
– 1G or 1 gig = 1,073,741,824 = 230
• Address – a number that identifies the location of a word in memory• Read Operation – the operation whereby a word stored in a specified
memory location is sensed and then transferred to another device.• Write Operation – the operation whereby a new word is placed or
stored into a particular memory location. • Volatile Memory – any type of memory that requires the application
of electrical power in order to store information. If the electrical power is removed, all information stored in the memory will be lost.
ECE 3450 M. A. Jupina, VU, 2010
Block Diagram of Memory
Read/Write Enable
Con
trol
B
us
ECE 3450 M. A. Jupina, VU, 2010
Each Word Location Has a Specific Binary Address
ECE 3450 M. A. Jupina, VU, 2010
1D Memory Architecture
Word 0
Word 1
Word 2
Word n-1
Word n-2
StorageCell
m bits
n w
ords
S0
S1
S2
S3
Sn-2
Sn-1
Input/Output
n words n select signals
Word 0
Word 1
Word 2
Word n-1
Word n-2
StorageCell
m bits
S0
S1
S2
S3
Sn-2
Sn-1
Input/Output
A0
A1
Ak-1 Dec
o de r
Decoder reduces # of inputsk = log2 n
ECE 3450 M. A. Jupina, VU, 2010
Illustration of the Write Operation
ECE 3450 M. A. Jupina, VU, 2010
Illustration of the Read Operation
ECE 3450 M. A. Jupina, VU, 2010
What is the capacity of a memory that has 16 address inputs, four data inputs, and four data outputs?
A certain memory stores 8K 16-bit words. How many data input and data output lines does it have? How many address lines does it have? What is its capacity in bytes?
216= 65,536 words = 64K.
Thus, memory capacity is 64K x 4.
Data input lines = 16; Data output lines = 16; Address lines = 13 (2N = 8192) Capacity in bytes = 16,384 ((8192x16)/8)
ECE 3450 M. A. Jupina, VU, 2010
2D Memory Architecture
A0
Row
Dec
oder
A1
Aj-1
bit line
word line
storage cell
Row
Add
ress
Col
umn
Add
ress
Aj
Aj+1
Ak-1
Column Decoder
2k-j
m x 2j
Input/Output (m bits)
selects appropriate word from memory row
ECE 3450 M. A. Jupina, VU, 2010
3D Memory ArchitectureR
ow
Add
rC
olum
n A
ddr
Blo
ck
Add
r
Input/Output (m bits)
Advantages: 1. Shorter word and/or bit lines 2. Block address activates only 1 block (saves power)
ECE 3450 M. A. Jupina, VU, 2010
The ROM Family
ECE 3450 M. A. Jupina, VU, 2010
Types of ROM• Mask programmed ROM (MROM)
– Photographic negative (mask) controls electrical interconnections– Economical only in high volume applications
• Programmable ROMs (PROMs)– Fusible links allow end users to program the device– Can only be programmed once– Economical for small volume applications
• Erasable programmable ROM (EPROM)– Can be erased and reprogrammed by user– UV light is used to clear the device– Entire device is cleared
• Electrically erasable PROM (EEPROM)– Voltage is used to clear memory– Individual bytes can be erased
• FLASH– Allows rapid in-circuit reprogramming of individual bytes
ECE 3450 M. A. Jupina, VU, 2010
16 X 8 ROM Example
ECE 3450 M. A. Jupina, VU, 2010
Example: Tables of Mathematical Functions Stored in ROMs
A1 A0 D3 D2 D1 D0
0 0 0 0 1 1
0 1 0 1 0 0
1 0 0 1 1 1
1 1 1 1 0 0
x 2 3y x
ECE 3450 M. A. Jupina, VU, 2010
Architecture of a 16 8 ROM
01
10
ECE 3450 M. A. Jupina, VU, 2010
Example: Function Generator Using a ROM and a DAC
TCLK
TSIGNAL
2 1
2
2 1
PP
N
OUT REFN
N
V V
V
Low PassFilter
ECE 3450 M. A. Jupina, VU, 2010
What clock frequency will result in a 100 Hz sine wave at the output?
What method could be used to vary the peak-to-peak amplitude of the sine wave?
100 256 25.6KHz
Adjust the reference voltage of the DAC.
ECE 3450 M. A. Jupina, VU, 2010
Typical Timing for a ROM Operation
ECE 3450 M. A. Jupina, VU, 2010
Structure of a MOS Mask-Programmed ROM (MROM)
One MOSFET is used for each memory cell. An open source connection stores a “0”; a closed source connection stores a “1.”
ECE 3450 M. A. Jupina, VU, 2010
Programmable ROMs (PROMs)
Fusible links are used that can be selectively blown open by the user to program a logic 0 into a cell
ECE 3450 M. A. Jupina, VU, 2010
Floating-Gate MOSFET
ECE 3450 M. A. Jupina, VU, 2010
Operation of a Floating Gate MOSFET
ECE 3450 M. A. Jupina, VU, 2010
Eraseable PROMs (EPROMs)
(a) Logic symbol for 27C64 EPROM(b) typical EPROM package showing ultraviolet window(c) 27C64 operating modes.
ECE 3450 M. A. Jupina, VU, 2010
Electrically Eraseable PROMs (EEPROMs)
(a) Symbol for the 2864 EEPROM(b) operating modes(c) timing for the write operation
ECE 3450 M. A. Jupina, VU, 2010
Flash Memory(a high density and low cost EEPROM with rapid erase and write times)
(a) Logic symbol for the 28F256A flash memory chip (b) control inputs CE, WE, and OE
ECE 3450 M. A. Jupina, VU, 2010
Trade-offs for semiconductor nonvolatile memories show that complexity and cost increase as erase and programming flexibility increase.
ECE 3450 M. A. Jupina, VU, 2010
The RAM Family
ECE 3450 M. A. Jupina, VU, 2010
Types of DRAM• FPM DRAM –Fast Page Mode, address one row and all
columns in that row before a new address is needed (this is a “page”). Saves time by allowing the same row address for several columns.
• EDO DRAM – Extended Data Output DRAM, next column is accessed before the external system accepts the current data. More speed
• BEDO DRAM - Burst Extended Data Output DRAM, up to four addressees to be internally generated from a single external address
• SDRAM – Synchronous DRAM –data transfer in “rapid-fire” bursts of several sequential memory locations.
• DDRSDRAM – Double Data Rate SDRAM – data transfers occur on both the rising and falling edges of the system clock.
• DRDRAM – Direct Rambus DRAM – Rambus, Inc.’s enhanced version of DDRSDRAM
ECE 3450 M. A. Jupina, VU, 2010
Memory Hierarchy in Computers
Speed (ns): .1 - 1 1 - 10 10 - 100
Size (bytes): K’s 10K’s M’s – G’s
Cost: highest lowest
ECE 3450 M. A. Jupina, VU, 2010
64
256
1,000
4,000
16,000
64,000
256,000
1,000,000
4,000,000
16,000,000
64,000,000
10
100
1000
10000
100000
1000000
10000000
100000000
1980 1983 1986 1989 1992 1995 1998 2001 2004 2007 2010
Year
Kbit
capa
city
/chi
p
Evolution in DRAM Chip Capacity
1.6-2.4 m
1.0-1.2 m
0.7-0.8 m
0.5-0.6 m
0.35-0.4 m
0.18-0.25 m
0.13 m
0.1 m
0.07 m
human memoryhuman DNA
encyclopedia2 hrs CD audio30 sec HDTV
book
page
4X growth every 3 years!
ECE 3450 M. A. Jupina, VU, 2010
Altera Flex 10K CPLD SRAM Example
I/O Element(IOE)
IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE
IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOERow
LocalInterconnect
Logic Element(LE)
Logic ArrayBlock (LAB)
EAB
EAB
Logic Array
EmbeddedArray Block(EAB)2K Bits RAM
Row
ECE 3450 M. A. Jupina, VU, 2010
FIFO SRAM Example
ECE 3450 M. A. Jupina, VU, 2010
Examples of the FIFO Register in Data-Rate Buffering Applications
ECE 3450 M. A. Jupina, VU, 2010
The 2147H 4K X 1 Static RAM Example
ECE 3450 M. A. Jupina, VU, 2010
2147H 4K X 1 SRAM Example
ECE 3450 M. A. Jupina, VU, 2010
A Single NMOS SRAM Cell (FF Circuit)
0
0
0 0 1
On Off
On On
1
1
0
Write
0
1
00 1
On Off
On On
1
0
1
Read
ECE 3450 M. A. Jupina, VU, 2010
Typical Timing for SRAM
ECE 3450 M. A. Jupina, VU, 2010
SRAM Timing Example
a) How long after the address lines stabilize will valid data appear at the outputs during a read cycle?
b) How long will output data remain valid after returns HIGH?
c) How many read operations can be performed per second?
d) How long should and be kept HIGH after the new address stabilizes during a write cycle?
e) What is the minimum time that input data must remain valid for a reliable write operation to occur?
f) How long must the address inputs remain stable after and return HIGH?
g) How many write operations can be performed per second?
100
100
70
30
100
20
40
10
20
RC
ACC
CO
OD
WC
AS
AH
W
DS
DH
t ns
t ns
t ns
t ns
t ns
t ns
t not given
t ns
t ns
t ns
Data Sheet Values
CS
CS/R W
CS/R W
ECE 3450 M. A. Jupina, VU, 2010
SRAM Timing Example Solution
100
100
70
30
100
20
40
10
20
RC
ACC
CO
OD
WC
AS
AH
W
DS
DH
t ns
t ns
t ns
t ns
t ns
t ns
t not given
t ns
t ns
t ns
Data Sheet Values
(a) tACC = 100ns (b) tOD = 30ns (c) tRC = 100ns; 1/100ns = 10 million(d) tAS = 20ns(e) tDS+tDH = 30ns(f) tAH = tWC - (tAS+ tW) = 40ns(g) tWC = 100ns; 1/100ns = 10 million
ECE 3450 M. A. Jupina, VU, 2010
Cell Arrangement in a 16K X 1 Dynamic RAM (DRAM)
ECE 3450 M. A. Jupina, VU, 2010
A MOS DRAM Cell
ECE 3450 M. A. Jupina, VU, 2010
Basic Operation of a DRAM Cell
ECE 3450 M. A. Jupina, VU, 2010
Simplified Architecture of the TMS44100 4M X 1 DRAM and RAS/CAS Timing
ECE 3450 M. A. Jupina, VU, 2010
Signal Activity for a Read Operation on a DRAM (The R/W input (not shown) is assumed to be HIGH)
ECE 3450 M. A. Jupina, VU, 2010
Signal Activity for a Write Operation on a DRAM
ECE 3450 M. A. Jupina, VU, 2010
One Scheme to Periodically Recharge (Refresh) the Memory Cell Capacitor
The RAS-only refresh method uses only the RAS signal to load the row address into the DRAM to refresh all cells in that row. The RAS-only refresh can be used to perform a burst refresh as shown. A refresh counter supplies the sequential row addresses from row 0 to row 1023 (for a 4M 1 DRAM).
ECE 3450 M. A. Jupina, VU, 2010
• SIMM – Single in-line memory modules that use 30 pin and 72pin configurations
• DIMM – Dual in-line memory modules uses 72 pin, 100 pin, 144 pin, and 168 pin configurations. DIMM capacity of 1 GB and higher are becoming more typical in 64 bit systems (not limited to 4 GB system memory any more).
SIMMs and DIMMs - DRAM Packaging
30 pin
72 pin
A SIMM or DIMM inserted into a socket on a system board.
ECE 3450 M. A. Jupina, VU, 2010
Comparison of the Types of Memories
ECE 3450 M. A. Jupina, VU, 2010
Memory Expansion
• Word-Length Expansion – one address addresses more than one Word
• Word-Capacity Expansion – address bits are increased
Three Groups of Lines (Buses) Connect the Main Memory ICs to the CPU
ECE 3450 M. A. Jupina, VU, 2010
ECE 3450 M. A. Jupina, VU, 2010
Combining Two 16 4 RAMs for a 16 8 Module
Control Bus {
ECE 3450 M. A. Jupina, VU, 2010
Combining Two 16 4 Chips for a 32 4 Memory
Control Bus {
ECE 3450 M. A. Jupina, VU, 2010
Four 2K 8 PROMs Arranged to Form a Total Capacity of 8K 8