ECE 272 Xilinx Tutorial

Workshop GoalsLearn how to use Xilinx to:

Draw a schematic

Create a symbol

Generate a testbench

Simulate your circuit

Getting Started Open Xilinx ISE (11)

Click File New Project

Create a new project directory titled “Workshop”

Name the project “Project1”

Select HDL as the top level source.

Device Properties

Create New SourceIn the Create New Source box, Click on New Source

Select Schematic from the box, and give it the file name “Schematic1”

Click next through the Create New Source window and the Add Existing Source window, then click finish.

Schematic CreationWe will be drawing this circuit:

To get started, take a look at the “Symbols” box on the left side of the Project Navigator window.

Adding Logic Gates Under Categories select logic

Under symbols, select the appropriate logic symbol Either AND2, XOR2, or OR2.

Click Add Symbol

Place each symbol in its proper place on the schematic.

Click Add Wire, and connect these logic gates as shown below.

Adding I/O Buffers Under Categories, select I/O

Under Symbols, select either IBUF or OBUF IBUF is for inputs, OBUF is for outputs.

Place these symbols, and connect to the logic gates with wires.

Add extra hanging wires on each of the buffers.

Defining Inputs and Outputs

Click on Add Net Name, and appropriately name the hanging wires A,B,C and Z. To do this, look at the Options box on the lower

left side of the window. Put the desired name in the “Name” box, then click on the branch you want to name.

Click on Add I/O Marker, select the input marker choice from the Options box, and add them to A, B and C.

Click on Add I/O Marker, select the output marker choice from the Options box, and add it to Z.

Final Schematic

Try writing up the truth table for this circuit. It will be useful when we simulate it later!

Creating a Circuit Symbol

Often times simple circuits like this are small parts of a larger, more complex circuit.

When building larger circuits, it is much easier to have the smaller sections represented by their own symbols.

We will next represent our logic circuit as a symbol with the same inputs and outputs.

Symbol Creation Click on Tools Symbol Wizard

Under Pin Name Source, select Using Schematic and make sure it is referencing the proper schematic (Schematic1

Click Next through the remaining boxes (all of the default values are fine).

If your symbol looks like the one below, click Finish.

Symbol Creation To make sure our symbol can be accessed in

future designs, go to Project New Source

Open a new schematic named “Schematic2”

Go to Categories in the symbols window and search for your project path (For example, mine was <C:/Workshop/Project1>)

Select the Schematic1 symbol and click on AddSymbol.

Does it appear correctly? If so, you are ready to incorporate your logic circuit into a larger design!

Circuit TestingBefore using any circuit in a larger design, it is important to make sure that it works correctly.

To test our circuit, we will create a file called a “testbench”. This file will take our logic circuit and

give it a series of inputs.We will then compare the outputs to the

truth table for the circuit, and see if it is working correctly.

Generating TestbenchClick on Project New Source

Select Verilog Test Fixture and name the file “Test1”

Select Schematic1 as the source to associate it with and click Next, then Finish.

Xilinx creates a Verilog Testbench file that we can use to test the circuit.

VerilogVerilog is an HDL (Hardware Description Language).

It is used to describe circuits in terms of the behavior of their components, how the wires connect them, etc.

Circuits described in Verilog are called modules.

This testbench is taking the Schematic1 module and treating it as the UUT (Unit Under Test).

The testebench is feeding the UUT inputs. Once we simulate this file, we can observe the output!!

Testbench ChangesRemove the line ‘ifdef auto_init

Change the line ‘endif to only say end

The lines of code between initial begin and end should appear like this:

Simulating TestbenchGo to the Design window on the left side and

change the selection on the Sources for drop-down menu to Behavioral Simulation.

Be sure you have your testbench selected as your process.

Right click on Simulate Behavioral Model and select Process Properties.

Change the simulation time to 100ns, then press OK

Double click on Simulate Behavioral Model

Simulation ResultsISim should open up and display your simulation results.

Does your waveform match mine?

Do the results of the simulation match what your logic table says should happen?

Questions!?