Lecture 5:

Spring 2021

1

ECE 2300Digital Logic & Computer Organization

Combinational Building Blocks

Lecture 5:

Announcements

2

• Lab 1 due today @ 11:59pm

• HW 2 to be posted on tonight

Lecture 5: 3

2-Input NOR Gate in CMOS

Lecture 5: 4

2-Input AND Gate in CMOS• CMOS gates produce inherent inversion• Need to add an inverter to a 2-Input NAND to

form AND gate

Lecture 5: 5

1 1 0 1

0 1 0 0

00 01 11 10

0

1

ABC

• Y = 1 if and only if A•B ≠ (B+C’)ABC Y000 1001 0010 1011 1100 1101 0110 0111 0

Canonical sumY = A’•B’•C’ + A’•B•C’ + A’•B•C + A•B’•C’

Recap: Two-Level Logic Minimization

Lecture 5: 6

Multi-Level Logic• So far we have primarily focused on two-level

representations for combinational logic

• Multi-level logic is typically more compact (i.e., cost-efficient) in practice

AB

CD E

Y = (A+B)(C’+D) + E’

Lecture 5: 7

Combinational Building Blocks• More complex functions built from basic gates

– Comparators – Parity checkers– Multiplexers – Decoders – Encoders …

• Typically tens to hundreds of transistors – Used to be called Medium Scale Integration (MSI)

• Common building blocks for digital systems

Lecture 5: 8

• XOR: – Similar to OR gate, except when inputs are 1– Used for comparisons, error checking, etc.

• XNOR: – Complemented version of XOR

XOR Gate

X Y XÅY (XÅY)’0 0 0 10 1 1 01 0 1 01 1 0 1

F=X•Y’+X’•Y

F=X’•Y’+X•Y

Lecture 5: 9

Equality Comparators Using XOR

XY

different1-bit comparator

4-bit comparator

A0B0A1B1A2B2A3B3

different

Lecture 5: 10

Parity Check Using XOR

1 if odd number of 1’s on input

• Generate Parity bit: signifies if the associated data has an even or odd number of 1’s– For N-input parity check, O(N) gates needed using

multi-level logic– In contrast, O(2N) gates required in two-level form

Lecture 5: 11

Multiplexer (“mux”)• Connects one of n inputs to the output

– select control signals pick one of the n sources• élog2nù select bits

• Useful when multiple data sources need to be routed to a single destination – Often arises from resource sharing– Example: select 1-of-n data inputs to an adder

Lecture 5:

2-to-1 Mux

12

• Selects one of two inputs to appear at the output

• Y = S’•I0 + S•I1

2-to-1 muxI1

I0S

Y

I1I0

S=1

Y = I1

I1I0

S=0

Y = I0

Lecture 5:

4-to-1 Mux

13

• Selects one of four inputsto appear at the output

• Y = S1’•S0’•I0 + S1’•S0•I1 +S1•S0’•I2 + S1•S0•I3

4-to-1 mux

I1I0 S1

Y

I3I2

S0

I1I0

I3I2

0 0

I1I0

I3I2

1 0

Lecture 5:

Cascading Multiplexers

14

• Large multiplexers can be implemented by cascading smaller ones

Y

? ? ?

4:1mux

2:1mux

2:1mux

2:1mux

I3I2

I5I4

I7I6

2:1mux

I1I0

Y

I7I6I5I4

S2

I3I2I1I0

S1 S0

4:1mux

4:1mux

2:1mux

8:1mux

Lecture 5: 15

• Any function of n variables can be implemented with a 2n:1 multiplexer

Logic Functions Using Muxes

– Input variables connected to select inputs– Data inputs tied to 0 or 1 according to truth table

00010111

CA B

01234567

S2

8:1 MUX

S1 S0

Y

ABC Y000 0001 0010 0011 1100 0101 1110 1111 1

Lecture 5:

Getting Away with a Smaller Mux

16

A B C D Y0 0 0 0 10 0 0 1 10 0 1 0 00 0 1 1 00 1 0 0 00 1 0 1 00 1 1 0 00 1 1 1 11 0 0 0 01 0 0 1 01 0 1 0 11 0 1 1 01 1 0 0 01 1 0 1 01 1 1 0 01 1 1 1 0

100

0

00

CA B

• Can use 2n-1:1 multiplexer and at most one inverter– Connect n-1 input

variables to select inputs

– Data inputs tied to 0, 1, nth variable, or inverted nth variable

D

D’

01234567

S2

8:1 MUX

S1 S0

Y

Lecture 5: 17

Decoder

A Y1 Y0

0 0 1

1 1 0

• Binary decoders – n inputs, 2n outputs – Each output corresponds to a unique input value – At most one output asserted at a time

• Example: A 1-to-2 decoder

Lecture 5: 18

2-to-4 Decoder

Y0 = A1’ ⦁A0’Y1 = A1’ ⦁A0

Y2 = A1 ⦁A0’Y3 = A1 ⦁A0

A1 A0

Y1

Y2

Y3

Y0

A1 A0 Y3 Y2 Y1 Y00 0 0 0 0 10 1 0 0 1 01 0 0 1 0 01 1 1 0 0 0

Y1Y2Y3

Y0

2:4 Decoder

11100100

A1A0

Lecture 5: 19

• n:2n decoder can be used to implement any function of n variables– Connect variables to inputs– Appropriate minterms

summed using extra gates to form the function

Logic Functions Using Decoders

B

DC

A

1514131211109876543210

4:16Decoder

I1

I3

I0

I2

ABCDABCD'ABC'DABC'D'AB'CDAB'CD'AB'C'DAB'C'D'A'BCDA'BCD'A'BC'DA'BC'D'A'B'CDA'B'CD'A'B'C'DA'B'C'D'

Lecture 5: 20

• F1 = A’B’C’D’ + AB’CD’ + ABC’D’• F2 = A’B’C’ + A’B’CD• F3 = A+B+C+D = (A’B’C’D’)’

F1

F2

F3

Logic Functions Using Decoders

B

DC

A

1514131211109876543210

4:16Decoder

I1

I3

I0

I2

ABCDABCD'ABC'DABC'D'AB'CDAB'CD'AB'C'DAB'C'D'A'BCDA'BCD'A'BC'DA'BC'D'A'B'CDA'B'CD'A'B'C'DA'B'C'D'

Lecture 5: 21

Decoder with Enable

E A1 A0 Y3 Y2 Y1 Y00 X X 0 0 0 01 0 0 0 0 0 11 0 1 0 0 1 01 1 0 0 1 0 01 1 1 1 0 0 0

X: don’t care inputHere 0XX covers four input combinations000, 001, 010, 011

Y1Y2Y3

Y0

2:4 Decoder

11100100

A1

A0

E

Lecture 5: 22

Decoder with Enable (2)

Y0 = A1’ ⦁A0’ ⦁EY1 = A1’ ⦁A0 ⦁EY2 = A1 ⦁A0’ ⦁EY3 = A1 ⦁A0 ⦁E

A1 A0

Y1

Y2

Y3

Y0

E

Lecture 5: 23

Encoders• Opposite of decoders

• Binary encoders: 2n inputs and n outputs

Decoder Encoder

Lecture 5: 24

4-to-2 Encoder

I3 I2 I1 I0 Y1 Y0

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

Exactly one input is asserted at any given time

I3

I2

I1

Y1

Y0

I3I2I1I0

Y0Y1

Lecture 5: 25

Priority Encoder• Highest numbered inputs have priority when

multiple inputs are asserted at the same time• Example: 4-to-2 priority encoder

I3 I2 I1 I0 Y1 Y0 None1 X X X 1 1 00 1 X X 1 0 00 0 1 X 0 1 00 0 0 1 0 0 00 0 0 0 0 0 1

Y1=I3+I3’I2=I3+I2Y0=I3+I3’I2’I1=I3+I2’I1 None=I3’I2’I1’I0’

I3I2I1I0

Y0Y1

None

Lecture 5: 26

Example: Microprocessor Interrupts• In order for devices to get service, they interrupt

the microprocessor

• Most important requests are given priority

power failuredisk error

I/O device requests Microprocessor

I7I6I5I4I3I2I1I0

Y2Y1Y0

None

8:3PriorityEncoder

Lecture 5: 27

Before Next Class• H&H 3.1-3.2

Next Time

Sequential Logic: Clocks, Latches, Flip-Flops