EC2207 Lab Manual

8/16/2019 EC2207 Lab Manual

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Om sakthi

ADHIPARASAKTHI ENGINEERING COLLEGEMELMARUVATHUR

DIGITAL ELECTRONICSLABORATORY MANUAL

(Fo III S!m!st! ECE"ACADEMIC YEAR #$$%&'$

P!a!) *+

M, M,THILAGAR- LECT.ECE/

Ms,R,KANCHANA- AP.ECE



S.N

o

Name of the experiment Pag

e

No

Mark

s

Sig

e

1 Study of logic gates.

2 Design and implementation of adders and subtractors using

logic gates.

3 Design and implementation of code conerters using logic

gates.

! Design and implementation of !"bit binary adder#subtractor

and $%D adder using &% '!(3.

) Design and implementation of 2"bit magnitude comparator

using logic gates* ("bit magnitude comparator using &% '!().

+ Design and implementation of 1+"bit odd#een parity checker#

generator using &% '!1(,.

'Design and implementation of multiplexer and demultiplexer

using logic gates and study of &% '!1), and &% '!1)!.

( Design and implementation of encoder and decoder using

logic gates and study of &% '!!) and &% '!1!'.

- Study of lip"lops.

1, %onstruction and eri/cation of !"bit ripple counter and Mod"

1,#Mod"12 ripple counter.

11 Design and implementation of 3"bit synchronous up#do0n

counter.

12 &mplementation of S&S* S&P* P&S and P&P shift registers

using ip"ops.

13 Design and implementation of $oolean unctions.

1! Simulation of adders and subtractors using erilog 4D5

soft0are.

1) Simulation of Multiplexer and De"multiplexer using erilog 4D5

soft0are.

1+ Simulation of !"bit ripple counter and mod"1,#mod"12 ripple

counter using erilog 4D5 soft0are.

1' Simulation of S&S* S&P* P&S and P&P shift registers using

erilog 4D5 soft0are.



SYLLABUS

1. Design and implementation of Adders and Subtractors using logic

gates.

2. Design and implementation of code converters using logic gates

(i) BCD to excess- code and voice versa

(ii) Binar! to gra! and vice-versa

. Design and implementation of " bit binar! Adder# subtractor and

BCD adder using $C %"&

". Design and implementation of 2Bit 'agnitude Comparator using

logic gates & Bit 'agnitude Comparator using $C %"&

. Design and implementation of 1 bit odd#even parit! c*ec+er

#generator using $C%"1&,.

. Design and implementation of 'ultiplexer and De-multiplexer using

logic gates and stud! of $C%"1, and $C %"1"

%. Design and implementation of encoder and decoder using logic

gates and stud! of $C%"" and $C%"1"%

&. Construction and verification of " bit ripple counter and 'od-1, #

'od-12 ipple counters

. Design and implementation of -bit s!nc*ronous up#do/n counter

1,. $mplementation of S$S0 S$0 $S0 and $0 s*ift registers using

3lip- flops.

11. Design of experiments 1& and 1, using 4erilog 5ard/are

Description 6anguage



LIST OF EXPERIMENTS

1. Stud! of logic gates.

2. Design and implementation of adders and subtractors using logic

gates.

. Design and implementation of code converters using logic gates.

". Design and implementation of "-bit binar! adder#subtractor and

BCD adder using $C %"&.

. Design and implementation of 2-bit magnitude comparator using

logic gates &-bit magnitude comparator using $C %"&.

. Design and implementation of 1-bit odd#even parit! c*ec+er#

generator using $C %"1&,.

%. Design and implementation of multiplexer and demultiplexer

using logic gates and stud! of $C %"1, and $C %"1".

&. Design and implementation of encoder and decoder using logic

gates and stud! of $C %"" and $C %"1"%.

. Stud! of 3lip-3lops.

1,. Construction and verification of "-bit ripple counter and 'od- 1,#'od-12 ripple counter.

11. Design and implementation of -bit s!nc*ronous up#do/n

counter.

12. $mplementation of S$S0 S$0 $S0 and $0 s*ift registers

using flip-flops.

1. Design and implementation of Boolean 3unctions.



HDL PROGRAMS

1". Simulation of adders and subtractors using 4erilog 5D6

soft/are.

1. Simulation of 'ultiplexer and De-multiplexer using 4erilog 5D6

soft/are.

1. Simulation of "-bit ripple counter and mod-1,#mod-12 ripple

counter using 4erilog 5D6 soft/are.

1%. Simulation of S$S0 S$0 $S0 and $0 s*ift registers using

4erilog 5D6 soft/are.



EXPT NO.1

STUDY OF LOGIC GATES

AIM:

To study about logic gates and verify their truth tables.

COMPONENTS REQUIRED:

THEORY:

Circuit that takes the logical decision and the process are called logic

gates. Each gate has one or more input and only one output.

OR, AN and NOT are basic gates. NAN, NOR and !"OR are

kno#n as universal gates. $asic gates form these gates.

AND GATE:

The AN gate performs a logical multiplication commonly kno#n as

AN function. The output is high #hen both the inputs are high. The output

is lo# level #hen any one of the inputs is lo#.

OR GATE:

%& No. CO'(ONENT %(EC)*)CAT)ON +T

-. AN ATE )C /012 -

3. OR ATE )C /043 -

4. NOT ATE )C /010 -

0. NAN ATE 3 )5( )C /011 -

6. NOR ATE )C /013 -7. !"OR ATE )C /027 -

/. NAN ATE 4 )5( )C /0-1 -

2. &E " 4

8. RE%)%TOR 3319 4



The OR gate performs a logical addition commonly kno#n as OR

function. The output is high #hen any one of the inputs is high. The output

is lo# level #hen both the inputs are lo#.

NOT GATE:

The NOT gate is called an inverter. The output is high #hen the

input is lo#. The output is lo# #hen the input is high.

NAND GATE:

The NAN gate is a contraction of AN"NOT. The output is high

#hen both inputs are lo# and any one of the input is lo# .The output is lo#

level #hen both inputs are high.

NOR GATE:

The NOR gate is a contraction of OR"NOT. The output is high #hen

both inputs are lo#. The output is lo# #hen one or both inputs are high.

X-OR GATE:

The output is high #hen any one of the inputs is high. The output is

lo# #hen both the inputs are lo# and both the inputs are high.

AND GATE:



SYMBOL: PIN DIAGRAM:

OR GATE:

NOT GATE:




X-OR GATE :

SYMBOL : PIN DIAGRAM :

2-INPUT NAND GATE:




3-INPUT NAND GATE :

NOR GATE:





PROCEDURE:

i: Connections are given as per circuit diagram.

ii: &ogical inputs are given as per circuit diagram.

iii: Observe the output and verify the truth table

RESULT:

Thus the Truth tables for logic gates are verified successfully.



EXPT NO : 2

DESIGN OF ADDER AND SUBTRACTOR

AIM:

To design and construct half adder, full adder, half subtractor and full

subtractor circuits and verify the truth table using logic gates.


%l.No.

CO'(ONENT %(EC)*)CAT)ON +T.

-. AN ATE )C /012 -

3. !"OR ATE )C /027 -

4. NOT ATE )C /010 -

0. OR ATE )C /043 -4. &E " 4

0. RE%)%TOR 3319 4

THEORY:

HALF ADDER:

A half adder has t#o inputs for the t#o bits to be added and t#o

outputs one from the sum ; %< and other from the carry ; c< into the higher adder position. Above circuit is called as a carry signal from the addition of

the less significant bits sum from the !"OR ate the carry out from the

AN gate.

FULL ADDER:

A full adder is a combinational circuit that forms the arithmetic sum of

input= it consists of three inputs and t#o outputs. A full adder is useful to addthree bits at a time but a half adder cannot do so. )n full adder sum output

#ill be taken from !"OR ate, carry output #ill be taken from OR ate.

HALF SUBTRACTOR:



The half subtractor is constructed using !"OR and AN ate. The

half subtractor has t#o input and t#o outputs. The outputs are difference and

borro#. The difference can be applied using !"OR ate, borro# output can

be implemented using an AN ate and an inverter.

FULL SUBTRACTOR:

The full subtractor is a combination of !"OR, AN, OR, NOT ates.

)n a full subtractor the logic circuit should have three inputs and t#o outputs.

The t#o half subtractor put together gives a full subtractor .The first half

subtractor #ill be C and A $. The output #ill be difference output of fullsubtractor. The e>pression A$ assembles the borro# output of the half

subtractor and the second term is the inverted difference output of first !"

OR.

LOGIC DIAGRAM:



HALF ADDER

TRUTH TABLE:

A B CARRY SUM

0

0

1

1

0

1

0

1

0

0

0

1

0

1

1

0

K-Ma !"# SUM: K-Ma !"# CARRY:

SUM $ A%B & AB% CARRY $ AB

LOGIC DIAGRAM:



FULL ADDER

FULL ADDER USING T'O HALF ADDER

TRUTH TABLE:

A B C CARRY SUM0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

0

0

1

0

1

1

1

0

1

1

0

1

0

0

1

K-Ma !"# SUM: K-Ma !"# CARRY:

SUM $ A%B%C & A%BC% & ABC% & ABC CARRY $ AB & BC & AC



LOGIC DIAGRAM:

HALF SUBTRACTOR

TRUTH TABLE:

A B BORRO' DIFFERENCE

0

0

1

1

0

1

0

1

0

1

0

0

0

1

1

0

K-Ma !"# DIFFERENCE:

DIFFERENCE $ A%B & AB%

K-Ma !"# BORRO':

BORRO' $ A%B



LOGIC DIAGRAM:

FULL SUBTRACTOR

FULL SUBTRACTOR USING T'O HALF SUBTRACTOR:

TRUTH TABLE:

A B C BORRO' DIFFERENCE

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

1

1

0

0

0

1

0

1

1

0

1

0

0

1



K-Ma !"# D(!!)#)*+):

D(!!)#)*+) $ A%B%C & A%BC% & AB%C% & ABC

K-Ma !"# B"##",:

B"##", $ A%B & BC & A%C





EXPT NO : 3

DESIGN AND IMPLEMENTATION OF CODE CONERTOR

AIM:

To design and implement 0"bit?i: $inary to gray code converter

?ii: ray to binary code converter

?iii: $C to e>cess"4 code converter

?iv: E>cess"4 to $C code converter


%.No. CO'(ONENT %(EC)*)CAT)ON +T.

-. !"OR ATE )C /027 -3. AN ATE )C /012 -

4. OR ATE )C /043 -

0. NOT ATE )C /010 -

6. &E " 6

7. RE%)%TOR 3319 6

THEORY:

The availability of large variety of codes for the same discrete

elements of information results in the use of different codes by different

systems. A conversion circuit must be inserted bet#een the t#o systems if

each uses different codes for same information. Thus, code converter is a

circuit that makes the t#o systems compatible even though each uses

different binary code.

The bit combination assigned to binary code to gray code. %ince each

code uses four bits to represent a decimal digit. There are four inputs and

four outputs. ray code is a non"#eighted code.

The input variable are designated as $4, $3, $-, $1 and the output

variables are designated as C4, C3, C-, Co. from the truth table,



combinational circuit is designed. The $oolean functions are obtained from

@"'ap for each output variable.

A code converter is a circuit that makes the t#o systems compatible

even though each uses a different binary code. To convert from binary code

to E>cess"4 code, the input lines must supply the bit combination of

elements as specified by code and the output lines generate the

corresponding bit combination of code. Each one of the four maps represents

one of the four outputs of the circuit as a function of the four input variables.

A t#o"level logic diagram may be obtained directly from the $oolean

e>pressions derived by the maps. These are various other possibilities for a

logic diagram that implements this circuit. No# the OR gate #hose output is

C has been used to implement partially each of three outputs.



LOGIC DIAGRAM:

BINARY TO GRAY CODE CONERTOR

K-Ma !"# G3:

G3 $ B3



K-Ma !"# G2:

K-Ma !"# G1:

K-Ma !"# G0:



TRUTH TABLE:

B(*a#/ (* G#a/ +") "

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

0

0

01

1

1

1

1

1

1

1

0

0

0

0

1

1

1

10

0

0

0

1

1

1

1

0

0

1

1

0

0

1

10

0

1

1

0

0

1

1

0

1

0

1

0

1

0

10

1

0

1

0

1

0

1

0

0

0

0

0

0

0

01

1

1

1

1

1

1

1

0

0

0

0

1

1

1

11

1

1

1

0

0

0

0

0

0

1

1

1

1

0

00

0

1

1

1

1

0

0

0

1

1

0

0

1

1

00

1

1

0

0

1

1

0



LOGIC DIAGRAM:

GRAY CODE TO BINARY CONERTOR

K-Ma !"# B3:

B3 $ G3



K-Ma !"# B2:

K-Ma !"# B1:



K-Ma !"# B0:

TRUTH TABLE:

G#a/ C") B(*a#/ C")

G3 G2 G1 G0 B3 B2 B1 B0

00

0

0

0

0

0

0

1

1

11

1

1

1

1

00

0

0

1

1

1

1

1

1

11

0

0

0

0

00

1

1

1

1

0

0

0

0

11

1

1

0

0

01

1

0

0

1

1

0

0

1

10

0

1

1

0

00

0

0

0

0

0

0

1

1

11

1

1

1

1

00

0

0

1

1

1

1

0

0

00

1

1

1

1

00

1

1

0

0

1

1

0

0

11

0

0

1

1

01

0

1

0

1

0

1

0

1

01

0

1

0

1



LOGIC DIAGRAM:

BCD TO EXCESS-3 CONERTOR

K-Ma !"# E3:

E3 $ B3 & B2 B0 & B14



K-Ma !"# E2:

K-Ma !"# E1:



K-Ma !"# E0:

TRUTH TABLE:

BCD (* E5+)66 7 3 "

B3 B2 B1 B0 G3 G2 G1 G0

0

00

0

0

0

0

0

1

1

11

1

1

1

1

0

00

0

1

1

1

1

0

0

00

1

1

1

1

0

01

1

0

0

1

1

0

0

11

0

0

1

1

0

10

1

0

1

0

1

0

1

01

0

1

0

1

0

00

0

0

1

1

1

1

1

55

5

5

5

5

0

11

1

1

0

0

0

0

1

55

5

5

5

5

1

00

1

1

0

0

1

1

0

55

5

5

5

5

1

01

0

1

0

1

0

1

0

55

5

5

5

5



LOGIC DIAGRAM:

EXCESS-3 TO BCD CONERTOR



K-Ma !"# A:

A $ X1 X2 & X3 X8 X1

K-Ma !"# B:



K-Ma !"# C:

K-Ma !"# D:



TRUTH TABLE:

E5+)66 7 3 I* BCD O

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

1

1

1

11

0

1

1

1

1

0

0

0

01

1

0

0

1

1

0

0

1

10

1

0

1

0

1

0

1

0

10

0

0

0

0

0

0

0

0

11

0

0

0

0

1

1

1

1

00

0

0

1

1

0

0

1

1

00

0

1

0

1

0

1

0

1

01

PROCEDURE:



?i: Connections #ere given as per circuit diagram.

?ii: &ogical inputs #ere given as per truth table

?iii: Observe the logical output and verify #ith the truth tables.

RESULT:

Thus the design and implementation of follo#ing code converters are

done.

-. $inary to gray code converter

3. ray to binary code converter

4. $C to e>cess"4 code converter

0. E>cess"4 to $C code converter



EXPT NO : 8

DESIGN OF 8-BIT ADDER AND SUBTRACTOR

AIM: To design and implement 0"bit adder and subtractor using )C /024.


%l.No. CO'(ONENT %(EC)*)CAT)ON +T.

-. )C )C /024 -

3. E!"OR ATE )C /027 -

4. NOT ATE )C /010 -

4. &E " 6

0. RE%)%TOR 3319 6

THEORY:

8 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum of

t#o binary numbers. )t can be constructed #ith full adders connected in

cascade, #ith the output carry from each full adder connected to the inputcarry of ne>t full adder in chain. The augends bits of ;A< and the addend bits

of ;$< are designated by subscript numbers from right to left, #ith subscript

1 denoting the least significant bits. The carries are connected in chain

through the full adder. The input carry to the adder is C 1 and it ripples

through the full adder to the output carry C0.

8 BIT BINARY SUBTRACTOR:

The circuit for subtracting A"$ consists of an adder #ith inverters,

placed bet#een each data input ;$< and the corresponding input of full adder.

The input carry C1 must be eBual to - #hen performing subtraction.



8 BIT BINARY ADDER9SUBTRACTOR:

The addition and subtraction operation can be combined into one

circuit #ith one common binary adder. The mode input ' controls the

operation. hen 'D1, the circuit is adder circuit. hen 'D-, it becomes

subtractor.

8 BIT BCD ADDER:

Consider the arithmetic addition of t#o decimal digits in $C,

together #ith an input carry from a previous stage. %ince each input digit

does not e>ceed 8, the output sum cannot be greater than -8, the - in the sum

being an input carry. The output of t#o decimal digits must be represented in

$C and should appear in the form listed in the columns.

A$C adder that adds 3 $C digits and produce a sum digit in $C.

The 3 decimal digits, together #ith the input carry, are first added in the top

0 bit adder to produce the binary sum.

PIN DIAGRAM FOR IC 8;3:





LOGIC DIAGRAM:

8-BIT BINARY SUBTRACTOR



LOGIC DIAGRAM:

8-BIT BINARY ADDER9SUBTRACTOR



TRUTH TABLE:

I* Daa A I* Daa B A(("* S<#a+("*

A8 A3 A2 A1 B8 B3 B2 B1 C S8 S3 S2 S1 B D8 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1



PROCEDURE:

?i: Connections #ere given as per circuit diagram.

?ii: &ogical inputs #ere given as per truth table

?iii: Observe the logical output and verify #ith the truth tables.

RESULT:

Thus the design and implementation of 0"bit adder and

subtractor are done using )C /024.



EXPT NO : =

DESIGN AND IMPLEMENTATION OF MAGNITUDE

COMPARATORS

AIM:

To design and implement

?i: 3 bit magnitude comparator using basic gates.

?ii: 2 bit magnitude comparator using )C /026.

APPARATUS REQUIRED:


-. AN ATE )C /012 3

3. !"OR ATE )C /027 -

4. OR ATE )C /043 -

0. NOT ATE )C /010 -

6. 0"$)T 'AN)TFE

CO'(ARATOR

)C /026 3

7. &E " 6

/. RE%)%TOR 3319 6

THEORY:

The comparison of t#o numbers is an operator that determine one

number is greater than, less than ?or: eBual to the other number. A magnitude

comparator is a combinational circuit that compares t#o numbers A and $

and determine their relative magnitude. The outcome of the comparator is

specified by three binary variables that indicate #hether AG$, AD$ ?or:

AH$.

A D A4 A3 A- A1



$ D $4 $3 $- $1

The eBuality of the t#o numbers and $ is displayed in a

combinational circuit designated by the symbol ?AD$:.

This indicates A greater than $, then inspect the relative magnitude of

pairs of significant digits starting from most significant position. A is 1 and

that of $ is 1.

e have AH$, the seBuential comparison can be e>panded as

AG$ D A4$4- !4A3$3

- !4!3A-$-- !4!3!-A1$1

-

AH$ D A4-$4 !4A3

-$3 !4!3A--$- !4!3!-A1

-$1

The same circuit can be used to compare the relative magnitude of

t#o $C digits.

here, A D $ is e>panded as,

A D $ D ?A4 $4: ?A3 $3: ?A- $-: ?A1 $1:

>4 >3 >- >1



LOGIC DIAGRAM:

2 BIT MAGNITUDE COMPARATOR



K MAP



TRUTH TABLE





TRUTH TABLE:

A B A>B A$B A?B

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0

0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1

PROCEDURE:

?i: Connections are given as per circuit diagram.

?ii: &ogical inputs are given as per circuit diagram.

?iii: Observe the output and verify the truth table.



RESULT:

Thus the design and )mplementation of 'agnitude comparators

are done and the results are verified



EXPT NO :@

1@ BIT ODD9EEN PARITY CHECKER 9GENERATOR

AIM:

To design and implement -7 bit odd5even parity checker generator

using )C /0-21.


%l.No.


-. NOT ATE )C /010 -

-. (AR)T NR5CIR )C /0-21 3

3. &E " 6

4. RE%)%TOR 3319 6

THEORY:

A parity bit is used for detecting errors during transmission of binary

information. A parity bit is an e>tra bit included #ith a binary message to

make the number is either even or odd. The message including the parity bit

is transmitted and then checked at the receiver ends for errors. An error is

detected if the checked parity bit doesn<t correspond to the one transmitted.

The circuit that generates the parity bit in the transmitter is called a ;parity

generator< and the circuit that checks the parity in the receiver is called a

;parity checker<.

)n even parity, the added parity bit #ill make the total number is even

amount. )n odd parity, the added parity bit #ill make the total number is odd

amount. The parity checker circuit checks for possible errors in the

transmission. )f the information is passed in even parity, then the bits

reBuired must have an even number of -<s. An error occur during



transmission, if the received bits have an odd number of -<s indicating that

one bit has changed in value during transmission.

PIN DIAGRAM FOR IC 81;0:



FUNCTION TABLE:

INPUTS OUTPUTS

N<)# "! H( Daa

I*6 I0 7 I4

PE PO E JO

EEN 1 0 1 0

ODD 1 0 0 1

EEN 0 1 0 1

ODD 0 1 1 0

X 1 1 0 0

X 0 0 1 1



LOGIC DIAGRAM:

1@ BIT ODD9EEN PARITY CHECKER

TRUTH TABLE:

I I@ I= I8 I3 I2 I1 I0 I%I@%I=%I8%I3%I2%11% I0% A+() E O

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 00 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 0

0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 1



LOGIC DIAGRAM:

1@ BIT ODD9EEN PARITY GENERATOR

TRUTH TABLE:

I I@ I= I8 I3 I2 I1 I0 I I@ I= I8 I3 I2 I1 I0 A+() E O

1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0

1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1

1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0



reBuired must have an even number of -<s. An error occur during

transmission, if the received bits have an odd number of -<s indicating that

one bit has changed in value during transmission.

PROCEDURE:




RESULT:

Thus the implementation of (arity generator5checker circuit

#as done and the truth table are verified.



EXPT NO :

DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND

DEMULTIPLEXER

AIM:

To design and implement multiple>er and demultiple>er using logic

gates and study of )C /0-61 and )C /0-60.

APPARATUS REQUIRED:


-. 4 )5( AN ATE )C /0-- 3

3. OR ATE )C /043 -

4. NOT ATE )C /010 -

0. &E " 6

6. RE%)%TOR 3319 6

THEORY:

MULTIPLEXER:

'ultiple>er means transmitting a large number of information unitsover a smaller number of channels or lines. A digital multiple>er is a

combinational circuit that selects binary information from one of many input

lines and directs it to a single output line. The selection of a particular input

line is controlled by a set of selection lines. Normally there are 3n input line

and n selection lines #hose bit combination determine #hich input is

selected.

DEMULTIPLEXER:

The function of emultiple>er is in contrast to multiple>er function. )t

takes information from one line and distributes it to a given number of



output lines. *or this reason, the demultiple>er is also kno#n as a data

distributor. ecoder can also be used as demultiple>er.

)n the -K 0 demultiple>er circuit, the data input line goes to all of the

AN gates. The data select lines enable only one gate at a time and the data

on the data input line #ill pass through the selected gate to the associated

data output line.



BLOCK DIAGRAM FOR 8:1 MULTIPLEXER:

FUNCTION TABLE:

S1 S0 INPUTS Y

0 0 D0 D0 S1% S0%

0 1 D1 D1 S1% S0

1 0 D2 D2 S1 S0%

1 1 D3 D3 S1 S0

Y $ D0 S1% S0% & D1 S1% S0 & D2 S1 S0% & D3 S1 S0

CIRCUIT DIAGRAM FOR MULTIPLEXER:



TRUTH TABLE:

S1 S0 Y $ OUTPUT

0 0 D0

0 1 D1

1 0 D2

1 1 D3

BLOCK DIAGRAM FOR 1:8 DEMULTIPLEXER:



FUNCTION TABLE:

S1 S0 INPUT

0 0 X D0 $ X S1% S0%

0 1 X D1 $ X S1% S0

1 0 X D2 $ X S1 S0%

1 1 X D3 $ X S1 S0

Y $ X S1% S0% & X S1% S0 & X S1 S0% & X S1 S0

LOGIC DIAGRAM FOR DEMULTIPLEXER:



TRUTH TABLE:

INPUT OUTPUT

S1 S0 I9P D0 D1 D2 D3

0 0 0 0 0 0 00 0 1 1 0 0 0

0 1 0 0 0 0 0

0 1 1 0 1 0 0

1 0 0 0 0 0 0

1 0 1 0 0 1 0

1 1 0 0 0 0 0

1 1 1 0 0 0 1

PIN DIAGRAM FOR IC 81=0:



PIN DIAGRAM FOR IC 81=8:

PROCEDURE:






RESULT:

Thus the design and implementation of 'ultiple>er and

emultiple>er circuit are done using logic gates.



EXPT NO : ;

DESIGN AND IMPLEMENTATION OF ENCODER AND DECODER

AIM:

To design and implement encoder and decoder using logic gates and

study of )C /006 and )C /0-0/.



-. 4 )5( NAN ATE )C /0-1 3

3. OR ATE )C /043 4

4. NOT ATE )C /010 -

3. &E " 6

4. RE%)%TOR 3319 6

THEORY:

ENCODER:An encoder is a digital circuit that perform inverse operation of a

decoder. An encoder has 3n input lines and n output lines. )n encoder the

output lines generates the binary code corresponding to the input value. )n

octal to binary encoder it has eight inputs, one for each octal digit and three

output that generate the corresponding binary code. )n encoder it is assumed

that only one input has a value of one at any given time other#ise the circuit

is meaningless. )t has an ambiguila that #hen all inputs are Lero the outputs

are Lero. The Lero outputs can also be generated #hen 1 D -.



DECODER:

A decoder is a multiple input multiple output logic circuit #hich

converts coded input into coded output #here input and output codes are

different. The input code generally has fe#er bits than the output code. Each

input code #ord produces a different output code #ord i.e there is one to one

mapping can be e>pressed in truth table. )n the block diagram of decoder

circuit the encoded information is present as n input producing 3n possible

outputs. 3n output values are from 1 through out 3n -.



PIN DIAGRAM FOR IC 88=:

BCD TO DECIMAL DECODER:

PIN DIAGRAM FOR IC 818:



LOGIC DIAGRAM FOR ENCODER:

TRUTH TABLE:INPUT OUTPUT

Y1 Y2 Y3 Y8 Y= Y@ Y A B C

1 0 0 0 0 0 0 0 0 1

0 1 0 0 0 0 0 0 1 0

0 0 1 0 0 0 0 0 1 1

0 0 0 1 0 0 0 1 0 0

0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 1 1 1 1

LOGIC DIAGRAM FOR DECODER:



TRUTH TABLE:

INPUT OUTPUT

E A B D0 D1 D2 D3

1 0 0 1 1 1 1

0 0 0 0 1 1 1

0 0 1 1 0 1 1

0 1 0 1 1 0 1

0 1 1 1 1 1 0

PROCEDURE:






RESULT:

Thus the design and implementation of encoder and decoder are

done using logic gates.

EXPT NO : 8

STUDY OF FLIP FLOPS

AIM:

To %tudy the follo#ing *lip *lops R% *lip *lop, *lip *lop, M@ *lip

*lop.




%.No. Components Range +uantity

-. NAN ate )C /011 -

)C /0-1 -3. &ock (ulse enerator " -

4. &E " 3

0. Resistor 331 3

THEORY:

A *lip"*lop is a device #hich can store a binary bit indefinitely until

directed by an input signal to s#itch ON. e can differentiate among

various types of *lip *lop by the number of inputs they possess and in the

manner in #hich an input affect the binary state.

RS F( F": )t consists of a basic *lip *lop circuit #ith t#o additional

NAN ates. hen %et input is - output changes from 1 to -. )f reset input

is - output #ill reset to Lero. hen the both inputs are - output #ill be

indeterminate.

.

D- F( F": One #ay to eliminate the undesirable condition of the

indeterminate state in the R% *lip *lop is to ensure that inputs % and R are



never eBual to - at the same time. The input goes directly to the % input

and its complement is applied at the R input.

K F( F": )t is a refinement of the R% *lip *lop in that indeterminate

state of the R% type is defined in the M@ *lip *lop. hen the both the inputs

of M and @ are eBual to - it s#itches to its complement state.



RS FLIP FLOP

L"(+a D(a#a



T# Ta<)

Q S R Q&14

1 1 1 1

1 1 - 1

1 - 1 -

1 - - indeterminate

- 1 1 -

- 1 - 1

- - 1 -

- - - indeterminate

Ca#a+)#(6(+ Ea("*

D FLIP FLOP



T# Ta<) Ca#a+)#(6(+ Ea("*

K FLIP FLOP



T# Ta<) Ca#a+)#(6(+ Ea("*



K F( F": )t is a refinement of the R% *lip *lop in that indeterminate

state of the R% type is defined in the M@ *lip *lop. hen the both the inputs

of M and @ are eBual to - it s#itches to its complement state.

PROCEDURE:

-. Construct the circuit for all the flip flops as sho#n.

3. Apply the input to the circuit as per the table.

4. erify the results #ith the table.

RESULT:

Thus the flip flops are studied and verified #ith the truth table.



EXPT NO :10

CONSTRUCTION AND ERIFICATION OF 8 BIT RIPPLE

COUNTER AND MOD 109MOD 12 RIPPLE COUNTER

AIM:

To design and verify 0 bit ripple counter mod -15 mod -3 ripple

counter.



-. M@ *&)( *&O( )C /0/7 3

3. NAN ATE )C /011 -

4. &E " 60. RE%)%TOR 3319 6

THEORY:

A counter is a register capable of counting number of clock pulse

arriving at its clock input. Counter represents the number of clock pulses

arrived. A specified seBuence of states appears as counter output. This is the

main difference bet#een a register and a counter. There are t#o types of counter, synchronous and asynchronous. )n synchronous common clock is

given to all flip flop and in asynchronous first flip flop is clocked by e>ternal

pulse and then each successive flip flop is clocked by + or + output of

previous stage. A soon the clock of second stage is triggered by output of

first stage. $ecause of inherent propagation delay time all flip flops are not

activated at same time #hich results in asynchronous operation.



PIN DIAGRAM FOR IC 8@:

LOGIC DIAGRAM FOR 8 BIT RIPPLE COUNTER:



TRUTH TABLE:

CLK QA QB QC QD

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 1 1 0 0

8 0 0 1 0

= 1 0 1 0

@ 0 1 1 0 1 1 1 0

; 0 0 0 1

J 1 0 0 1

10 0 1 0 1

11 1 1 0 1

12 0 0 1 1



13 1 0 1 1

18 0 1 1 1

1= 1 1 1 1

LOGIC DIAGRAM FOR MOD - 10 RIPPLE COUNTER:

TRUTH TABLE:

CLK QA QB QC QD

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 1 1 0 0

8 0 0 1 0





PROCEDURE:




RESULT:

Thus the design and implementation of 0 bit ripple counter and

mod -15 mod -3 ripple counter are done.



EXPT NO. :11

DESIGN AND IMPLEMENTATION OF 3 BIT SYNCHRONOUS

UP9DO'N COUNTER

AIM:

To design and implement 4 bit synchronous up5do#n counter.


%l.No.


-. M@ *&)( *&O( )C /0/7 3

3. 4 )5( AN ATE )C /0-- -

4. OR ATE )C /043 -

0. !OR ATE )C /027 -

6. NOT ATE )C /010 -

7. &E " 6

/. RE%)%TOR 3319 6

THEORY:

A counter is a register capable of counting number of clock pulsearriving at its clock input. Counter represents the number of clock pulses

arrived. An up5do#n counter is one that is capable of progressing in

increasing order or decreasing order through a certain seBuence. An up5do#n

counter is also called bidirectional counter. Fsually up5do#n operation of the

counter is controlled by up5do#n signal. hen this signal is high counter

goes through up seBuence and #hen up5do#n signal is lo# counter follo#s

reverse seBuence.

K MAP



STATE DIAGRAM:

CHARACTERISTICS TABLE:



Q Q&1 K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

LOGIC DIAGRAM:

TRUTH TABLE:

I*

U9D",*

P#)6)* Sa)

QA QB QC

N)5 Sa)

QA&1 Q B&1 QC&1

A

A K A

B

B K B

C

C K C

0 0 0 0 1 1 1 1 X 1 X 1 X



0 1 1 1 1 1 0 X 0 X 0 X 1

0 1 1 0 1 0 1 X 0 X 1 1 X

0 1 0 1 1 0 0 X 0 0 X X 1

0 1 0 0 0 1 1 X 1 1 X 1 X

0 0 1 1 0 1 0 0 X X 0 X 10 0 1 0 0 0 1 0 X X 1 1 X

0 0 0 1 0 0 0 0 X 0 X X 1

1 0 0 0 0 0 1 0 X 0 X 1 X

1 0 0 1 0 1 0 0 X 1 X X 1

1 0 1 0 0 1 1 0 X X 0 1 X

1 0 1 1 1 0 0 1 X X 1 X 1

1 1 0 0 1 0 1 X 0 0 X 1 X

1 1 0 1 1 1 0 X 0 1 X X 1

1 1 1 0 1 1 1 X 0 X 0 1 X

1 1 1 1 0 0 0 X 1 X 1 X 1

PROCEDURE:






RESULT:

Thus the design and implementation of 4 bit synchronous

up5do#n counter is done.

EXPT NO : 12

DESIGN AND IMPLEMENTATION OF SHIFT REGISTER

AIM:

To design and implement

?i: %erial in serial out

?ii: %erial in parallel out



?iii: (arallel in serial out

?iv: (arallel in parallel out



-. *&)( *&O( )C /0/0 3

3. OR ATE )C /043 -

4. &E " 6

0. RE%)%TOR 3319 6

THEORY:A register is capable of shifting its binary information in one or both

directions is kno#n as shift register. The logical configuration of shift

register consist of a "*lip flop cascaded #ith output of one flip flop

connected to input of ne>t flip flop. All flip flops receive common clock

pulses #hich causes the shift in the output of the flip flop. The simplest

possible shift register is one that uses only flip flop. The output of a given

flip flop is connected to the input of ne>t flip flop of the register. Each clock

pulse shifts the content of register one bit position to right.

PIN DIAGRAM:



LOGIC DIAGRAM:

SERIAL IN SERIAL OUT:

TRUTH TABLE:

CLK S)#(a (* S)#(a "

1 1 0

2 0 0

3 0 0

8 1 1

= X 0

@ X 0

X 1

LOGIC DIAGRAM:

SERIAL IN PARALLEL OUT:



TRUTH TABLE:

CLK DATA

OUTPUT

QA QB QC QD

1 1 1 0 0 0

2 0 0 1 0 0

3 0 0 0 1 1

8 1 1 0 0 1

LOGIC DIAGRAM:

PARALLEL IN SERIAL OUT:



TRUTH TABLE:CLK Q3 Q2 Q1 Q0 O9P

0 1 0 0 1 1

1 0 0 0 0 0

2 0 0 0 0 0

3 0 0 0 0 1

LOGIC DIAGRAM:

PARALLEL IN PARALLEL OUT:



TRUTH TABLE:

CLK

DATA INPUT OUTPUTDA DB DC DD QA QB QC QD

1 1 0 0 1 1 0 0 1

2 1 0 1 0 1 0 1 0

PROCEDURE:






RESULT:

Thus the design and implementation of follo#ing shift registers

are done.

-. %erial in serial out

3. %erial in parallel out

4. (arallel in serial out

0. (arallel in parallel out

EX.NO : 13

IMPLEMENTATION OF BOOLEAN FUNCTIONS

AIM:



To implement the given $oolean e>pression using logic gates

APPARATUS REQUIRED:

S.N" C""*)*6 Ra*) Qa*(/

- AN ate )C /0-- -3 OR ate )C /043 -

4 NOT ate )C /013 -

0 NAN ate )C /011 -

6 Resistor 331 -

7 &E " -

THEORY:

A binary variable can take the value of 1 or -. A $oolean function is

an e>pression formed #ith binary variables, the t#o binary operators OR

and AN, and unary operator NOT, parenthesis and an eBual sign, *or a

given value of the variables, the function can either 1 or -.

LOGICAL DIAGRAM:



PROCEDURE:

-. Connections are made as per the circuit diagram.

3. ive the input and verify as per the gates and table given.





!ilin> 8.- soft#are.

APPARATUS REQUIRED:

• (C #ith !ilin> 8.- soft#are.

SIMULATION PROCEDURE:

• Open !ilin> 8.- soft#are.

• Open a ne# proPect and give a name for the proPect.

• Open a ne# erilog hdl source and give a name for a program.

• %et the input and output variables.

•rite I& program.

• %elect synthesis5implementation option and run the check synta>..

• Open a ne# Test bench #aveform source and give a name for the

test bench.

• ive the inputs in the timing diagram #indo#.

• %elect behavioral simulation option and run the simulate

behavioral modeling option.

HDL PROGRAM FOR HALF ADDER:

// Module half adder. module half_adder (sum, carry, a, !"ou#$u# sum,carry"%&$u# a,"'or (sum,a,!"



a&d (carry,a,!"e&dmodule

HDL PROGRAM FOR FLL ADDER:// Module full adder.

module full_adder (sum, cou#, a, ,c%&!"ou#$u# sum,cou#"%&$u# a,,c%&"

)%re s*,c*,c+"'or (s*,a,!"a&d (c*,a,!"

'or (sum,s*,c%&!"a&d (c+,s*,c%&!"

or (cou#,c+,c*!"

e&dmodule

-MLA-O OP FOR HALF ADDER:



-MLA-O OP FOR FLL ADDER:

HDL PROGRAM FOR HALF 0RA1OR:



// Module half su#rac#or. module half_su#rac#or (d%ff, orro), a, !"ou#$u# d%ff,orro)"%&$u# a,"

)%re a&o#"&o# '2 (a&o#,a!"'or '* (d%ff,a,!"a&d '+ (orro),a&o#,!"e&dmodule

HDL PROGRAM FOR FLL 0RA1OR:

// Module full su#rac#or.

module full_ su#rac#or (d%ff, ou#, a, ,%&!"ou#$u# sum,cou#"%&$u# a,,c%&"

)%re a&o#,s*&o#" )%re s*,c*,c+"

&o# '2 (a&o#,a!"&o# '3 (s*&o#,s*!"

'or '* (s*,a,!"

a&d '+ (c*,a&o#,!"

'or '4 (d%ff,s*,%&!"a&d '5 (c+,s*&o#,%&!"

or '6 (ou#,c+,c*!"

E&dmodule

-M-G D-AGRAM FOR HALF 0RA1OR:





RESULT:

Thus the I& program for adders and subtractors are simulated

and the output results are verified.

EXP NO. :1=





-M-G D-AGRAM FOR DEML-PLE7ER:

HDL PROGRAM FOR 5 O * ML-PLE7ER:



// Module 58#o8* mul#%$le'er. module mu'5_#o_* (ou#, %2, %*, %+, %4, s*, s2!"ou#$u# ou#"%&$u# %2, %*, %+, %4"%&$u# s*, s2"

)%re s*&, s2&" )%re y2, y*, y+, y4"&o# (s*&, s*!"&o# (s2&, s2!"a&d (y2, %2, s*&, s2&!"a&d (y*, %*, s*&, s2!"a&d (y+, %+, s*, s2&!"a&d (y4, %4, s*, s2!"

or (ou#, y2, y*, y+, y4!"e&dmodule

HDL PROGRAM FOR * O 5 DEML-PLE7ER:

// Module *8#o85 Demul#%$le'er.

module demu'*_#o_5 ( %, s2, s*, d2,d*,d+,d4!"ou#$u# d2,d*,d+,d4"%&$u# %"%&$u# s*, s2"

)%re s*&, s2&"&o# (s*&, s*!"&o# (s2&, s2!"a&d (d2, %, s*&, s2&!"a&d (d*, %, s*, s2&!"a&d (d+, %, s*&, s2!"

a&d (d4, %, s*, s2!"e&dmodule





SIMULATION OF 8 BIT RIPPLE COUNTER AND MOD-109MOD-12

RIPPLE COUNTER USING HDL SOFT'ARE

AIM:

To simulate erilog hdl program for 0 bit ripple counter and mod"

-15mod"-3 ripple counter using !ilin> 8.- soft#are.

APPARATUS REQUIRED:







• rite I& program.



test bench.• ive the inputs in the timing diagram #indo#.



-M-G D-AGRAM FOR 580- R-PPLE 1OER:



HDL PROGRAM FOR 580- R-PPLE 1OER:



//580%# R%$$le 1ou&#er

module r%$$le_cou&#er(9, cl, rese#!"ou#$u# ;4:2< 9"%&$u# cl, rese#"_FF #ff2(9;2<,cl, rese#!"_FF #ff*(9;*<,9;2<, rese#!"_FF #ff+(9;+<,9;*<, rese#!"_FF #ff4(9;4<,9;+<, rese#!"E&dmodule

// Fl%$flo$ _FF

module _FF(9, cl, rese#!"ou#$u# 9"%&$u# cl, rese#"

)%re d"D_FF dff2(9, d, cl, rese#!"&o# &*(d, 9!"e&dmodule

// module D_FF )%#h sy&chro&ous rese#

module D_FF(9, d, cl, rese#!"ou#$u# 9"%&$u# d, cl, rese#"re= 9"al)ays >($osed=e rese# or &e=ed=e cl!%f (rese#!9 ?@ *2"else9 ?@ d"e&dmodule



-M-G D-AGRAM FOR MOD8*2 R-PPLE 1OER:



HDL PROGRAM FOR MOD8*2 R-PPLE 1OER:

//Mod8*2 R%$$le 1ou&#er

module mod8*2_r%$cou&#er(9, cl, rese#!"ou#$u# ;4:2< 9"%&$u# cl, rese#"

)%re &*"_FF #ff2(9;2<,cl, rese#!"_FF #ff*(9;*<,9;2<, rese#!"_FF #ff+(9;+<,9;*<, rese#!"_FF #ff4(9;4<,9;+<, &*!"&a&d (&*, 9;*<, 9;4<!"e&dmodule

// Fl%$flo$ _FF



// module D_FF )%#h sy&chro&ous rese#

module D_FF(9, d, cl, rese#!"ou#$u# 9"%&$u# d, cl, rese#"re= 9"al)ays >($osed=e rese# or &e=ed=e cl!%f (rese#!

9 ?@ *2"else9 ?@ d"e&dmodule



-M-G D-AGRAM FOR MOD8*+ R-PPLE 1OER:

HDL PROGRAM FOR MOD8*+ R-PPLE 1OER:



//Mod8*+ R%$$le 1ou&#er

module mod8*+_r%$cou&#er(9, cl, rese#!"ou#$u# ;4:2< 9"%&$u# cl, rese#"

)%re &*"_FF #ff2(9;2<,cl, rese#!"_FF #ff*(9;*<,9;2<, rese#!"_FF #ff+(9;+<,9;*<, rese#!"_FF #ff4(9;4<,9;+<, &*!"&a&d (&*, 9;+<, 9;4<!"e&dmodule

// Module _FF



// Module D_FF




RESULT:

Thus the I& program for 0 bit ripple counter and mod"

-15mod"-3 ripple counter are simulated and the output results are verified.

EXP NO. :1



SIMULATION OF SISO SIPO PISO AND PIPO SHIFT REGISTERS

USING HDL SOFT'ARE

AIM:

To simulate erilog hdl program for %)%O, %)(O and ()(O shift

registers using !ilin> 8.- soft#are.

APPARATUS REQUIRED:







• rite I& program.



test bench.

• ive the inputs in the timing diagram #indo#.





-M-G D-AGRAM FOR -O/-PO H-F REG-ER:



HDL PROGRAM FOR -O/-PO H-F REG-ER:

// -O sh%f# re=%s#er

module -O_sh%f#_re=%s#er (9, d, cl, rese#!"ou#$u# ;4:2< 9"%&$u# d, cl, rese#"D_FF dff2(9;2<, d, cl, rese#!"D_FF dff*(9;*<, 9;2<, cl, rese#!"D_FF dff+(9;+<, 9;*<, cl, rese#!"D_FF dff4(9;4<, 9;+<, cl, rese#!"E&dmodule

// module D_FF

module D_FF(9, d, cl, rese#!"ou#$u# 9"%&$u# d, cl, rese#"re= 9"al)ays >($osed=e rese# or &e=ed=e cl!%f (rese#!9 ?@ *2"

else9 ?@ d"e&dmodule



-M-G D-AGRAM FOR P-PO H-F REG-ER:



HDL PROGRAM FOR P-PO H-F REG-ER:

// P-PO sh%f# re=%s#er

module -O_sh%f#_re=%s#er (9, d, cl, rese#!"ou#$u# ;4:2< 9"%&$u# ;4:2< d, cl, rese#"D_FF dff2(9;2<, d;2<, cl, rese#!"D_FF dff*(9;*<, d;*<, cl, rese#!"D_FF dff+(9;+<, d;+<, cl, rese#!"D_FF dff4(9;4<, d;4<, cl, rese#!"E&dmodule

// module D_FF






BCD ADDER

AIM:

To verify the $C Adder functions using the truth table.

LOGIC DIAGRAM:BCD ADDER



K MAP

Y $ S8 S3 & S24

TRUTH TABLE:

BCD SUM CARRY

S8 S3 S2 S1 C

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 0

0 1 0 0 0

0 1 0 1 0

0 1 1 0 00 1 1 1 0

1 0 0 0 0

Documents

EC2207 Lab Manual