EC-I MICROPROCESSOR AND COMMUNICATION ELECTRONICS

Unit 1: Microprocessor Architecture and Instruction Set

8085,8086/8088 microprocessor architecture – Various registers

– central processing unit of micro computers – Timing and control unit

– Instruction and data flow – system timings - examples – instruction

set – data transfer group – logical group – branch group – stack and I/O

control instructions – addressing modes.

Unit – 2 Software programs (8085 only)

Addition – subtraction – multiplication – division – BCD arithmetic

– searching an array of a given number – Choosing the biggest and

smallest number from a list – Ascending and descending orders –

square root of a number –Time delay – square wave generator.

Unit – 3 Interfacing memory and I/O devices

Interfacing memory and devices – I/O and memory mapped I/O

Types of interfacing devices – Data transfer schemes – programmed

and DMA data transfer schemes – programmable peripheral interface –

8255 A – 8253 – Timer interface – DMA controller - Programmable

interrupt controller 8259 – Programmable communication interface

8251

Unit – 4 Digital transmission systems and modulation techniques

Point to point links – line coding – coherent optical fibre

communication - definition and classification coherent system –

Requirements on semiconductor lasers

Modulation and Demodulation principles of amplitude –

frequency and phase modulation – simple circuits for amplitude ,

frequency and phase modulation and demodulation – pulse

modulation.

Unit - 5 Satellite communications

Ground station – Antenna – angle of elevation and transmission

path – height of geo station orbits – problems – satellite works –

frequency allocation and polarization - various blocks of equipment

abroad the satellite – transmit and receive contour – Block diagram of

network control stations (NCS) – interconnecting telephone traffic

between remote stations – SS/TDMA concepts

PART- A

1. Define Microprocessor

A microprocessor is a computer processor that incorporates the

functions of a computer's central processing unit (CPU) on a

single integrated circuit (IC). It is also the brain of the system.

2. What are the components of microcomputer?

Arithmetic and Logical Unit, Timing and Control Unit, Registers

3. List the types of semiconductor memory?

Random Access Memory, Read Only Memory, Erasable

Programmable Read Only Memory , EEPROM

4. List out the general and special purpose registers in 8085

Accumulator ,B,C,D,E,H and L, Stack Pointer , Program

Counter

5. What is a bus? What are the different types of buses. Define

The group of lines used for connecting input/ output devices

and memories with the CPU is called bus. Three different

types of buses are Data Bus, Address Bus. Control bus

Data Bus: 8 bits of data are transmitted to the in parallel D0-D7

Address Bus: Transmit Address and Data at different moments

in a multiplexing technique AD0-AD15

6. Explain : INTR, IO/M’ , HLDA, ALE

INTR : Interrupt request signal . It is sampled in the last state of

the last machine cycle

IO/M’ : It is the status signal that distinguishes whether the

address is for memory or IO

HLDA: It is the signal for Hold Acknowledgement, that

indicates the HOLD request has been received

ALE : It is an Address Latch Enable that enables the lower 8

bits of the address to be latched either to IO or memory

7. What is Interrupt? Which has the highest priority?

The request signal that affects the normal sequence of

the program. TRAP has the highest priority

8. What are the different types of flags? Give its format

Carry Flag(C), Auxilliary Carry Flag(AC)

Zero Flag (Z) , Parity Flag (P), Sign Flag (S)

9. Give two examples for two byte instruction . Explain

MVI A,05 Moves the immediate data 05 to Acc

IN 08 Reads the port value 08 to Accumulator

10. Write down the five different types of instruction set.

Data Transfer group

Arithmetic group

Logical group

Branch group and

Stack , I/O and Machine Control group

10. Define Addressing mode

The instruction requires certain data on which it has to operate

have various techniques called Addressing modes .

11. Write an ALP for 8-bit simple addition(without carry)

LXI H, 8850

MOV A,M

INX H

ADD M

STA 8852

12. What is PSW?

Program Status Word . 5 status flags and three undefined bits is

called PSW.

13. What is program counter?

The PC stores the address of the next instruction that is going

to be executed.It is a 16 bit register.

14. Define Stack Pointer?

Stores the address of the Stack Top . It is a 16 bit register

15. What is PUSH and POP?

Inserting and Deleting an item to and from the stack is called

PUSH and POP

16. Define the modulation index of Amplitude modulation

The AM modulation index is a measure based on the ratio of the

modulation excursions of the RF signal to the level of the

unmodulated carrier. It is thus defined as:

where and are the modulation amplitude and carrier

amplitude, respectively; the modulation amplitude is the peak

(positive or negative) change in the RF amplitude from its

unmodulated value. Modulation index is normally expressed as a

percentage, and may be displayed on a meter connected to an AM

transmitter.

17. Explain the necessity of modulation in communication system

Modulation is an important step of communication system.

Modulation is defined as the process whereby some characteristic

(line amplitude, frequency, phase of a high frequency signal wave

(carrier wave) is varied in accordance with instantaneous value

intensity of low frequency signal wave (modulating wave.)

Need for modulaiton

To separate signal from different transmitters

Size of the antenna

18. Define Phase modulation

The phase of the AC signal wave, also called the carrier, varies

in a continuous manner. Thus, there are infinitely many possible

carrier phase states. When the instantaneous data input waveform

has positive polarity, the carrier phase shifts in one direction; when

the instantaneous data input waveform has negative polarity, the

carrier phase shifts in the opposite direction. At every instant in time,

the extent of carrier-phase shift(the phase angle) is directly

proportional to the extent to which the signal amplitude is positive or

negative.

19. What are point to point links?

A point-to-point connection refers to a communications

connection between two nodes or endpoints. An example is a

telephone call, in which one telephone is connected with one other,

and what is said by one caller can only be heard by the other. This is

contrasted with a point-to-multipoint or broadcast communication

topology, in which many nodes can receive information transmitted by

one node. Other examples of point-to-point communications links are

leased lines, microwave relay links, and two way radio. Examples of

point-to-multipoint communications systems are radio and television

broadcasting.

20. Distinguish between FM and PM

AM stands for amplitude modulation where the amplitude of the

carrier is modulated as per the message signal. The other aspects of

the carrier wave such as frequency phase etc. remain constant. On

the other hand, FM means frequency modulation and in it only

frequency of the carrier wave changes while amplitude, phase etc.

remain constant.

21. Define Coherent system.

Modulation technique like BPSK is used for long distance

communication which is equivalent to suppressed carrier orthogonal

wave modulation. At the receiver the suppressed carrier is

regenerated with identical phase and frequency to that of transmitter

carrier frequency and the process of demodulation is referred to as

coherent demodulation.

22. What is sampling theorem?

The theorem that a signal that varies continuously with time is

completely determined by its values at an infinite sequence of equally

spaced times if the frequency of these sampling times is greater than

twice the highest frequency component of the signal. Also known as

Shannon's sampling theorem.

23. Define the term elementary doublet

An elementary doublet is a small length of conductor δℓ (small

compared to the wavelength λ) carrying an alternating current:

Here ω = 2πf is the angular frequency (and f the frequency), and

i = √−1 is the imaginary unit, so that I is a phasor.

24. What are the advantages of communication satellite?

Wide Coverage

Stationary Position

Multiple Access

Suitability for transcontinental telecommunications, broadcasting, mobile and thin route communications.

Frequency reuse capability

Very low Doppler Shift

Reliability.

Cost effectiveness.

25. What is geo stationary orbits? Why it is preferred

Attitude 35,786 km.

Period 23 Hr. 56 min. 4.091 sec. (One sidereal day)

Orbit inclination. 00

Velocity 3.075 km per sec.

Coverage 42.5% of earth’s surface.

Sub satellite point On equator.

Area of no

coverage

Beyond 810 North and South latitude.

(77º if angle of elevation below 5º are eliminated )

Advantages - Simple ground station tracking.

- No hand over problem

- Nearly constant range

- Very small doppler shift

Disadvantages - Transmission delay of the order of 250 msec.

- Large free space loss

- No polar coverage

26. Define power gain of antenna

Power gain (or simply gain) is a unitless measure that combines

an antenna's efficiency Eantenna and directivity D:

When considering the power gain for a particular direction given

by an elevation (or "altitude") and azimuth , then:

is known as the directive gain. The directive gain signifies the

ratio of radiated power in a given direction relative to that of an

isotropic radiator which is radiating the same total power as the

antenna in question but uniformly in all directions. Note that a true

isotropic radiator does not exist in practice.

27. What is ground station?

A ground station, earth station, or earth terminal is a terrestrial

radio station designed for extra planetary telecommunication with

spacecraft, or reception of radio waves from an astronomical radio

source. Ground stations are located either on the surface of the Earth

or in its atmosphere.[1] Earth stations communicate with spacecraft by

transmitting and receiving radio waves in the super high frequency or

extremely high frequency bands (e.g., microwaves). When a ground

station successfully transmits radio waves to a spacecraft (or vice

versa), it establishes a telecommunications link. A principal

telecommunications device of the ground station is the parabolic

antenna.

PART - B

1. Discuss the addressing modes of 8085

There are five addressing modes in 8085.

a. Immediate Addressing Mode: An immediate is transferred directly to the register.

Eg: - MVI A, 30H (30H is copied into the register A)

MVI B,40H(40H is copied into the register B).

b. Register Addressing Mode: Data is copied from one register to another register.

Eg: - MOV B, A (the content of A is copied into the reg B)

MOV A, C (the content of C is copied into the reg A)

c. Direct Addressing Mode: Data is directly copied from the given address to the reg.

Eg: - LDA 3000H (The content at the location 3000H is copied to the register A).

d. Indirect Addressing Mode: -

The data is transferred from the address pointed by the data in a register to other register.

Eg: - MOV A, M (data is transferred from the memory location pointed by the regiser to the accumulator).

e. Implied Addressing Mode: This mode doesn't require any operand. The data is specified by opcode itself. Eg: - RAL, CMP

2. Discuss the flag registers of 8085

The flag register in 8085 is an 8-bit register which contains 5 bit

positions.

These five flags are of 1bit F/F and are known as zero, sign,

carry, parity and auxiliary carry.

For sign flag if the result of an MSB operation is 1 then it is set

else it is reset.

The zero flag is set of the result of an instruction is zero.

The auxiliary carry flag is used for BCD operations, not free to

the programmer.

The carry flag is used for carrying and borrowing in case of

addition and subtraction operations.

The parity flag is used for results containing an even number of

one's.

Other three bits are undefined.

3. Discuss the instruction format of 8085

One byte instruction: Single byte specifies the opcode

MOV A,B

ADD B

CMP

Two byte instruction: The first byte specifies the opcode

MVI A,06

SUI B,06

IN port

Three Byte instruction: The first byte specifies the opcode.

The second and the third byte specifies the address of the

memory location.

LDA 8850

LXI H,9960

JMP 5040

4. Draw the pin diagram of 8085

5. Write a note on BCD arithmetic

BCD takes advantage of the fact that any one decimal numeral

can be represented by a four bit pattern. The most obvious way of

encoding digits is "natural BCD" (NBCD), where each decimal digit is

represented by its corresponding four-bit binary value, as shown in

the following table. This is also called "8421" encoding.

Decimal

Digit

BCD

8 4 2 1

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

6. Write an Assembly language program to find the square root of a

number

LXI H,C050

MOV A,M MVI B,01 MVI C,00

L2: SUB B JC L1 INR C INR B INR B JMP L2

L1: MOV A,C STA C060 HLT

7. How time delays are given in the programs using registers

8. Explain the concept of memory mapped I/O and I/O mapped I/O

I/O mapped I/Os have separate address space than the

memory. So, total addressed capacity is no. of I/Os connected and

memory connected. Separate I/O related instructions are used to

access I/Os. A separate signal is used for addressing I/O device.

Memory mapped IOs share the memory space with external

memory. So, total addressed capacity is memory connected only.

This is underutilisation of resources if your processor supports I/O

mapped I/O. In this case instructions used to access I/Os are same

as that used for memory.

9. Write a note on asynchronous mode of data transfer

When the I/O device speed and μp speed do not match,

asynchronous mode may be used. The key feature of this mode is

that, the MPU initiates data transfer by requesting the device to

get ready and then goes on checking its status. The I/O instruction is

executed only when the I/O device is ready to accept or supply data.

So each data transfer is preceded by a ‘request ready’ signal

generated by the MPU and an acknowledgement signal issued by the

I/O device. The method is known as handshaking mode of data

transfer, as it resembles the back-and-forth movement of hands

involved in handshaking, to coordinate the data transfer. The

flowchart for this mode of data transfer. The asynchronous mode is

ideal for reconciling the timing differences between the MPU and I/O

devices. However, an important disadvantage is that a lot of precious

MPU time is wasted during the looping to check the I/O device

status. The wastage of the MPU time may be prohibitive or

impractical in many situations.

10. With neat sketch explain DMA controller

11. Draw the block diagram of 8086 architecture

The four segment registers (CS, DS, ES, and SS) are used to

"point" at location 0 (the base address) of each segment. The

segment registers are only 16 bits wide, but the memory address is

20 bits wide. The BIU takes care of this problem by appending four

0's to the low-order bits of the segment register. In effect, this

multiplies the segment register contents by 16.

The segment address is not arbitrary, it must begin at an

address divisible by 16. The four segments need not be defined

separately. It is allowable for all four segments to completely overlap

(CS = DS = ES = SS).

Memory locations not defined to be within one of the current

segments cannot be accessed by the 8086/88 without first redefining

one of the segment registers to include that location. Thus at any

given instant a maximum of 256 K (64K * 4) bytes of memory can be

utilized. The contents of the segment registers can only be specified

via S/W.

12. Explain the timing diagram of MVI B,05

13. Write an ALP to perform BCD addition

LXI H 4000H : HL points 4000H

MOV A, M : Get first operand

INX H : HL points 4001H

ADD M : Add second operand

DAA: Decimal Adjust Accumalator

INX H : HL points 4002H

MOV M, A : Store result at 4002H

HLT : Terminate program execution

14. Explain the block diagram to AM transmitter

Transmitters transmit AM signals are known as AM

transmitters. These transmitters are used in medium wave (MW) and

short wave (SW) frequency bands for AM broadcast. The MW band

has frequencies between 550 KHz and 1650 KHz, and the SW band

has frequencies ranging from 3 MHz to 30 MHz. The two types of AM

transmitters that are used based on their transmitting powers are:

High Level

Low Level

High level transmitters use high level modulation, and low level

transmitters use low level modulation. The choice between the two

modulation schemes depends on the transmitting power of the AM

transmitter. In broadcast transmitters, where the transmitting power

may be of the order of kilowatts, high level modulation is employed. In

low power transmitters, where only a few watts of transmitting power

are required , low level modulation is used.

High-Level and Low-Level Transmitters

The basic difference between the two transmitters is the power

amplification of the carrier and modulating signals.

Figure (a) shows the block diagram of high-level AM transmitter.

Figure (a) is drawn for audio transmission. In high-level

transmission, the powers of the carrier and modulating signals are

amplified before applying them to the modulator stage, as shown in

figure (a). In low-level modulation, the powers of the two input signals

of the modulator stage are not amplified. The required transmitting

power is obtained from the last stage of the transmitter, the class C

power amplifier.

The various sections of the figure (a) are:

Carrier oscillator

Buffer amplifier

Frequency multiplier

Power amplifier

Audio chain

Modulated class C power amplifier

Carrier oscillator

The carrier oscillator generates the carrier signal, which lies in

the RF range. The frequency of the carrier is always very high.

Because it is very difficult to generate high frequencies with good

frequency stability, the carrier oscillator generates a sub multiple with

the required carrier frequency. This sub multiple frequency is

multiplied by the frequency multiplier stage to get the required carrier

frequency. Further, a crystal oscillator can be used in this stage to

generate a low frequency carrier with the best frequency stability. The

frequency multiplier stage then increases the frequency of the carrier

to its required value.

Buffer Amplifier

The purpose of the buffer amplifier is two fold. It first matches

the output impedance of the carrier oscillator with the input

impedance of the frequency multiplier, the next stage of the carrier

oscillator. It then isolates the carrier oscillator and frequency

multiplier.

Frequency Multiplier

The sub-multiple frequency of the carrier signal, generated by

the carrier oscillator , is now applied to the frequency multiplier

through the buffer amplifier. This stage is also known as harmonic

generator. The frequency multiplier generates higher harmonics of

carrier oscillator frequency. The frequency multiplier is a tuned circuit

that can be tuned to the requisite carrier frequency that is to be

transmitted.

Audio Chain

The audio signal to be transmitted is obtained from the

microphone, as shown in figure (a). The audio driver amplifier

amplifies the voltage of this signal. This amplification is necessary to

drive the audio power amplifier. Next, a class A or a class B power

amplifier amplifies the power of the audio signal.

Modulated Class C Amplifier

This is the output stage of the transmitter. The modulating

audio signal and the carrier signal, after power amplification, are

applied to this modulating stage. The modulation takes place at this

stage. The class C amplifier also amplifies the power of the AM signal

to the reacquired transmitting power. This signal is finally passed to

the antenna., which radiates the signal into space of transmission.

Coupling of Output Stage and Antenna

The output stage of the modulated class C power amplifier

feeds the signal to the transmitting antenna. To transfer maximum

power from the output stage to the antenna it is necessary that the

impedance of the two sections match.

15. Describe pulse position modulation

Pulse-position modulation (PPM) is a form of signal modulation

in which M message bits are encoded by transmitting a single pulse

in one of possible time-shifts. This is repeated every T seconds,

such that the transmitted bit rate is bits per second. It is

primarily useful for optical communications systems, where there

tends to be little or no multipath interference.

16. Discuss the frequency spectrum of FM wave

In telecommunications and signal processing, frequency

modulation (FM) is the encoding of information in a carrier wave by

varying the instantaneous frequency of the wave

If the information to be transmitted (i.e., the baseband signal) is

and the sinusoidal carrier is , where fc is

the carrier's base frequency, and Ac is the carrier's amplitude, the

modulator combines the carrier with the baseband data signal to get

the transmitted signal:

In this equation, is the instantaneous frequency of the

oscillator and is the frequency deviation, which represents the

maximum shift away from fc in one direction, assuming xm(t) is limited

to the range ±1.

Most of the energy of the signal is contained within fc ± fΔ, it can

be shown by Fourier analysis that a wider range of frequencies is

required to precisely represent an FM signal. The frequency spectrum

of an actual FM signal has components extending infinitely, although

their amplitude decreases and higher-order components are often

neglected in practical design problems.

Modulation index

As in other modulation systems, the value of the modulation

index indicates by how much the modulated variable varies around its

un modulated level. It relates to variations in the carrier frequency:

Bessel functions

For the case of a carrier modulated by a single sine wave, the

resulting frequency spectrum can be calculated using Bessel

functions of the first kind, as a function of the sideband number and

the modulation index. The carrier and sideband amplitudes are

illustrated for different modulation indices of FM signals. For particular

values of the modulation index, the carrier amplitude becomes zero

and all the signal power is in the sidebands.

17. Define AM. Discuss briefly about frequency spectra of AM wave

Amplitude modulation (AM) is a modulation technique used in

electronic communication, most commonly for transmitting

information via a radio carrier wave. AM works by varying the

strength (amplitude) of the carrier in proportion to the waveform being

sent. The waveform corresponds to the sounds to be reproduced by a

loudspeaker, or the light intensity of television pixels. This contrasts

with frequency modulation, in which the frequency of the carrier

signal is varied, and phase modulation, in which its phase is varied,

by the modulating signal. AM was the earliest modulation method

used to transmit voice by radio.

Consider a carrier wave (sine wave) of frequency fc and

amplitude A given by:

.

Let m(t) represent the modulation waveform. For this example

we shall take the modulation to be simply a sine wave of a frequency

fm, a much lower frequency (such as an audio frequency) than fc:

,

where M is the amplitude of the modulation. We shall insist that

M<1 so that (1+m(t)) is always positive. Amplitude modulation results

when the carrier c(t) is multiplied by the positive quantity (1+m(t)):

Using prosthaphaeresis identities, y(t) can be shown to be the

sum of three sine waves:

Therefore, the modulated signal has three components: the

carrier wave c(t) which is unchanged, and two pure sine waves

(known as sidebands) with frequencies slightly above and below the

carrier frequency fc.

18. Explain the generation and demodulation of PWM

Pulse-width modulation (PWM), or pulse-duration modulation

(PDM), is a technique used to encode a message into a pulsing

signal. It is a type of modulation.

The term duty cycle describes the proportion of 'on' time to the

regular interval or 'period' of time; a low duty cycle corresponds to low

power, because the power is off for most of the time. Duty cycle is

expressed in percent, 100% being fully on.

The main advantage of PWM is that power loss in the switching

devices is very low. When a switch is off there is practically no

current, and when it is on and power is being transferred to the load,

there is almost no voltage drop across the switch. Power loss, being

the product of voltage and current, is thus in both cases close to zero.

19. Discuss about satellite orbits and satellite positions

Satellite orbits are classified in terms of the orbital height. These are:

Low Earth Orbit (LEO)

Medium Earth Orbit (MEO) / Intermediate Circular Orbit (ICO)

Highly Elliptical Orbit (HEO)

Geosynchronous Earth Orbit (GEO)

Satellite orbits with orbital height of approximately 1000 km or less

are known as Low Earth Orbit (LEO). LEOs tend to be in general circular in

shape. Satellite orbits with orbital heights of typically in the range of 5000

km to about 25,000 km are known as Medium Earth Orbit (MEO) /

Intermediate Circular orbit (ICO). MEO and ICO are often used

synonymously, but MEO classification is not restricted to circular orbits.

Satellites in Highly Elliptical Orbit (HEO) are suitable for communications in

the higher latitudes.

In Geosynchronous Earth Orbit (GEO) the satellite is in equatorial

circular orbit with an altitude of 35,786 km and orbital period of 24 hours.

Three satellites in GEO placed 1200 apart over equator cover most of the

world for communications purposes.

20. Discuss about antenna look angles

The look angles for the ground station antenna are the azimuth

and elevation angles required at the antenna so that it points directly

at the satellite.

The three pieces of information to determine the look angles for

the geostationary orbit are

* The earth station latitude, denoted here by PE

* The earth station longitude, denoted here by JE

* The longitude of the subsatellite point, denoted here by JSS

(often referred to as the satellite longitude)

Polar Mount Antenna

Polar mount is a piece of equipment installed into geostationary

satellites to be accessed by swinging the satellite dish around one

axis. This allows one positioned only to be used to remotely point the

antenna at any satellite.

21. Discuss in detail TDMA

Time division multiple access (TDMA) is a channel access

method for shared medium networks. It allows several users to share

the same frequency channel by dividing the signal into different time

slots. The users transmit in rapid succession, one after the other,

each using its own time slot. This allows multiple stations to share the

same transmission medium (e.g. radio frequency channel) while

using only a part of its channel capacity. TDMA is used in the digital

2G cellular systems such as Global System for Mobile

Communications (GSM), IS-136, Personal Digital Cellular (PDC) and

iDEN, and in the Digital Enhanced Cordless Telecommunications

(DECT) standard for portable phones. It is also used extensively in

satellite systems, combat-net radio systems, and PON networks for

upstream traffic from premises to the operator. For usage of Dynamic

TDMA packet mode communication, see below.

TDMA frame structure showing a data stream divided into

frames and those frames divided into time slots.

TDMA is a type of Time-division multiplexing, with the special

point that instead of having one transmitter connected to one

receiver, there are multiple transmitters. In the case of the uplink from

a mobile phone to a base station this becomes particularly difficult

because the mobile phone can move around and vary the timing

advance required to make its transmission match the gap in

transmission from its peers.

PART - C

1. Explain the architecture of Intel 8085 with neat sketch

Explanation of Registers, ALU, Timing and control unit, Flags

2. Discuss the Instruction set of 8085

Instruction is a command given to the computer to perform a

specified operation on given data. The instruction set of a

microprocessor is the collection of the instructions that the

microprocessor is designed to execute. The instructions described

here are of Intel 8085. These instructions are of Intel Corporation.

They cannot be used by other microprocessor manufactures. The

programmer can write a program in assembly language using these

instructions. These instructions have been classified into the following

groups:

1. Data Transfer Group

2. Arithmetic Group

3. Logical Group

4. Branch Control Group

5. I/O and Machine Control Group

Data Transfer Group

Instructions, which are used to transfer data from one register

to another register, from memory to register or register to memory,

come under this group. Examples are: MOV, MVI, LXI, LDA, STA etc.

When an instruction of data transfer group is executed, data is

transferred from the source to the destination without altering the

contents of the source. For example, when MOV A, B is executed the

content of the register B is copied into the register A, and the content

of register B remains unaltered. Similarly, when LDA 2500 is

executed the content of the memory location 2500 is loaded into the

accumulator. But the content of the memory location 2500 remains

unaltered.

Arithmetic Group

The instructions of this group perform arithmetic operations

such as addition, subtraction; increment or decrement of the content

of a register or memory. Examples are: ADD, SUB, INR, DAD etc.

Logical Group

The Instructions under this group perform logical operation

such as AND, OR, compare, rotate etc. Examples are: ANA, XRA,

ORA, CMP, and RAL etc.

Branch Control Group

This group includes the instructions for conditional and

unconditional jump, subroutine call and return, and restart. Examples

are: JMP, JC, JZ, CALL, CZ, RST etc.

I/O and Machine Control Group

This group includes the instructions for input/output ports, stack

and machine control. Eg are: IN, OUT, PUSH, POP, and HLT etc.

Data Transfer Group

1. MOV r1, r2 (Move Data; Move the content of the one register to another). [r1] <-- [r2]

2. MOV r, m (Move the content of memory register). r <-- [M]

3. MOV M, r. (Move the content of register to memory). M <-- [r]

4. MVI r, data. (Move immediate data to register). [r] <-- data.

5. MVI M, data. (Move immediate data to memory). M <-- data.

6. LXI rp, data 16. (Load register pair immediate). [rp] <-- data 16 bits, [rh] <-- 8 LSBs of

data.

7. LDA addr. (Load Accumulator direct). [A] <-- [addr].

8. STA addr. (Store accumulator direct). [addr] <-- [A].

9. LHLD addr. (Load H-L pair direct). [L] <-- [addr], [H] <-- [addr+1].

10. SHLD addr. (Store H-L pair direct) [addr] <-- [L], [addr+1] <-- [H].

11. LDAX rp. (LOAD accumulator indirect) [A] <-- [[rp]]

12. STAX rp. (Store accumulator indirect) [[rp]] <-- [A].

13. XCHG. (Exchange the contents of H-L with D-E pair) [H-L] <--> [D-E].

Arithmetic Group

1. ADD r. (Add register to accumulator) [A] <-- [A] + [r].

2. ADD M. (Add memory to accumulator) [A] <-- [A] + [[H-L]].

3. ADC r. (Add register with carry to accumulator). [A] <-- [A] + [r] + [CS].

4. ADC M. (Add memory with carry to accumulator) [A] <-- [A] + [[H-L]] [CS].

5. ADI data (Add immediate data to accumulator) [A] <-- [A] + data.

6. ACI data (Add with carry immediate data to accumulator). [A] <-- [A] + data + [CS].

7. DAD rp. (Add register paid to H-L pair). [H-L] <-- [H-L] + [rp].

8. SUB r. (Subtract register from accumulator). [A] <-- [A] – [r].

9. SUB M. (Subtract memory from accumulator). [A] <-- [A] – [[H-L]].

10. SBB r. (Subtract register from accumulator with borrow). [A] <-- [A] – [r] – [CS].

11. SBB M. (Subtract memory from accumulator with borrow). [A] <-- [A] – [[H-L]] – [CS].

12. SUI data. (Subtract immediate data from accumulator) [A] <-- [A] – data.

13. SBI data. (Subtract immediate data from accumulator with borrow). [A] <-- [A] – data –

[CS].

14. INR r (Increment register content) [r] <-- [r] +1.

15. INR M. (Increment memory content) [[H-L]] <-- [[H-L]] + 1.

16. DCR r. (Decrement register content). [r] <-- [r] – 1.

17. DCR M. (Decrement memory content) [[H-L]] <-- [[H-L]] – 1.

18. INX rp. (Increment register pair) [rp] <-- [rp] – 1.

19. DCX rp (Decrement register pair) [rp] <-- [rp] -1.

20. DAA (Decimal adjust accumulator) .

Logical Group

1. ANA r. (AND register with accumulator) [A] <-- [A] ^ [r].

2. ANA M. (AND memory with accumulator). [A] <-- [A] ^ [[H-L]].

3. ANI data. (AND immediate data with accumulator) [A] <-- [A] ^ data.

4. ORA r. (OR register with accumulator) [A] <-- [A] v [r].

5. ORA M. (OR memory with accumulator) [A] <-- [A] v [[H-L]]

6. ORI data. (OR immediate data with accumulator) [A] <-- [A] v data.

7. XRA r. (EXCLUSIVE – OR register with accumulator) [A] <-- [A] v [r]

8. XRA M. (EXCLUSIVE-OR memory with accumulator) [A] <-- [A] v [[H-L]]

9. XRI data. (EXCLUSIVE-OR immediate data with accumulator) [A] <-- [A]

10. CMA. (Complement the accumulator) [A] <-- [A]

11. CMC. (Complement the carry status) [CS] <-- [CS]

12. STC. (Set carry status) [CS] <-- 1.

13. CMP r. (Compare register with accumulator) [A] – [r]

14. CMP M. (Compare memory with accumulator) [A] – [[H-L]]

15. CPI data. (Compare immediate data with accumulator) [A] – data.

The 2nd byte of the instruction is data, and it is subtracted from the content of the

accumulator. The status flags are set according to the result of subtraction. But the result

is discarded. The content of the accumulator remains unchanged.

16. RLC (Rotate accumulator left) [An+1] <-- [An], [A0] <-- [A7],[CS] <-- [A7].

The content of the accumulator is rotated left by one bit. The seventh bit of the

accumulator is moved to carry bit as well as to the zero bit of the accumulator. Only CS

flag is affected.

17. RRC. (Rotate accumulator right) [A7] <-- [A0], [CS] <-- [A0], [An] <-- [An+1].

The content of the accumulator is rotated right by one bit. The zero bit of the accumulator

is moved to the seventh bit as well as to carry bit. Only CS flag is affected.

18. RAL. (Rotate accumulator left through carry)

[An+1] <-- [An], [CS] <-- [A7], [A0] <-- [CS].

19. RAR. (Rotate accumulator right through carry)

[An] <-- [An+1], [CS] <-- [A0], [A7] <-- [CS]

Branch Group

1. JMP addr (label). (Unconditional jump: jump to the instruction specified by the address).

[PC] <-- Label.

2. Conditional Jump addr (label): After the execution of the conditional jump instruction the

program jumps to the instruction specified by the address (label) if the specified

condition is fulfilled. The program proceeds further in the normal sequence if the

specified condition is not fulfilled. If the condition is true and program jumps to the

specified label, the execution of a conditional jump takes 3 machine cycles: 10 states. If

condition is not true, only 2 machine cycles; 7 states are required for the execution of the

instruction.

1. JZ addr (label). (Jump if the result is zero)

2. JNZ addr (label) (Jump if the result is not zero)

3. JC addr (label). (Jump if there is a carry)

4. JNC addr (label). (Jump if there is no carry)

5. JP addr (label). (Jump if the result is plus)

6. JM addr (label). (Jump if the result is minus)

7. JPE addr (label) (Jump if even parity)

8. JPO addr (label) (Jump if odd parity)

Stack, I/O and Machine Control Group

1. IN port-address. (Input to accumulator from I/O port) [A] <-- [Port]

2. OUT port-address (Output from accumulator to I/O port) [Port] <-- [A]

3. PUSH rp (Push the content of register pair to stack)

4. PUSH PSW (PUSH Processor Status Word)

5. POP rp (Pop the content of register pair, which was saved, from the stack)

6. POP PSW (Pop Processor Status Word)

7. HLT (Halt)

8. XTHL (Exchange stack-top with H-L)

9. SPHL (Move the contents of H-L pair to stack pointer)

10. EI (Enable Interrupts)

11. DI (Disable Interrupts)

12. SIM (Set Interrupt Masks)

13. RIM (Read Interrupt Masks)

14. NOP (No Operation)

3. Write an ALP for performing addition and subtraction of 8 bit numbers

Addition Program:

LXI H 4000H : HL points 4000H

MOV A, M : Get first operand

INX H : HL points 4001H

ADD M : Add second operand

INX H : HL points 4002H

MOV M, A : Store result at 4002H

HLT : Terminate program execution

Subtraction Program

LXI H, 4000H : HL points 4000H

MOV A, M : Get first operand

INX H : HL points 4001H

SUB M : Subtract second operand

INX H : HL points 4002H

MOV M, A : Store result at 4002H.

HLT : Terminate program execution

4. Write an ALP for performing multiplication of 8-bit numbers

LDA 2200H

MOV E, A

MVI D, 00 : Get the first number in DE register pair

LDA 2201H

MOV C, A : Initialize counter

LX I H, 0000 H : Result = 0

BACK: DAD D : Result = result + first number

DCR C : Decrement count

JNZ BACK : If count 0 repeat

SHLD 2300H : Store result

HLT : Terminate program execution

5. Write an ALP to find the largest of a given number

LDA 2200H

MOV C, A : Initialize counter

XRA A : Maximum = Minimum possible value = 0

LXI H, 2201H : Initialize pointer

BACK: CMP M : Is number> maximum

JNC SKIP : Yes, replace maximum

MOV A, M

SKIP: INX H

DCR C

JNZ BACK

STA 2300H : Store maximum number

HLT : Terminate program execution

6. Write an ALP to sort the numbers in descending order

START:MVI B, 00 ; Flag = 0

LXI H, 4150 ; Count = length of array

MOV C, M

DCR C ; No. of pair = count -1

INX H ; Point to start of array

LOOP:MOV A, M ; Get kth element

INX H

CMP M ; Compare to (K+1) th element

JNC LOOP 1 ; No interchange if kth >= (k+1) th

MOV D, M ; Interchange if out of order

MOV M, A ;

DCR H

MOV M, D

INX H

MVI B, 01H ; Flag=1

LOOP 1:DCR C ; count down

JNZ LOOP ;

DCR B ; is flag = 1?

JZ START ; do another sort, if yes

HLT ; If flag = 0, step execution

7. Illustrate 8255 Programmable Peripheral Interface . Discuss the

command modes

The 8255 has 24 input/output pins in all. These are divided into

three 8-bit ports. Port A and port B can be used as 8-bit input/output

ports. Port C can be used as an 8-bit input/output port or as two 4-bit

input/output ports or to produce handshake signals for ports A and B.

The three ports are further grouped as follows:

1. Group A consisting of port A and upper part of port C.

2. Group B consisting of port B and lower part of port C.

Eight data lines (D0 - D7) are available (with an 8-bit data

buffer) to read/write data into the ports or control register under the

status of the RD (pin 5) and WR (pin 36), which are active low

signals for read and write operations respectively. The address lines

A1 and A0 allow to successively access any one of the ports or the

control register as listed below:

A1 A0 Port selected

0 0 port A

0 1 port B

1 0 port C

1 1 control register

The control signal CS (pin 6) is used to enable the 8255 chip.

It is an active low signal, i.e., when CS = '0', the 8255 is enabled.

The RESET input (pin 35) is connected to the RESET line of system

like 8085, 8086, etc., so that when the system is reset, all the ports

are initialized as input lines. This is done to prevent 8255 and/or any

peripheral connected to it, from being destroyed due to mismatch of

ports. As an example, consider an input device connected to 8255 at

port A. If from the previous operation, port A is initialized as an output

port and if 8255 is not reset before using the current configuration,

then there is a possibility of damage of either the input device

connected or 8255 or both since both 8255 and the device connected

will be sending out data.

Mode 0 - simple I/O

In this mode, the ports can be used for simple I/O operations

without handshaking signals. Port A, port B provide simple I/O

operation. The two halves of port C can be either used together as an

additional 8-bit port, or they can be used as individual 4-bit ports.

Since the two halves of port C are independent, they may be used

such that one-half is initialized as an input port while the other half is

initialized as an output port.

The input/output features in mode 0 are as follows:

1. Output ports are latched.

2. Input ports are buffered, not latched.

3. Ports do not have handshake or interrupt capability.

4. With 4 ports, 16 different combinations of I/O are

possible.

Mode 1 - Handshaking

To use port A or port B for handshake (strobe) input or output

operation, initialize that port in mode 1 (port A and port B can be

initialized to operate in different modes, i.e., for e.g., port A can

operate in mode 0 and port B in mode 1). Some of the pins of port C

function as handshake lines.

For port B in this mode (irrespective of whether is acting as an

input port or output port), PC0, PC1 and PC2 pins function as

handshake lines.

If port A is initialized as mode 1 input port, then, PC3, PC4 and

PC5 function as handshake signals. Pins PC6 and PC7 are available

for use as input/output lines.

The mode 1 which supports handshaking has following

features:

1. Two ports i.e. port A and B can be used as 8-bit i/o ports.

2. Each port uses three lines of port c as handshake signal

and remaining two signals can be used as i/o ports.

3. Interrupt logic is supported.

4. Input and Output data are latched.

Mode 2- Bidirectional

Only group A can be initialized in this mode. Port A can be used

for bidirectional handshake data transfer. This means that data can

be input or output on the same eight lines (PA0 - PA7). Pins PC4 -

PC7 are used as handshake lines for port A. The remaining pins of

port C (PC0 - PC3) can be used as input/output lines if group B is

initialized in mode 0 or as handshaking for port B if group B is

initialized in mode 1.

8. Illustrate 8253 Programmer Timer Interface with its operating modes

and

D0...D7: 8 bit data lines. This is connected to the data bus so we can read and send commands.

CLK 0, CLK 1, CLK 2: Clock input pins. There are 3 pins for 3 separate counters OUT 0, OUT 1, OUT 2: Output data line. There are 3 pins for 3 separate counters GATE 0, GATE 1, GATE 2:Gate data line. There are 3 pins for 3 separate counters GND: Ground Vcc: Input voltage WR: Write enable. When this line is active, lets the 8253 that we are writing data RD: Read enable. When this line is active, lets the 8253 that we are reading data CS: Chip select signal A0, A1: Address lines. Used to determin what register we are accessing.

.

Mode 0: Interrupt on Terminal Count

In this mode, the counter will be programmed to an initial

COUNT value and after words counts down at a rate to the input

clock frequency (The CLK signal).

Mode 1: Hardware Triggered One-Shot

In this mode, the counter is programmed to give an output

pulse every certain number of clock pulses. The OUT line is set to

high as soon as a Control Word is written. After COUNT is written,

the counter waits until the rising edge of the GATE input. If the trigger

occurs during the pulse output, the 8253 will be retriggered again.

Mode 2: Rate Generator

The counter is programmed to an initial COUNT value.

Counting starts at the next clock cycle. OUT remains high until

COUNT reaches 1. After words, OUT will be set low for one clock

pulse. OUT is then set back high, and COUNT is reset back to its

initial value. This process repeats until a new control word is sent to

the controller.

Mode 3: Square Wave Generator

OUT will be high for half of the period, and low for the other

half. If COUNT is odd, OUT will be high for (n+1)/2 counts. If COUNT

is even, OUT will be low for (n-1)/2 counts.

Mode 4: Software Triggered Strobe

The counter is programmed to an initial COUNT value.

Counting starts at the next clock cycle. OUT remains high until

COUNT reaches 0. The counter will then set OUT low for one clock

cycle. After words, it resets OUT to high again.

Mode 5: Hardware Triggered Strobe

The counter is programmed to an initial COUNT value. OUT

remains high until the controller detects the rising edge of the GATE

input. When this happens, the counting starts. When COUNT reaches

0, OUT goes low for one clock cycle.

8253 Registers

8253 PIT Internal Registers

Register

Name

Port

Address

RD

line

WR

line

A0

line

A1

line Function

Counter 0 0x40 1 0 0 0 Load Counter 0

0 1 0 0 Reads Counter 0

Counter 1 0x41 1 0 0 1 Load Counter 1

0 1 0 1 Reads Counter 1

Counter 2 0x42 1 0 1 0 Load Counter 2

0 1 1 0 Reads Counter 2

Control Word 0x43 1 0 1 1 Write Control

Word

NA

0 1 1 1 No Operation

9. Illustrate 8259 Programmable interrupt controller with its different

modes

ICW1 (Initialisation Command Word One)

A0

0

D7 D6 D5 D4 D3 D2 D1 D0

A7 A6 A5 1 LTIM ADI SNGL IC4

D0: IC4: 0=no ICW4, 1=ICW4 required

D1: SNGL: 1=Single PIC, 0=Cascaded PIC

D2: ADI: Address interval. Used only in 8085, not 8086. 1=ISR's are 4 bytes apart (0200, 0204,

etc) 0=ISR's are 8 byte apart (0200, 0208, etc)

D3: LTIM: level triggered interrupt mode: 1=All IR lines level triggered. 0=edge triggered

D4-D7: A5-A7: 8085 only. ISR address lower byte segment. The lower byte is

ICW2 (Initialisation Command Word Two)

Higher byte of ISR address (8085), or 8 bit vector address (8086).

A0

1

D7 D6 D5 D4 D3 D2 D1 D0

A15 A14 A13 A12 A11 A10 A9 A8

ICW2 (Initialisation Command Word Two)

Higher byte of ISR address (8085), or 8 bit vector address (8086).

A0

1

D7 D6 D5 D4 D3 D2 D1 D0

A15 A14 A13 A12 A11 A10 A9 A8

ICW3 (Initialisation Command Word Three)

A0

1

D7 D6 D5 D4 D3 D2 D1 D0

Master S7 S6 S5 S4 S3 S2 S1 S0

Slave 0 0 0 0 0 ID3 ID2 ID1

Master mode: 1 indicates slave is present on that interrupt, 0 indicates direct interrupt Slave mode: ID3-ID2-ID1 is the slave ID number. Slave 4 on IR4 has ICW3=04h (0000 0100)

10. Illustrate 8251 Programmable communication interface

The 8251A is a programmable serial communication interface chip designed for synchronous and asynchronous serial data communication.

It supports the serial transmission of data.

It is packed in a 28 pin DIP.

Read/Write control logic:

The Read/Write Control logic interfaces the 8251A with CPU, determines the functions of the 8251A according to the control word written into its control register.

It monitors the data flow.

This section has three registers and they are control register, status register and data buffer.

The active low signals RD, WR, CS and C/D(Low) are used for read/write operations with these three registers.

When C/D(low) is high, the control register is selected for writing control word or reading status word.

When C/D(low) is low, the data buffer is selected for read/write operation.

When the reset is high, it forces 8251A into the idle mode.

The clock input is necessary for 8251A for communication with CPU and this clock does not control either the serial transmission or the reception rate.

Transmitter section:

The transmitter section accepts parallel data from CPU and converts them into serial data.

The transmitter section is double buffered, i.e., it has a buffer register to hold an 8-bit parallel data and another register called output register to convert the parallel data into serial bits.

When output register is empty, the data is transferred from buffer to output register. Now the processor can again load another data in buffer register.

If buffer register is empty, then TxRDY is goes to high.

If output register is empty then TxEMPTY goes to high.

The clock signal, TxC (low) controls the rate at which the bits are transmitted by the USART.

The clock frequency can be 1,16 or 64 times the baud rate.

Receiver Section:

The receiver section accepts serial data and convert them into parallel data

The receiver section is double buffered, i.e., it has an input register to receive serial data and convert to parallel, and a buffer register to hold the parallel data.

When the RxD line goes low, the control logic assumes it as a START bit, waits for half a bit time and samples the line again.

If the line is still low, then the input register accepts the following bits, forms a character and loads it into the buffer register.

The CPU reads the parallel data from the buffer register.

When the input register loads a parallel data to buffer register, the RxRDY line goes high.

The clock signal RxC (low) controls the rate at which bits are received by the USART.

During asynchronous mode, the signal SYNDET/BRKDET will indicate the break in the data transmission.

During synchronous mode, the signal SYNDET/BRKDET will indicate the reception of synchronous character.

MODEM Control:

The MODEM control unit allows to interface a MODEM to 8251A and to establish data communication through MODEM over telephone lines.

This unit takes care of handshake signals for MODEM interface.

11. Explain the principle of PCM . Also discuss the generation and demodulation of PCM

Pulse-code modulation (PCM) is a method used to digitally

represent sampled analog signals. It is the standard form of digital

audio in computers, Compact Discs, digital telephony and other

digital audio applications. In a PCM stream, the amplitude of the

analog signal is sampled regularly at uniform intervals, and each

sample is quantized to the nearest value within a range of digital

steps.

In the diagram, a sine wave (red curve) is sampled and

quantized for PCM. The sine wave is sampled at regular intervals,

shown as vertical lines. For each sample, one of the available values

(on the y-axis) is chosen by some algorithm. This produces a fully

discrete representation of the input signal (blue points) that can be

easily encoded as digital data for storage or manipulation. For the

sine wave example at right, we can verify that the quantized values at

the sampling moments are 8, 9, 11, 13, 14, 15, 15, 15, 14, etc.

Encoding these values as binary numbers would result in the

following set of nibbles: 1000 (23×1+22×0+21×0+20×0=8+0+0+0=8),

1001, 1011, 1101, 1110, 1111, 1111, 1111, 1110, etc. These digital

values could then be further processed or analyzed by a digital signal

processor. Several PCM streams could also be multiplexed into a

larger aggregate data stream, generally for transmission of multiple

streams over a single physical link. One technique is called time-

division multiplexing (TDM) and is widely used, notably in the modern

public telephone system.

The PCM process is commonly implemented on a single

integrated circuit generally referred to as an analog-to-digital

converter (ADC).

To recover the original signal from the sampled data, a

"demodulator" can apply the procedure of modulation in reverse.

After each sampling period, the demodulator reads the next value

and shifts the output signal to the new value. As a result of these

transitions, the signal has a significant amount of high-frequency

energy caused by aliasing. To remove these undesirable frequencies

and leave the original signal, the demodulator passes the signal

through analog filters that suppress energy outside the expected

frequency range (greater than the Nyquist frequency ).[note 1] The

sampling theorem shows PCM devices can operate without

introducing distortions within their designed frequency bands if they

provide a sampling frequency twice that of the input signal. For

example, in telephony, the usable voice frequency band ranges from

approximately 300 Hz to 3400 Hz. Therefore, per the Nyquist–

Shannon sampling theorem, the sampling frequency (8 kHz) must be

at least twice the voice frequency (4 kHz) for effective reconstruction

of the voice signal.

The electronics involved in producing an accurate analog signal

from the discrete data are similar to those used for generating the

digital signal. These devices are Digital-to-analog converters (DACs).

They produce a voltage or current (depending on type) that

represents the value presented on their digital inputs. This output

would then generally be filtered and amplified for use.

12. Discuss the PAM with circuit diagram , also explain TDM

Pulse-amplitude modulation (PAM), is a form of signal

modulation where the message information is encoded in the

amplitude of a series of signal pulses. It is an analog pulse

modulation scheme in which the amplitudes of a train of carrier

pulses are varied according to the sample value of the message

signal. Demodulation is performed by detecting the amplitude level of

the carrier at every symbol period.

Time-division multiplexing (TDM) is a method of transmitting

and receiving independent signals over a common signal path by

means of synchronized switches at each end of the transmission line

so that each signal appears on the line only a fraction of time in an

alternating pattern. This form of signal multiplexing was developed in

telecommunications for telegraphy systems

13. Explain the block diagram of Network Control Stations

The INMARSAT satellite system comprises of the following

essential components.

a. Space segment operating and standby satellites

with repeaters

b. Network of land earth stations which are owned by

some signatories to the INMARSAT organization

c. Subscriber mobile earth stations or terminals which

are either leased or individual owner / operators

d. System control facility which comprises of network

operation centre and satellite control centre (SCC)

which are owned by INMARSAT organization

14. Describe the circuit layout of a satellite

Two major elements of Satellite Communications Systems are

Space Segment

Ground Segment

The Space Segment includes

Satellite

Means for launching satellite

Satellite control centre for station keeping of the satellite

The functions of the ground segment are to transmit the signal

to the satellite and receive the signal from the satellite. The

ground segment consists of

Earth Stations

Rear Ward Communication links

User terminals and interfaces

Network control centre