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INSTRUCTION MANUAL

-- FOR

DATA BUS ADAPTER

DBA-488-SR400

--

-

ILC DATA DEVICE CORPORATION

105 Wilbur Place Bohemia New York 11716 - 516-567-5600 TWX 510-228-7324 leader In S~nchro Conwerslon bull High-Speed Hlgh-Accuracy D A amp AD Conwenlon bull Mllllary Data Conv8nlon Systems

--- Rev B Effective 15 December 1981 with DBA-488 SN 061

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TABLE OF CONTENTS

SECTION 1 GENERAL DESCRIPTION

Scope of Manual

Purpose of the DBA-488 Bus Adapter

Physical Description

The IEEE GPill

Basic Structure and Constraints

Basic Bus Terminology

Interface Bus Signals

Remote Message Coding

3-Wire Handshake Procedure

SECTION 2 FUNCTIONAL DESCRIPTION OF DBA-488

Introduction

Block Diagram Description

Functional Description

Equipment Complement

Transceivers U1 and U2

Interface Controller U5

Microprocessor U6

ROMU9

PIAIS U10 and Ull

Power Up and Device Address

Data Transfer

SECTION 3 DATA BUS ADAPTER DBA-488-SR400

Equipment Supplied

DBA-488 Ordered with SR-400

DBA-488 Ordered Separately

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TABLE OF CONTENTS (CONTD)

SECTION 3 DATA BUS ADAPTER DBA-488-SR400 (Contd)

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Table

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Unpacking

Interconnections

Setting the Primary Device Address

Operating Procedure

Command Codes

ControI Word or Data Command Sequence (Listen)

Maintenance

DBA-488 Parts List

LIST OF ILLUSTRATIONS

DBA-488 Data Bus Adapter

Interface Connections and Bus Structure

Handshake Timing Sequence

DBA-488 Block Diagram

DBA-488 Data Bus Adapter Schematic Diagram

DBA-488-SR400 Connection Diagram bullbullbull

Listen Command Sequence Flow Chart

DBA-488 Location of Parts bull bull bull bull

LJST OF TABLES

Message Coding

DBA-488 to SR-400 Connections

Command Code Functions

DBA-488 Parts List

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SECTION 1

GENERAL DESCRIPTION

SCOPE OF MANUAL11

Sections 1 and 2 of this instruction manual describe the DBA-488 Data Bus Adapter (figure 1-1) manufactured by ILC Data Device Corporation Bohemia N Y Section 3 covers the DBA-488- ( ) the combination of the DBA-488 with one of DDCs synchro instruments (eg the DBA-488-SR103 DBA-488shySR400 DBA-488-SR202)

12 PURPOSE OF THE DBA-488 DATA BUS ADAPTER -The DBA-488 links DDCs synchro instruments to any programmable measurement instrument system such as computer controlled automatic test eqtlipment (ATE) or process controi system that operates from the IEEE-488-1975 General Purpose Interface Bus Operation of the DBA-488 is also fully compatible with the HewlettshyPackard HP-IB bus without programming changes Highlights of the IEEE-488shy1975 bus are included for reference in later paragraphs

-

Figure 1-1 DBA-488 Data Bus Adapter -1-1

13 PHYSICAL DESCRIPTION

The DBA-488 is eonfigured as a fully enclosed flat rectaIoular( assembly

81 X 61 X 17 (206 X 156 X 43 cm) that weighs less than 2-1 2 lbs (11 kg) Four holes in the lips of the eover facilitate mounting Two intershyface conneetors one for the IEEE-488 General Purpose Intcrfaee Bus (GPIB) and the other for the assoeiated instrument are mou nted on onc side of the unit Eight cA-ternally aeeessible miniature address seleet roeker switehcs are l-ocated between the two conncctors

14 THE IEEE-488 GPIB

The following abbreviated deseription of the IEEE-488 GPIB is ineluded for reference For eomplete bus details eonsult IEEE Standard 488-1975 Digital Interfaee for Programmable Instrumentation Copies of IEEE 488-1975 may be purchased from IEEE (Institute of Electrieal and Eleetronies Engineers) or from the American National Standards Institute both of whieh are loeated in New York N Y

141 BASIC STRUCTURE AND CONSTRAINTS

The IEEE bus is a byte-serial bit-parallel interfaee system It is structured with 16 lines consisting of the following

a Eight data bus lines for transmission of ASCII characters Data is asynchronous and gcncrally bidirectional

b Five bus management (control) signal lines

c Threc data byte transfer control lines (handshake)

The system includes constraints on the number of devices data rate total transmission length and is confincd to exchange of digital data

142 BASIC BUS TERlVllNOLOGY

aController - A devicc that can address other devices to listen or to talk

b Listener - A device that can be addressed through the bus to receive messhysages from another dcvice or the controller via the bus

c Talker - A device that can bc addressed through the bus to transmit messhysages to another device or the controller via the bus

NOTE

Controller listener and talker capabilitics may occur individually and collcetively in devices interconnected by the IEEE bus (See fig 1-2)

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1-2

DATA OIOI- DI08

II I

DEVICE A

(TIUlt DAILY ) I ~ I ~ i- shy

II I

DEVCE B f----

(liSTEN ONLY) I

l II ~

I

DEICE C ( TALK liND r

LI5TEAI) I t-- shy

I II

DElleE D (TAL Ilt L5TEAJ I lAVD COIVTROL HIAlDSHAKE L-shy LINE S

III 1 NDACL~ N~FD

DAV-I

C EOI 5RGl 1lUJ- rnbull lfT1JJ

MA AJA6 EMENT (COAJTIiOL) L INeuro S

Figure 1-2 Interface Connections and Bus Structure

1-3

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143 INTERFACE BUS SIGNAIB

NOTE

The IEEE Standard 488-1975 is defined for a negative logic format

Logic O Logic l

= =

False True

= =

High Low

(~2 OV) eO 8V)

a EOI (End or Identify) True levelon this bus management (control) line indicates end of multiple byte transfer When used with ATN performs parallel polling sequence

b SRQ (Service Request) Device sets this control line true when it requires service from the interface controller

c REN (Remote Enable) This controller driven line is used with other messhysages to select source of device programrning data (e g front panel or interface control)

d IFC (lnterface Clear) This controller driven Une is set true to place all ws-connected devices in their idle states

e ATN (Attentian) This control line specifies how data on the data lines are to be interpreted and which devices must respond to the data When ATN is true the DIOl-DI08 lines carry addresses or commands When ATN is set false the data lines carry data

f NDAC (Not Data Accepted) When set false by a device indicates that data has been accepted

this handshake line

g NRFD (Not Ready for Data) When set false by a device this handshake line indicates that the device is ready to accept data

h DAV (Data Valid) When set true this handshake line indicates that informashytion on the data lines is available and valid

i DIOl-m08 (Data Input-Output) These lines carry data in bit-parallel byteshyserial form Information on the lines represents either addresscommands or data depending on the logic state of the ATN line

j Unlisten Command This command is transrnitted on the data lines in conjunction with ATN true to terrninate the device listen function

k Untalk Command This command is transrnitted on the data lines in conjunction with ATN true to terrninate the device talk function

144 REMOTE MESSAGE CODING

Table l-l shows the coding of same of the control messages transmitted on the IEEE bus The l and O designatians refer to the logic states (negative logic convention) X = dont care Al-A5 specify the five address bits set within the device by the address select switches

1-4

) ] ] )) ) ] ] J J l J ) J J J J

~ I

CJ1

TABLE 1-1 MESSAGE CODING

IO Data Handshake Controi Message DI08 DI07 DI06 DI05 DI04 DI03 m02 mOl DAV NRFD NDAC ATN EOI SRQ IFC REN

ATN (Attention) x X X X X X X X X X X 1 X X X X

Data Byte D8 D7 D6 D5 D4 D3 D2 Dl X X X X X X X X

DAV (Data Available) X X X X X X X X 1 X X X X X X X

NRFD (Not Ready for Data) X X X X X X X X X 1 X X X X X X

NDAC (Not Data Accepted) X X X X X X X X X X 1 X X X X X

DCL (Device Clear) X ~ ~ 1 ~ 1 ~ ~ X X X X X X X X

End X X X X X X X X X X X X 1 X X X

Go to Local X O O O O O O 1 X X X X X X X X

Identify X X X X X X X X X X X X 1 X X X

IFC (Interface Clear) X X X X X X X X X X X X X X 1 X

MLA (My Listen Address) X ~ 1 A5 A4 A3 A2 Al X X X X X X X X

MTA (My Talk Address) X 1 ~ A5 A4 A3 A2 Al X X X X X X X X

REN (Remote Enable) X X X X X X X X X X X X X X X 1

SRQ (Service Required) X X X X X X X X X X X X X 1 X X

Unlisten X ~ 1 1 1 1 1 1 X X X X X X X X

Untalk X 1 ~ 1 1 1 1 1 X X X X X X X X

145 3-WIRE HANDSHAKE PROCEDURE

The 3-wire handshake procedure repeated for each byte transferred from a source to ot1e or more acceptors ensures that each listener is ready to accept data that the information on the data lines is valid and that the data has been accepted by all listeners The DAV line is controlled by the source (talker) the NDAC and NRFD lines are controlled by the acceptors (listeners)

FiglLre 1-3 illustrates the handshake cyc le for a source and several acceptors

a Both source and acceptors start in a known state The source initializes DA V to high (false data not valid) and the acceptors initialize NRFD to low (true none are ready for data) and NDAC to low (true none have accepted the data)

b The source checks that both NRFD and NDAC are not high then places the first data byte on the DIO lines (If both lines are sensed high the error condition ends the procedure)

c When all acceptors are ready to accept the first data byte NRFD goes high -d After data is settled and valid and the source has sensed NRFD high it sets DAV low (data is valid)

e The first acceptor sets NRFD low then accepts the f~rst byte receptors follow suit at their own rates

The other

f Each acceptor sets NDAC high to indicate that it has accepted

g When NDAC is sensed high by the source (after all acceptors have accepted the data byte) it sets DA V high (data on DIO lines no longer valid) At this point one data byte transfer has been completed

h Upon sensing DAV high the acceptors set NDAC low

i Source and acceptor initial conditions are now reestablished and the next handshake cycle may be initiated

1-6

ACCEPTOR OPERATiONSOURCE OPERATiON

READYNO TO ACCEPT DA TA

NO NRFD

DATA iS VALiD AND MAY NOW BE ACCEPTED

NO

YES --

Figure 1-3 Handshake Timing Sequence

1-7

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SECTION 2

FUNCTIONAL DESCRIPTION OF DBA-488

INTRODUCTION21

This section provides a general functional description of the DBA-488 identifying the major input-output signals and covering basic signal flow Detailed step-byshystep operations within the DBA-488 are a function of the particular instrument and the stored program

22 BLOCK DIAGRAM DESCRIPTION (See figure 2-1)

Operation of the DBA-488 is supervised by a self-contained microprocessor in accordance with a program stored in an erasable programmable ROM Data transshyfer to and from the 16-line IEEE bus is mediated by the controller The 32 inputshyoutput lines at the instrument interface are independently programmed under microprocessor control for input or output data transfer according to the requireshyments of the particular instrument connected to the DBA-488 The device address preset manually by the user via the address select switches is transferred to the controller memory at power turn-on

23 FUNCTIONAL DESCRIPTION (See figure 2-2)

231 EQUIPMENT COMPLEMENT

The DBA-488 consists of four bus transceivers U1-U4 interface controller U5 microprocessor U6 tri-state buffers U7 and U8 ROM U9 and peripheral intershyface adapters (PIAs) U10 and Ull In addition a low voltage power supply consisting of power transformer T1 bridge rectifier CRA1 and voltage regulator VR1 provides 5 volts DC for operating the unit

232 TRANSCEIVERS U1 AND U2

Transceivers U1-U4 serve as the interface between the IEEE bus and the DBA-488 internal logic Transceivers U1 and U2 are used for bus management and handshake signals U3 and U4 accommodate the eight data lines Logic levels applied to the four transmit-receive inputs of each quad transceiver from controller U5 determine which section behaves as a bus driver or receiver for the associated bus line The T fR control for SRQ is always ired high (transmit) while those for REN 1FC and ATN are wired low (receive) The remaining signals are controlled by U5 The bus transceiver outputs meet all requirements of IEEE Std 488-1975

2-1

881T5512 Byr~ IO

ROM NTERshyB BITSFACE

tJ I BBIT

tJ ( DATA

INSTRUMENT IEEE INTERFACE488 32 10 UNS

BUS 8DITA LlNES 8 BIT5 PLUS

l DATA L JE S 8 CONT~

LINES 8 B I T 8 BITSL-----

mAlTROL IlDDRESStlleRO shySELECTPROCESSOR

SLJITCHES

Figure 2-1 DBA-488 Block Diagram bull

1 l ] ] I l J _J l l

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233 INTERFACE CONTROLLER U5

Under the direction of microprocessor U6 interface controller U5 mediates the transfer of data between the DBA-488 and the IEEE bus Controller U5 decodes messages from the IEEE bus processes those directed to the DBA-488 and transshyfers messages to the internai data bus It should be noted that although the IEEE bus signals follow negative logic convention positive logic is used within the DBAshy488 (Thus the signal NRFD from the IEEE bus is designated RFD at the input of U5) The controller is equipped with internai registers that are selected by register select lines RSO RS1 and RS2 and chip select CS (via microprocessor address bits AO Al and A2 and Al4) in conjunction with the readwrite (RW) signals and ~2 clock from the microprocessor The registers accornmodate functions such as aringddress data in data out interrupt status etc Data transfer between U5 and U3 U4 is effected through the m - IB7 lines the DB~ - DB7 lines carry data between U5 and the internai data bus CS enables U5 and ~2 is a timing signal provided by U6

234 lVIICROPROCESSOR U6

The 8-bit microprocessor contains registers accumulators a 128 X 8 bit RAM and an internai clock The 16-line address bus (A~-A15) supervises the DBA-488 operations The 8-line bidirectional data bus (D~-D7) transfers data to and from memory and the peripheral devices Clock pulses at pin E (~2) are used for timing Upon receipt of an interrupt request (IRQ) from controller U5 (upon U5s receipt of DC L on the data lines) U6 completes its current instruction then cycles through an interrupt sequence that resets the microprocessor The read write (RW) output of U6 controls the read write status of controller U5 and PIAs U10 and Ull

235 ROM U9

Erasable prograrnmable ROM U9 stores the DBA-488 program in its 512 X 8 bit memory When enabled (CS input low) and strobed by a clock pulse from U6 (STR input) address bits A~-A8 are decoded and data transfer is effected on the DO~ - D07 lines

236 PIAS U10 AND Ull

PIAs U10 and Ull interface the DBA-488 with the DDC instrument Four 8-bit bidirectional data buses (PA~ - PA7 and PB~ - PB7) cornmunicate with the instrushyment an 8-bit bidirectional bus (D~ - D7) links the selected PIAs with the internai data bus Each chip is selected by ~ low via a U6 address routed through tri shystate buffer U8 Register select inputs (RS~ RS1) controlled by microprocessor U6 accress registers within each PIA which provide functions such as data direction control peripheral interface etc PIA readwrite operation is conshytrolled by the RIW input from U6

2-3

-------------------------------- I ISTR Ul-AENT 11rr E R r CE

P(gtG PM PAZ PA4 P80 PB+ PBz PB-p PAG PM PAz PAq PBlt PE ~-~PAl PA-5 PA~ PAI RESET PB7 PR - PS3 P81 PA PAS PA3 PAI PB Res PB Ps1

Po J I ~4+- ~a -0+ JJf- 1lt-+-14 ~1ls~ IIL 7 __ Z0 T2i l gt l ll ~J 2i1 ~ll~3 - - - ST l (T 3 T -41_3l-z let It f012Jtz2tz~t~d Z5

i2-1 I i I I (1 4 si 1111(1151 I~I iii lo

Po PO P O il 81 11 I si 4131 2 Ii I 11 151 141 b L) 8 1 1 2 141 121

Po UIO Ull Ull-j Ula

p AZ-BPIAI- 8 p IA2-APIAI-A $5i3ltgt(fJ $IB~~$ Coigt~~$6()CP

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3101 SSI 13III Il5l~ 2iI25~i13313lI3113121 251~712(13+1 J 3~ 135 r~ II SV ~~131 bl 281271211 3 +1 l u-fl 1 1elI

122 ~ -- t5V

~ t5V t5V bull Icamp tgtV I I bull 1 -O+shybull II 1 -- -----------+ ---- -------11--11-1---+------~c~ ~~ Al ~ ~IZ~~R3 AiIi

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IlP e De1 30 D~ fp2 Eo I 2) DB2 ~ 2) 111-1----=--+-lt7 -~

(p SRQ 23 Jo [)8 3lt1 ~ Tl~ II i

Al

D-t~OSRQ lel ~1 -e DSIl REN 4 U I ID REN l2 ii DB4

bull 1 Ie Q __-=-2i--1 Dlt 1-i-1----+-lt7 -~ J IFC 1 ~J~ 14 IFe 21 11 DBS

bull I e-- l) us 1o-__2--i D7 13 D8ltu

I I I t~ ~~---t-ltJ -~ r-~======~~-~~~ ~_1 1= ~I L-_-4~--+------~4~O ReSI I I IN 1 8 3 -z AringT N = 2(P 6PI~bull I ( 37 E6 INDfgtC I l ( DAC Il 37 iCSO Al) I=-~---t-u -~ bull 1 bull ( lt136rp4J --____ 3=-4-1 RwiNRFOIO UL 0 RFD IS 3e iC51 Al I _ bull 1 (

--_--=30=-1 EXIll 14(1~lq _ i4- D- 1i1 3~ ilt 2- M 1 1 D7 1 0-- o-H bull I ( ~ M5B I - shy

I 3 c~ 1 I I-_---=3-11 XTALtO rPZGPIB I I III +gt

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----J rGJll II 3~

1 D101 I~4 s

- D1o21 7 ---t-----~~t=t=~----~-~SV RE L I I 2 -HA-L-T3IDlogt 110 I U3 ASE

bull I I( )_ e 34 iP2 t5V --- 5 HR

4D1 04-I 15 1133 -- C4 1i111LI 4 IRQ I I I 1 +5 lgt 22 D() Vec ~ UlUe

Ibl C5 Pllltllto SoV

j3 1[)OW 2 IB4- -=- 32 Ph e I I I U~

L- el -- -NO

IB~ 3i U12shyIJ4 DlOl ~l 1ltgt T1gt I ~ F cp rP cp -=- (8V S~_ PIN 14- +sv~5D1071~2 U4 ) ID 1Bamp 3D DtvAGIA1oI1 --L ADAI Aringl A3 A~ Ar AIoA~ As 20 I - 35 ~NDPIN

~ D106 1 ~i iS 14- 1 B Z l eC i V C)C4 C3C2C Je ~3 AI5 t51

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W I 11 e

1 2 I

zil u= 140 IRQ R- zo 1=-------- - ~TV

~ pto J 1 TI

4 tS~~

4 2

~gnlf[3EFI 13 c shy

121 Figure 2-2 1)BA-488 Data Bus (1] Ll- )4 Plt6 4 3 ~ 11-(NV Adapter ScWelnatic Diagram

2-4 1

237 POWER UP AND DEVICE ADDRESS

When power is applied to the DBA-488 the logic low level at test point TP2 (resulting from the uncharged state of C2) initializes U5 U10 UH and U6 The ASE (address select) output of U5 drops enabling the outputs of address switch S1 The five preset LSBs of Sl representing the primary device address are then transferred into a register in controller U5 for subsequent use

238 DATA TRANSFER

Controller U5 responds to the device address (applied via the data line inputs on the lE lines) when the IEEE bus sets ATN true Notified by U5 via the DB data lines U6 addresses ROM U9 which determines if talk or listen operation is reshyquired If the talk mode is selected U6 enables PIAs U10 and Ull and causes data from the instrument to be transferred through the PIAs to controller U5 which transfers the data through the IB lines to U3 and U4 These buffers enabled by a TR2 level from U5 transfer the required data to the IEEE bus Transmisshysion of the individual data bytes is accomplished in proper sequence as a function of the handshake procedure The bus management lines (ATN IFC SRQ EOI and REN) insure that information flows through the interface lines in orderly fashion When the last data bytes (ASCII carriage returnline feed) are transmitted the DBA-488 sets EOI true to signal the end of the data transfer This feature permits compatible operation of the DBA-488 with the HPIB system The entire sequence is terminated by an Untalk command from the controller

When the DBA-488 listen address is received data applied to U3 and U4 is transshyferred to controller U5 The microprocessor then transfers the data from U5 to the PIA s which pass the information to the instrument An EOI or carriage return line feed is received to indicate the end of the data transfer and the listen sequence is terminated by an Unlisten command

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2-5

SECTION 3

DATA BUS ADAPTER DBA-488-SR400

31 EQUIPMENT SUPPLlED

311 DBA-488 ORDERED WITH SR-400

When the DBA-488 is ordered together with an SR-400 SynchroResolver Simulator the DBA-488 is bracket mounted at the rear of the SR-400 and both units are elecshytrically intercOIlllected through a cable (See figure 3-1) AC power is applied to the DBA-488 when the SR-400 is turned on The only component not supplied is the standard mating connector to the IEEE bus

31 2 DBA-488 ORDERED SEPARATE LY

When a DBA-488 is ordered separately (for retrofit to an SR-400) a mating conshynector for the instrument interface is supplied but is not wired The standard mating connector for the IEEE bus is not supplied Mounting hardware is included as required

The DBA-488 is not equipped with a power switch Line voltage (115 volts at 60 Hz) is applied via the instrument interface connector If the SR-400 front panel POWER switch is to controi the DBA-488 this switch must be wired to pins on the instrument This requires a modification to the SR-400 as shown in table 3-1

NOTE

The DBA-488 may be ordered for operation from 220 volts 5060 Hz

32 UNPACKING

Carefully remove the equipment from the packaging material and inspect for possible damage Should any unit show signs of damage notify the nearest ILC Data Device Corporation field representative immediately

33 INTERCONNECTIONS

Table 3-1 shows the interconnections between the DBA-488 and SR-400 and indicates the function of each lead For SR-400 units being retrofitted switched AC line voltage (115 volts) may be wired to pins 39 and 40 of instrument connector J2 Conshynect pin 39 of J2 to the switched terminal of POWER switch S8 and pin 40 to pin L of instrument connector J1 The interconnecting cable must be wired as shown in table 3-1

3-1

-

JS )foOHZ

J(

SR - 400

cJl pz

INSTRUt1EAJT ~I---------JYMCHRO OR REllI~ roNAlECro~ RESOLVER OUTPUT

I---------REF INPUT INTeuroRCONAlECTlN(J CA13LE ___

DBA-488 NS TRUI-feNT INrEliRIICE CONNECTOR

PI

DJ3A- 4BB

STANOARD HATNy COAlNeCTOR IEEEshyBUS

Figure 3-1_ DBA-488-SR400 Connection Diagram

3-2

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31 2

TABLE OF CONTENTS

SECTION 1 GENERAL DESCRIPTION

Scope of Manual

Purpose of the DBA-488 Bus Adapter

Physical Description

The IEEE GPill

Basic Structure and Constraints

Basic Bus Terminology

Interface Bus Signals

Remote Message Coding

3-Wire Handshake Procedure

SECTION 2 FUNCTIONAL DESCRIPTION OF DBA-488

Introduction

Block Diagram Description

Functional Description

Equipment Complement

Transceivers U1 and U2

Interface Controller U5

Microprocessor U6

ROMU9

PIAIS U10 and Ull

Power Up and Device Address

Data Transfer

SECTION 3 DATA BUS ADAPTER DBA-488-SR400

Equipment Supplied

DBA-488 Ordered with SR-400

DBA-488 Ordered Separately

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TABLE OF CONTENTS (CONTD)

SECTION 3 DATA BUS ADAPTER DBA-488-SR400 (Contd)

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Figure

1-1

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Table

1-1

3-1

3-2

3-3

Unpacking

Interconnections

Setting the Primary Device Address

Operating Procedure

Command Codes

ControI Word or Data Command Sequence (Listen)

Maintenance

DBA-488 Parts List

LIST OF ILLUSTRATIONS

DBA-488 Data Bus Adapter

Interface Connections and Bus Structure

Handshake Timing Sequence

DBA-488 Block Diagram

DBA-488 Data Bus Adapter Schematic Diagram

DBA-488-SR400 Connection Diagram bullbullbull

Listen Command Sequence Flow Chart

DBA-488 Location of Parts bull bull bull bull

LJST OF TABLES

Message Coding

DBA-488 to SR-400 Connections

Command Code Functions

DBA-488 Parts List

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3-8

SECTION 1

GENERAL DESCRIPTION

SCOPE OF MANUAL11

Sections 1 and 2 of this instruction manual describe the DBA-488 Data Bus Adapter (figure 1-1) manufactured by ILC Data Device Corporation Bohemia N Y Section 3 covers the DBA-488- ( ) the combination of the DBA-488 with one of DDCs synchro instruments (eg the DBA-488-SR103 DBA-488shySR400 DBA-488-SR202)

12 PURPOSE OF THE DBA-488 DATA BUS ADAPTER -The DBA-488 links DDCs synchro instruments to any programmable measurement instrument system such as computer controlled automatic test eqtlipment (ATE) or process controi system that operates from the IEEE-488-1975 General Purpose Interface Bus Operation of the DBA-488 is also fully compatible with the HewlettshyPackard HP-IB bus without programming changes Highlights of the IEEE-488shy1975 bus are included for reference in later paragraphs

-

Figure 1-1 DBA-488 Data Bus Adapter -1-1

13 PHYSICAL DESCRIPTION

The DBA-488 is eonfigured as a fully enclosed flat rectaIoular( assembly

81 X 61 X 17 (206 X 156 X 43 cm) that weighs less than 2-1 2 lbs (11 kg) Four holes in the lips of the eover facilitate mounting Two intershyface conneetors one for the IEEE-488 General Purpose Intcrfaee Bus (GPIB) and the other for the assoeiated instrument are mou nted on onc side of the unit Eight cA-ternally aeeessible miniature address seleet roeker switehcs are l-ocated between the two conncctors

14 THE IEEE-488 GPIB

The following abbreviated deseription of the IEEE-488 GPIB is ineluded for reference For eomplete bus details eonsult IEEE Standard 488-1975 Digital Interfaee for Programmable Instrumentation Copies of IEEE 488-1975 may be purchased from IEEE (Institute of Electrieal and Eleetronies Engineers) or from the American National Standards Institute both of whieh are loeated in New York N Y

141 BASIC STRUCTURE AND CONSTRAINTS

The IEEE bus is a byte-serial bit-parallel interfaee system It is structured with 16 lines consisting of the following

a Eight data bus lines for transmission of ASCII characters Data is asynchronous and gcncrally bidirectional

b Five bus management (control) signal lines

c Threc data byte transfer control lines (handshake)

The system includes constraints on the number of devices data rate total transmission length and is confincd to exchange of digital data

142 BASIC BUS TERlVllNOLOGY

aController - A devicc that can address other devices to listen or to talk

b Listener - A device that can be addressed through the bus to receive messhysages from another dcvice or the controller via the bus

c Talker - A device that can bc addressed through the bus to transmit messhysages to another device or the controller via the bus

NOTE

Controller listener and talker capabilitics may occur individually and collcetively in devices interconnected by the IEEE bus (See fig 1-2)

-

1-2

DATA OIOI- DI08

II I

DEVICE A

(TIUlt DAILY ) I ~ I ~ i- shy

II I

DEVCE B f----

(liSTEN ONLY) I

l II ~

I

DEICE C ( TALK liND r

LI5TEAI) I t-- shy

I II

DElleE D (TAL Ilt L5TEAJ I lAVD COIVTROL HIAlDSHAKE L-shy LINE S

III 1 NDACL~ N~FD

DAV-I

C EOI 5RGl 1lUJ- rnbull lfT1JJ

MA AJA6 EMENT (COAJTIiOL) L INeuro S

Figure 1-2 Interface Connections and Bus Structure

1-3

-

143 INTERFACE BUS SIGNAIB

NOTE

The IEEE Standard 488-1975 is defined for a negative logic format

Logic O Logic l

= =

False True

= =

High Low

(~2 OV) eO 8V)

a EOI (End or Identify) True levelon this bus management (control) line indicates end of multiple byte transfer When used with ATN performs parallel polling sequence

b SRQ (Service Request) Device sets this control line true when it requires service from the interface controller

c REN (Remote Enable) This controller driven line is used with other messhysages to select source of device programrning data (e g front panel or interface control)

d IFC (lnterface Clear) This controller driven Une is set true to place all ws-connected devices in their idle states

e ATN (Attentian) This control line specifies how data on the data lines are to be interpreted and which devices must respond to the data When ATN is true the DIOl-DI08 lines carry addresses or commands When ATN is set false the data lines carry data

f NDAC (Not Data Accepted) When set false by a device indicates that data has been accepted

this handshake line

g NRFD (Not Ready for Data) When set false by a device this handshake line indicates that the device is ready to accept data

h DAV (Data Valid) When set true this handshake line indicates that informashytion on the data lines is available and valid

i DIOl-m08 (Data Input-Output) These lines carry data in bit-parallel byteshyserial form Information on the lines represents either addresscommands or data depending on the logic state of the ATN line

j Unlisten Command This command is transrnitted on the data lines in conjunction with ATN true to terrninate the device listen function

k Untalk Command This command is transrnitted on the data lines in conjunction with ATN true to terrninate the device talk function

144 REMOTE MESSAGE CODING

Table l-l shows the coding of same of the control messages transmitted on the IEEE bus The l and O designatians refer to the logic states (negative logic convention) X = dont care Al-A5 specify the five address bits set within the device by the address select switches

1-4

) ] ] )) ) ] ] J J l J ) J J J J

~ I

CJ1

TABLE 1-1 MESSAGE CODING

IO Data Handshake Controi Message DI08 DI07 DI06 DI05 DI04 DI03 m02 mOl DAV NRFD NDAC ATN EOI SRQ IFC REN

ATN (Attention) x X X X X X X X X X X 1 X X X X

Data Byte D8 D7 D6 D5 D4 D3 D2 Dl X X X X X X X X

DAV (Data Available) X X X X X X X X 1 X X X X X X X

NRFD (Not Ready for Data) X X X X X X X X X 1 X X X X X X

NDAC (Not Data Accepted) X X X X X X X X X X 1 X X X X X

DCL (Device Clear) X ~ ~ 1 ~ 1 ~ ~ X X X X X X X X

End X X X X X X X X X X X X 1 X X X

Go to Local X O O O O O O 1 X X X X X X X X

Identify X X X X X X X X X X X X 1 X X X

IFC (Interface Clear) X X X X X X X X X X X X X X 1 X

MLA (My Listen Address) X ~ 1 A5 A4 A3 A2 Al X X X X X X X X

MTA (My Talk Address) X 1 ~ A5 A4 A3 A2 Al X X X X X X X X

REN (Remote Enable) X X X X X X X X X X X X X X X 1

SRQ (Service Required) X X X X X X X X X X X X X 1 X X

Unlisten X ~ 1 1 1 1 1 1 X X X X X X X X

Untalk X 1 ~ 1 1 1 1 1 X X X X X X X X

145 3-WIRE HANDSHAKE PROCEDURE

The 3-wire handshake procedure repeated for each byte transferred from a source to ot1e or more acceptors ensures that each listener is ready to accept data that the information on the data lines is valid and that the data has been accepted by all listeners The DAV line is controlled by the source (talker) the NDAC and NRFD lines are controlled by the acceptors (listeners)

FiglLre 1-3 illustrates the handshake cyc le for a source and several acceptors

a Both source and acceptors start in a known state The source initializes DA V to high (false data not valid) and the acceptors initialize NRFD to low (true none are ready for data) and NDAC to low (true none have accepted the data)

b The source checks that both NRFD and NDAC are not high then places the first data byte on the DIO lines (If both lines are sensed high the error condition ends the procedure)

c When all acceptors are ready to accept the first data byte NRFD goes high -d After data is settled and valid and the source has sensed NRFD high it sets DAV low (data is valid)

e The first acceptor sets NRFD low then accepts the f~rst byte receptors follow suit at their own rates

The other

f Each acceptor sets NDAC high to indicate that it has accepted

g When NDAC is sensed high by the source (after all acceptors have accepted the data byte) it sets DA V high (data on DIO lines no longer valid) At this point one data byte transfer has been completed

h Upon sensing DAV high the acceptors set NDAC low

i Source and acceptor initial conditions are now reestablished and the next handshake cycle may be initiated

1-6

ACCEPTOR OPERATiONSOURCE OPERATiON

READYNO TO ACCEPT DA TA

NO NRFD

DATA iS VALiD AND MAY NOW BE ACCEPTED

NO

YES --

Figure 1-3 Handshake Timing Sequence

1-7

-

-

-

SECTION 2

FUNCTIONAL DESCRIPTION OF DBA-488

INTRODUCTION21

This section provides a general functional description of the DBA-488 identifying the major input-output signals and covering basic signal flow Detailed step-byshystep operations within the DBA-488 are a function of the particular instrument and the stored program

22 BLOCK DIAGRAM DESCRIPTION (See figure 2-1)

Operation of the DBA-488 is supervised by a self-contained microprocessor in accordance with a program stored in an erasable programmable ROM Data transshyfer to and from the 16-line IEEE bus is mediated by the controller The 32 inputshyoutput lines at the instrument interface are independently programmed under microprocessor control for input or output data transfer according to the requireshyments of the particular instrument connected to the DBA-488 The device address preset manually by the user via the address select switches is transferred to the controller memory at power turn-on

23 FUNCTIONAL DESCRIPTION (See figure 2-2)

231 EQUIPMENT COMPLEMENT

The DBA-488 consists of four bus transceivers U1-U4 interface controller U5 microprocessor U6 tri-state buffers U7 and U8 ROM U9 and peripheral intershyface adapters (PIAs) U10 and Ull In addition a low voltage power supply consisting of power transformer T1 bridge rectifier CRA1 and voltage regulator VR1 provides 5 volts DC for operating the unit

232 TRANSCEIVERS U1 AND U2

Transceivers U1-U4 serve as the interface between the IEEE bus and the DBA-488 internal logic Transceivers U1 and U2 are used for bus management and handshake signals U3 and U4 accommodate the eight data lines Logic levels applied to the four transmit-receive inputs of each quad transceiver from controller U5 determine which section behaves as a bus driver or receiver for the associated bus line The T fR control for SRQ is always ired high (transmit) while those for REN 1FC and ATN are wired low (receive) The remaining signals are controlled by U5 The bus transceiver outputs meet all requirements of IEEE Std 488-1975

2-1

881T5512 Byr~ IO

ROM NTERshyB BITSFACE

tJ I BBIT

tJ ( DATA

INSTRUMENT IEEE INTERFACE488 32 10 UNS

BUS 8DITA LlNES 8 BIT5 PLUS

l DATA L JE S 8 CONT~

LINES 8 B I T 8 BITSL-----

mAlTROL IlDDRESStlleRO shySELECTPROCESSOR

SLJITCHES

Figure 2-1 DBA-488 Block Diagram bull

1 l ] ] I l J _J l l

-

-

-

233 INTERFACE CONTROLLER U5

Under the direction of microprocessor U6 interface controller U5 mediates the transfer of data between the DBA-488 and the IEEE bus Controller U5 decodes messages from the IEEE bus processes those directed to the DBA-488 and transshyfers messages to the internai data bus It should be noted that although the IEEE bus signals follow negative logic convention positive logic is used within the DBAshy488 (Thus the signal NRFD from the IEEE bus is designated RFD at the input of U5) The controller is equipped with internai registers that are selected by register select lines RSO RS1 and RS2 and chip select CS (via microprocessor address bits AO Al and A2 and Al4) in conjunction with the readwrite (RW) signals and ~2 clock from the microprocessor The registers accornmodate functions such as aringddress data in data out interrupt status etc Data transfer between U5 and U3 U4 is effected through the m - IB7 lines the DB~ - DB7 lines carry data between U5 and the internai data bus CS enables U5 and ~2 is a timing signal provided by U6

234 lVIICROPROCESSOR U6

The 8-bit microprocessor contains registers accumulators a 128 X 8 bit RAM and an internai clock The 16-line address bus (A~-A15) supervises the DBA-488 operations The 8-line bidirectional data bus (D~-D7) transfers data to and from memory and the peripheral devices Clock pulses at pin E (~2) are used for timing Upon receipt of an interrupt request (IRQ) from controller U5 (upon U5s receipt of DC L on the data lines) U6 completes its current instruction then cycles through an interrupt sequence that resets the microprocessor The read write (RW) output of U6 controls the read write status of controller U5 and PIAs U10 and Ull

235 ROM U9

Erasable prograrnmable ROM U9 stores the DBA-488 program in its 512 X 8 bit memory When enabled (CS input low) and strobed by a clock pulse from U6 (STR input) address bits A~-A8 are decoded and data transfer is effected on the DO~ - D07 lines

236 PIAS U10 AND Ull

PIAs U10 and Ull interface the DBA-488 with the DDC instrument Four 8-bit bidirectional data buses (PA~ - PA7 and PB~ - PB7) cornmunicate with the instrushyment an 8-bit bidirectional bus (D~ - D7) links the selected PIAs with the internai data bus Each chip is selected by ~ low via a U6 address routed through tri shystate buffer U8 Register select inputs (RS~ RS1) controlled by microprocessor U6 accress registers within each PIA which provide functions such as data direction control peripheral interface etc PIA readwrite operation is conshytrolled by the RIW input from U6

2-3

-------------------------------- I ISTR Ul-AENT 11rr E R r CE

P(gtG PM PAZ PA4 P80 PB+ PBz PB-p PAG PM PAz PAq PBlt PE ~-~PAl PA-5 PA~ PAI RESET PB7 PR - PS3 P81 PA PAS PA3 PAI PB Res PB Ps1

Po J I ~4+- ~a -0+ JJf- 1lt-+-14 ~1ls~ IIL 7 __ Z0 T2i l gt l ll ~J 2i1 ~ll~3 - - - ST l (T 3 T -41_3l-z let It f012Jtz2tz~t~d Z5

i2-1 I i I I (1 4 si 1111(1151 I~I iii lo

Po PO P O il 81 11 I si 4131 2 Ii I 11 151 141 b L) 8 1 1 2 141 121

Po UIO Ull Ull-j Ula

p AZ-BPIAI- 8 p IA2-APIAI-A $5i3ltgt(fJ $IB~~$ Coigt~~$6()CP

tgtrp D1 D21gt3 1gtlt 1gt5 D Di RfS RS0 RSI Cel R-w E c-S4gt cs 1 1gt1l1gt 1 DZ lgt3 D4- D5 [)( D7 RES es412S1C-SZ RW E CS(J CSI

3101 SSI 13III Il5l~ 2iI25~i13313lI3113121 251~712(13+1 J 3~ 135 r~ II SV ~~131 bl 281271211 3 +1 l u-fl 1 1elI

122 ~ -- t5V

~ t5V t5V bull Icamp tgtV I I bull 1 -O+shybull II 1 -- -----------+ ---- -------11--11-1---+------~c~ ~~ Al ~ ~IZ~~R3 AiIi

11 b14 aJ------t-U-~3DltPlO AfJ 32 DITIRI ze - cgtsltP ~~--t-- -~ J2 v 31 D2 U0

IlP e De1 30 D~ fp2 Eo I 2) DB2 ~ 2) 111-1----=--+-lt7 -~

(p SRQ 23 Jo [)8 3lt1 ~ Tl~ II i

Al

D-t~OSRQ lel ~1 -e DSIl REN 4 U I ID REN l2 ii DB4

bull 1 Ie Q __-=-2i--1 Dlt 1-i-1----+-lt7 -~ J IFC 1 ~J~ 14 IFe 21 11 DBS

bull I e-- l) us 1o-__2--i D7 13 D8ltu

I I I t~ ~~---t-ltJ -~ r-~======~~-~~~ ~_1 1= ~I L-_-4~--+------~4~O ReSI I I IN 1 8 3 -z AringT N = 2(P 6PI~bull I ( 37 E6 INDfgtC I l ( DAC Il 37 iCSO Al) I=-~---t-u -~ bull 1 bull ( lt136rp4J --____ 3=-4-1 RwiNRFOIO UL 0 RFD IS 3e iC51 Al I _ bull 1 (

--_--=30=-1 EXIll 14(1~lq _ i4- D- 1i1 3~ ilt 2- M 1 1 D7 1 0-- o-H bull I ( ~ M5B I - shy

I 3 c~ 1 I I-_---=3-11 XTALtO rPZGPIB I I III +gt

10

Rw

----J rGJll II 3~

1 D101 I~4 s

- D1o21 7 ---t-----~~t=t=~----~-~SV RE L I I 2 -HA-L-T3IDlogt 110 I U3 ASE

bull I I( )_ e 34 iP2 t5V --- 5 HR

4D1 04-I 15 1133 -- C4 1i111LI 4 IRQ I I I 1 +5 lgt 22 D() Vec ~ UlUe

Ibl C5 Pllltllto SoV

j3 1[)OW 2 IB4- -=- 32 Ph e I I I U~

L- el -- -NO

IB~ 3i U12shyIJ4 DlOl ~l 1ltgt T1gt I ~ F cp rP cp -=- (8V S~_ PIN 14- +sv~5D1071~2 U4 ) ID 1Bamp 3D DtvAGIA1oI1 --L ADAI Aringl A3 A~ Ar AIoA~ As 20 I - 35 ~NDPIN

~ D106 1 ~i iS 14- 1 B Z l eC i V C)C4 C3C2C Je ~3 AI5 t51

~ 2~

W I 11 e

1 2 I

zil u= 140 IRQ R- zo 1=-------- - ~TV

~ pto J 1 TI

4 tS~~

4 2

~gnlf[3EFI 13 c shy

121 Figure 2-2 1)BA-488 Data Bus (1] Ll- )4 Plt6 4 3 ~ 11-(NV Adapter ScWelnatic Diagram

2-4 1

237 POWER UP AND DEVICE ADDRESS

When power is applied to the DBA-488 the logic low level at test point TP2 (resulting from the uncharged state of C2) initializes U5 U10 UH and U6 The ASE (address select) output of U5 drops enabling the outputs of address switch S1 The five preset LSBs of Sl representing the primary device address are then transferred into a register in controller U5 for subsequent use

238 DATA TRANSFER

Controller U5 responds to the device address (applied via the data line inputs on the lE lines) when the IEEE bus sets ATN true Notified by U5 via the DB data lines U6 addresses ROM U9 which determines if talk or listen operation is reshyquired If the talk mode is selected U6 enables PIAs U10 and Ull and causes data from the instrument to be transferred through the PIAs to controller U5 which transfers the data through the IB lines to U3 and U4 These buffers enabled by a TR2 level from U5 transfer the required data to the IEEE bus Transmisshysion of the individual data bytes is accomplished in proper sequence as a function of the handshake procedure The bus management lines (ATN IFC SRQ EOI and REN) insure that information flows through the interface lines in orderly fashion When the last data bytes (ASCII carriage returnline feed) are transmitted the DBA-488 sets EOI true to signal the end of the data transfer This feature permits compatible operation of the DBA-488 with the HPIB system The entire sequence is terminated by an Untalk command from the controller

When the DBA-488 listen address is received data applied to U3 and U4 is transshyferred to controller U5 The microprocessor then transfers the data from U5 to the PIA s which pass the information to the instrument An EOI or carriage return line feed is received to indicate the end of the data transfer and the listen sequence is terminated by an Unlisten command

-

2-5

SECTION 3

DATA BUS ADAPTER DBA-488-SR400

31 EQUIPMENT SUPPLlED

311 DBA-488 ORDERED WITH SR-400

When the DBA-488 is ordered together with an SR-400 SynchroResolver Simulator the DBA-488 is bracket mounted at the rear of the SR-400 and both units are elecshytrically intercOIlllected through a cable (See figure 3-1) AC power is applied to the DBA-488 when the SR-400 is turned on The only component not supplied is the standard mating connector to the IEEE bus

31 2 DBA-488 ORDERED SEPARATE LY

When a DBA-488 is ordered separately (for retrofit to an SR-400) a mating conshynector for the instrument interface is supplied but is not wired The standard mating connector for the IEEE bus is not supplied Mounting hardware is included as required

The DBA-488 is not equipped with a power switch Line voltage (115 volts at 60 Hz) is applied via the instrument interface connector If the SR-400 front panel POWER switch is to controi the DBA-488 this switch must be wired to pins on the instrument This requires a modification to the SR-400 as shown in table 3-1

NOTE

The DBA-488 may be ordered for operation from 220 volts 5060 Hz

32 UNPACKING

Carefully remove the equipment from the packaging material and inspect for possible damage Should any unit show signs of damage notify the nearest ILC Data Device Corporation field representative immediately

33 INTERCONNECTIONS

Table 3-1 shows the interconnections between the DBA-488 and SR-400 and indicates the function of each lead For SR-400 units being retrofitted switched AC line voltage (115 volts) may be wired to pins 39 and 40 of instrument connector J2 Conshynect pin 39 of J2 to the switched terminal of POWER switch S8 and pin 40 to pin L of instrument connector J1 The interconnecting cable must be wired as shown in table 3-1

3-1

-

JS )foOHZ

J(

SR - 400

cJl pz

INSTRUt1EAJT ~I---------JYMCHRO OR REllI~ roNAlECro~ RESOLVER OUTPUT

I---------REF INPUT INTeuroRCONAlECTlN(J CA13LE ___

DBA-488 NS TRUI-feNT INrEliRIICE CONNECTOR

PI

DJ3A- 4BB

STANOARD HATNy COAlNeCTOR IEEEshyBUS

Figure 3-1_ DBA-488-SR400 Connection Diagram

3-2

TABLE OF CONTENTS (CONTD)

SECTION 3 DATA BUS ADAPTER DBA-488-SR400 (Contd)

-

Paragraph

32

33

34

35

36

37

38

39

Figure

1-1

1-2

1-3

2-1

2-2

3-1

3-2

3-3

Table

1-1

3-1

3-2

3-3

Unpacking

Interconnections

Setting the Primary Device Address

Operating Procedure

Command Codes

ControI Word or Data Command Sequence (Listen)

Maintenance

DBA-488 Parts List

LIST OF ILLUSTRATIONS

DBA-488 Data Bus Adapter

Interface Connections and Bus Structure

Handshake Timing Sequence

DBA-488 Block Diagram

DBA-488 Data Bus Adapter Schematic Diagram

DBA-488-SR400 Connection Diagram bullbullbull

Listen Command Sequence Flow Chart

DBA-488 Location of Parts bull bull bull bull

LJST OF TABLES

Message Coding

DBA-488 to SR-400 Connections

Command Code Functions

DBA-488 Parts List

ii

~

3-1

3-1

3-3

3-3

3-3

3-3

3-5

3-5

Page

1-1

1-3

1-7

2-2

2-4

3-2

3-7

3-9

Page

1-5

3-4

3-6

3-8

SECTION 1

GENERAL DESCRIPTION

SCOPE OF MANUAL11

Sections 1 and 2 of this instruction manual describe the DBA-488 Data Bus Adapter (figure 1-1) manufactured by ILC Data Device Corporation Bohemia N Y Section 3 covers the DBA-488- ( ) the combination of the DBA-488 with one of DDCs synchro instruments (eg the DBA-488-SR103 DBA-488shySR400 DBA-488-SR202)

12 PURPOSE OF THE DBA-488 DATA BUS ADAPTER -The DBA-488 links DDCs synchro instruments to any programmable measurement instrument system such as computer controlled automatic test eqtlipment (ATE) or process controi system that operates from the IEEE-488-1975 General Purpose Interface Bus Operation of the DBA-488 is also fully compatible with the HewlettshyPackard HP-IB bus without programming changes Highlights of the IEEE-488shy1975 bus are included for reference in later paragraphs

-

Figure 1-1 DBA-488 Data Bus Adapter -1-1

13 PHYSICAL DESCRIPTION

The DBA-488 is eonfigured as a fully enclosed flat rectaIoular( assembly

81 X 61 X 17 (206 X 156 X 43 cm) that weighs less than 2-1 2 lbs (11 kg) Four holes in the lips of the eover facilitate mounting Two intershyface conneetors one for the IEEE-488 General Purpose Intcrfaee Bus (GPIB) and the other for the assoeiated instrument are mou nted on onc side of the unit Eight cA-ternally aeeessible miniature address seleet roeker switehcs are l-ocated between the two conncctors

14 THE IEEE-488 GPIB

The following abbreviated deseription of the IEEE-488 GPIB is ineluded for reference For eomplete bus details eonsult IEEE Standard 488-1975 Digital Interfaee for Programmable Instrumentation Copies of IEEE 488-1975 may be purchased from IEEE (Institute of Electrieal and Eleetronies Engineers) or from the American National Standards Institute both of whieh are loeated in New York N Y

141 BASIC STRUCTURE AND CONSTRAINTS

The IEEE bus is a byte-serial bit-parallel interfaee system It is structured with 16 lines consisting of the following

a Eight data bus lines for transmission of ASCII characters Data is asynchronous and gcncrally bidirectional

b Five bus management (control) signal lines

c Threc data byte transfer control lines (handshake)

The system includes constraints on the number of devices data rate total transmission length and is confincd to exchange of digital data

142 BASIC BUS TERlVllNOLOGY

aController - A devicc that can address other devices to listen or to talk

b Listener - A device that can be addressed through the bus to receive messhysages from another dcvice or the controller via the bus

c Talker - A device that can bc addressed through the bus to transmit messhysages to another device or the controller via the bus

NOTE

Controller listener and talker capabilitics may occur individually and collcetively in devices interconnected by the IEEE bus (See fig 1-2)

-

1-2

DATA OIOI- DI08

II I

DEVICE A

(TIUlt DAILY ) I ~ I ~ i- shy

II I

DEVCE B f----

(liSTEN ONLY) I

l II ~

I

DEICE C ( TALK liND r

LI5TEAI) I t-- shy

I II

DElleE D (TAL Ilt L5TEAJ I lAVD COIVTROL HIAlDSHAKE L-shy LINE S

III 1 NDACL~ N~FD

DAV-I

C EOI 5RGl 1lUJ- rnbull lfT1JJ

MA AJA6 EMENT (COAJTIiOL) L INeuro S

Figure 1-2 Interface Connections and Bus Structure

1-3

-

143 INTERFACE BUS SIGNAIB

NOTE

The IEEE Standard 488-1975 is defined for a negative logic format

Logic O Logic l

= =

False True

= =

High Low

(~2 OV) eO 8V)

a EOI (End or Identify) True levelon this bus management (control) line indicates end of multiple byte transfer When used with ATN performs parallel polling sequence

b SRQ (Service Request) Device sets this control line true when it requires service from the interface controller

c REN (Remote Enable) This controller driven line is used with other messhysages to select source of device programrning data (e g front panel or interface control)

d IFC (lnterface Clear) This controller driven Une is set true to place all ws-connected devices in their idle states

e ATN (Attentian) This control line specifies how data on the data lines are to be interpreted and which devices must respond to the data When ATN is true the DIOl-DI08 lines carry addresses or commands When ATN is set false the data lines carry data

f NDAC (Not Data Accepted) When set false by a device indicates that data has been accepted

this handshake line

g NRFD (Not Ready for Data) When set false by a device this handshake line indicates that the device is ready to accept data

h DAV (Data Valid) When set true this handshake line indicates that informashytion on the data lines is available and valid

i DIOl-m08 (Data Input-Output) These lines carry data in bit-parallel byteshyserial form Information on the lines represents either addresscommands or data depending on the logic state of the ATN line

j Unlisten Command This command is transrnitted on the data lines in conjunction with ATN true to terrninate the device listen function

k Untalk Command This command is transrnitted on the data lines in conjunction with ATN true to terrninate the device talk function

144 REMOTE MESSAGE CODING

Table l-l shows the coding of same of the control messages transmitted on the IEEE bus The l and O designatians refer to the logic states (negative logic convention) X = dont care Al-A5 specify the five address bits set within the device by the address select switches

1-4

) ] ] )) ) ] ] J J l J ) J J J J

~ I

CJ1

TABLE 1-1 MESSAGE CODING

IO Data Handshake Controi Message DI08 DI07 DI06 DI05 DI04 DI03 m02 mOl DAV NRFD NDAC ATN EOI SRQ IFC REN

ATN (Attention) x X X X X X X X X X X 1 X X X X

Data Byte D8 D7 D6 D5 D4 D3 D2 Dl X X X X X X X X

DAV (Data Available) X X X X X X X X 1 X X X X X X X

NRFD (Not Ready for Data) X X X X X X X X X 1 X X X X X X

NDAC (Not Data Accepted) X X X X X X X X X X 1 X X X X X

DCL (Device Clear) X ~ ~ 1 ~ 1 ~ ~ X X X X X X X X

End X X X X X X X X X X X X 1 X X X

Go to Local X O O O O O O 1 X X X X X X X X

Identify X X X X X X X X X X X X 1 X X X

IFC (Interface Clear) X X X X X X X X X X X X X X 1 X

MLA (My Listen Address) X ~ 1 A5 A4 A3 A2 Al X X X X X X X X

MTA (My Talk Address) X 1 ~ A5 A4 A3 A2 Al X X X X X X X X

REN (Remote Enable) X X X X X X X X X X X X X X X 1

SRQ (Service Required) X X X X X X X X X X X X X 1 X X

Unlisten X ~ 1 1 1 1 1 1 X X X X X X X X

Untalk X 1 ~ 1 1 1 1 1 X X X X X X X X

145 3-WIRE HANDSHAKE PROCEDURE

The 3-wire handshake procedure repeated for each byte transferred from a source to ot1e or more acceptors ensures that each listener is ready to accept data that the information on the data lines is valid and that the data has been accepted by all listeners The DAV line is controlled by the source (talker) the NDAC and NRFD lines are controlled by the acceptors (listeners)

FiglLre 1-3 illustrates the handshake cyc le for a source and several acceptors

a Both source and acceptors start in a known state The source initializes DA V to high (false data not valid) and the acceptors initialize NRFD to low (true none are ready for data) and NDAC to low (true none have accepted the data)

b The source checks that both NRFD and NDAC are not high then places the first data byte on the DIO lines (If both lines are sensed high the error condition ends the procedure)

c When all acceptors are ready to accept the first data byte NRFD goes high -d After data is settled and valid and the source has sensed NRFD high it sets DAV low (data is valid)

e The first acceptor sets NRFD low then accepts the f~rst byte receptors follow suit at their own rates

The other

f Each acceptor sets NDAC high to indicate that it has accepted

g When NDAC is sensed high by the source (after all acceptors have accepted the data byte) it sets DA V high (data on DIO lines no longer valid) At this point one data byte transfer has been completed

h Upon sensing DAV high the acceptors set NDAC low

i Source and acceptor initial conditions are now reestablished and the next handshake cycle may be initiated

1-6

ACCEPTOR OPERATiONSOURCE OPERATiON

READYNO TO ACCEPT DA TA

NO NRFD

DATA iS VALiD AND MAY NOW BE ACCEPTED

NO

YES --

Figure 1-3 Handshake Timing Sequence

1-7

-

-

-

SECTION 2

FUNCTIONAL DESCRIPTION OF DBA-488

INTRODUCTION21

This section provides a general functional description of the DBA-488 identifying the major input-output signals and covering basic signal flow Detailed step-byshystep operations within the DBA-488 are a function of the particular instrument and the stored program

22 BLOCK DIAGRAM DESCRIPTION (See figure 2-1)

Operation of the DBA-488 is supervised by a self-contained microprocessor in accordance with a program stored in an erasable programmable ROM Data transshyfer to and from the 16-line IEEE bus is mediated by the controller The 32 inputshyoutput lines at the instrument interface are independently programmed under microprocessor control for input or output data transfer according to the requireshyments of the particular instrument connected to the DBA-488 The device address preset manually by the user via the address select switches is transferred to the controller memory at power turn-on

23 FUNCTIONAL DESCRIPTION (See figure 2-2)

231 EQUIPMENT COMPLEMENT

The DBA-488 consists of four bus transceivers U1-U4 interface controller U5 microprocessor U6 tri-state buffers U7 and U8 ROM U9 and peripheral intershyface adapters (PIAs) U10 and Ull In addition a low voltage power supply consisting of power transformer T1 bridge rectifier CRA1 and voltage regulator VR1 provides 5 volts DC for operating the unit

232 TRANSCEIVERS U1 AND U2

Transceivers U1-U4 serve as the interface between the IEEE bus and the DBA-488 internal logic Transceivers U1 and U2 are used for bus management and handshake signals U3 and U4 accommodate the eight data lines Logic levels applied to the four transmit-receive inputs of each quad transceiver from controller U5 determine which section behaves as a bus driver or receiver for the associated bus line The T fR control for SRQ is always ired high (transmit) while those for REN 1FC and ATN are wired low (receive) The remaining signals are controlled by U5 The bus transceiver outputs meet all requirements of IEEE Std 488-1975

2-1

881T5512 Byr~ IO

ROM NTERshyB BITSFACE

tJ I BBIT

tJ ( DATA

INSTRUMENT IEEE INTERFACE488 32 10 UNS

BUS 8DITA LlNES 8 BIT5 PLUS

l DATA L JE S 8 CONT~

LINES 8 B I T 8 BITSL-----

mAlTROL IlDDRESStlleRO shySELECTPROCESSOR

SLJITCHES

Figure 2-1 DBA-488 Block Diagram bull

1 l ] ] I l J _J l l

-

-

-

233 INTERFACE CONTROLLER U5

Under the direction of microprocessor U6 interface controller U5 mediates the transfer of data between the DBA-488 and the IEEE bus Controller U5 decodes messages from the IEEE bus processes those directed to the DBA-488 and transshyfers messages to the internai data bus It should be noted that although the IEEE bus signals follow negative logic convention positive logic is used within the DBAshy488 (Thus the signal NRFD from the IEEE bus is designated RFD at the input of U5) The controller is equipped with internai registers that are selected by register select lines RSO RS1 and RS2 and chip select CS (via microprocessor address bits AO Al and A2 and Al4) in conjunction with the readwrite (RW) signals and ~2 clock from the microprocessor The registers accornmodate functions such as aringddress data in data out interrupt status etc Data transfer between U5 and U3 U4 is effected through the m - IB7 lines the DB~ - DB7 lines carry data between U5 and the internai data bus CS enables U5 and ~2 is a timing signal provided by U6

234 lVIICROPROCESSOR U6

The 8-bit microprocessor contains registers accumulators a 128 X 8 bit RAM and an internai clock The 16-line address bus (A~-A15) supervises the DBA-488 operations The 8-line bidirectional data bus (D~-D7) transfers data to and from memory and the peripheral devices Clock pulses at pin E (~2) are used for timing Upon receipt of an interrupt request (IRQ) from controller U5 (upon U5s receipt of DC L on the data lines) U6 completes its current instruction then cycles through an interrupt sequence that resets the microprocessor The read write (RW) output of U6 controls the read write status of controller U5 and PIAs U10 and Ull

235 ROM U9

Erasable prograrnmable ROM U9 stores the DBA-488 program in its 512 X 8 bit memory When enabled (CS input low) and strobed by a clock pulse from U6 (STR input) address bits A~-A8 are decoded and data transfer is effected on the DO~ - D07 lines

236 PIAS U10 AND Ull

PIAs U10 and Ull interface the DBA-488 with the DDC instrument Four 8-bit bidirectional data buses (PA~ - PA7 and PB~ - PB7) cornmunicate with the instrushyment an 8-bit bidirectional bus (D~ - D7) links the selected PIAs with the internai data bus Each chip is selected by ~ low via a U6 address routed through tri shystate buffer U8 Register select inputs (RS~ RS1) controlled by microprocessor U6 accress registers within each PIA which provide functions such as data direction control peripheral interface etc PIA readwrite operation is conshytrolled by the RIW input from U6

2-3

-------------------------------- I ISTR Ul-AENT 11rr E R r CE

P(gtG PM PAZ PA4 P80 PB+ PBz PB-p PAG PM PAz PAq PBlt PE ~-~PAl PA-5 PA~ PAI RESET PB7 PR - PS3 P81 PA PAS PA3 PAI PB Res PB Ps1

Po J I ~4+- ~a -0+ JJf- 1lt-+-14 ~1ls~ IIL 7 __ Z0 T2i l gt l ll ~J 2i1 ~ll~3 - - - ST l (T 3 T -41_3l-z let It f012Jtz2tz~t~d Z5

i2-1 I i I I (1 4 si 1111(1151 I~I iii lo

Po PO P O il 81 11 I si 4131 2 Ii I 11 151 141 b L) 8 1 1 2 141 121

Po UIO Ull Ull-j Ula

p AZ-BPIAI- 8 p IA2-APIAI-A $5i3ltgt(fJ $IB~~$ Coigt~~$6()CP

tgtrp D1 D21gt3 1gtlt 1gt5 D Di RfS RS0 RSI Cel R-w E c-S4gt cs 1 1gt1l1gt 1 DZ lgt3 D4- D5 [)( D7 RES es412S1C-SZ RW E CS(J CSI

3101 SSI 13III Il5l~ 2iI25~i13313lI3113121 251~712(13+1 J 3~ 135 r~ II SV ~~131 bl 281271211 3 +1 l u-fl 1 1elI

122 ~ -- t5V

~ t5V t5V bull Icamp tgtV I I bull 1 -O+shybull II 1 -- -----------+ ---- -------11--11-1---+------~c~ ~~ Al ~ ~IZ~~R3 AiIi

11 b14 aJ------t-U-~3DltPlO AfJ 32 DITIRI ze - cgtsltP ~~--t-- -~ J2 v 31 D2 U0

IlP e De1 30 D~ fp2 Eo I 2) DB2 ~ 2) 111-1----=--+-lt7 -~

(p SRQ 23 Jo [)8 3lt1 ~ Tl~ II i

Al

D-t~OSRQ lel ~1 -e DSIl REN 4 U I ID REN l2 ii DB4

bull 1 Ie Q __-=-2i--1 Dlt 1-i-1----+-lt7 -~ J IFC 1 ~J~ 14 IFe 21 11 DBS

bull I e-- l) us 1o-__2--i D7 13 D8ltu

I I I t~ ~~---t-ltJ -~ r-~======~~-~~~ ~_1 1= ~I L-_-4~--+------~4~O ReSI I I IN 1 8 3 -z AringT N = 2(P 6PI~bull I ( 37 E6 INDfgtC I l ( DAC Il 37 iCSO Al) I=-~---t-u -~ bull 1 bull ( lt136rp4J --____ 3=-4-1 RwiNRFOIO UL 0 RFD IS 3e iC51 Al I _ bull 1 (

--_--=30=-1 EXIll 14(1~lq _ i4- D- 1i1 3~ ilt 2- M 1 1 D7 1 0-- o-H bull I ( ~ M5B I - shy

I 3 c~ 1 I I-_---=3-11 XTALtO rPZGPIB I I III +gt

10

Rw

----J rGJll II 3~

1 D101 I~4 s

- D1o21 7 ---t-----~~t=t=~----~-~SV RE L I I 2 -HA-L-T3IDlogt 110 I U3 ASE

bull I I( )_ e 34 iP2 t5V --- 5 HR

4D1 04-I 15 1133 -- C4 1i111LI 4 IRQ I I I 1 +5 lgt 22 D() Vec ~ UlUe

Ibl C5 Pllltllto SoV

j3 1[)OW 2 IB4- -=- 32 Ph e I I I U~

L- el -- -NO

IB~ 3i U12shyIJ4 DlOl ~l 1ltgt T1gt I ~ F cp rP cp -=- (8V S~_ PIN 14- +sv~5D1071~2 U4 ) ID 1Bamp 3D DtvAGIA1oI1 --L ADAI Aringl A3 A~ Ar AIoA~ As 20 I - 35 ~NDPIN

~ D106 1 ~i iS 14- 1 B Z l eC i V C)C4 C3C2C Je ~3 AI5 t51

~ 2~

W I 11 e

1 2 I

zil u= 140 IRQ R- zo 1=-------- - ~TV

~ pto J 1 TI

4 tS~~

4 2

~gnlf[3EFI 13 c shy

121 Figure 2-2 1)BA-488 Data Bus (1] Ll- )4 Plt6 4 3 ~ 11-(NV Adapter ScWelnatic Diagram

2-4 1

237 POWER UP AND DEVICE ADDRESS

When power is applied to the DBA-488 the logic low level at test point TP2 (resulting from the uncharged state of C2) initializes U5 U10 UH and U6 The ASE (address select) output of U5 drops enabling the outputs of address switch S1 The five preset LSBs of Sl representing the primary device address are then transferred into a register in controller U5 for subsequent use

238 DATA TRANSFER

Controller U5 responds to the device address (applied via the data line inputs on the lE lines) when the IEEE bus sets ATN true Notified by U5 via the DB data lines U6 addresses ROM U9 which determines if talk or listen operation is reshyquired If the talk mode is selected U6 enables PIAs U10 and Ull and causes data from the instrument to be transferred through the PIAs to controller U5 which transfers the data through the IB lines to U3 and U4 These buffers enabled by a TR2 level from U5 transfer the required data to the IEEE bus Transmisshysion of the individual data bytes is accomplished in proper sequence as a function of the handshake procedure The bus management lines (ATN IFC SRQ EOI and REN) insure that information flows through the interface lines in orderly fashion When the last data bytes (ASCII carriage returnline feed) are transmitted the DBA-488 sets EOI true to signal the end of the data transfer This feature permits compatible operation of the DBA-488 with the HPIB system The entire sequence is terminated by an Untalk command from the controller

When the DBA-488 listen address is received data applied to U3 and U4 is transshyferred to controller U5 The microprocessor then transfers the data from U5 to the PIA s which pass the information to the instrument An EOI or carriage return line feed is received to indicate the end of the data transfer and the listen sequence is terminated by an Unlisten command

-

2-5

SECTION 3

DATA BUS ADAPTER DBA-488-SR400

31 EQUIPMENT SUPPLlED

311 DBA-488 ORDERED WITH SR-400

When the DBA-488 is ordered together with an SR-400 SynchroResolver Simulator the DBA-488 is bracket mounted at the rear of the SR-400 and both units are elecshytrically intercOIlllected through a cable (See figure 3-1) AC power is applied to the DBA-488 when the SR-400 is turned on The only component not supplied is the standard mating connector to the IEEE bus

31 2 DBA-488 ORDERED SEPARATE LY

When a DBA-488 is ordered separately (for retrofit to an SR-400) a mating conshynector for the instrument interface is supplied but is not wired The standard mating connector for the IEEE bus is not supplied Mounting hardware is included as required

The DBA-488 is not equipped with a power switch Line voltage (115 volts at 60 Hz) is applied via the instrument interface connector If the SR-400 front panel POWER switch is to controi the DBA-488 this switch must be wired to pins on the instrument This requires a modification to the SR-400 as shown in table 3-1

NOTE

The DBA-488 may be ordered for operation from 220 volts 5060 Hz

32 UNPACKING

Carefully remove the equipment from the packaging material and inspect for possible damage Should any unit show signs of damage notify the nearest ILC Data Device Corporation field representative immediately

33 INTERCONNECTIONS

Table 3-1 shows the interconnections between the DBA-488 and SR-400 and indicates the function of each lead For SR-400 units being retrofitted switched AC line voltage (115 volts) may be wired to pins 39 and 40 of instrument connector J2 Conshynect pin 39 of J2 to the switched terminal of POWER switch S8 and pin 40 to pin L of instrument connector J1 The interconnecting cable must be wired as shown in table 3-1

3-1

-

JS )foOHZ

J(

SR - 400

cJl pz

INSTRUt1EAJT ~I---------JYMCHRO OR REllI~ roNAlECro~ RESOLVER OUTPUT

I---------REF INPUT INTeuroRCONAlECTlN(J CA13LE ___

DBA-488 NS TRUI-feNT INrEliRIICE CONNECTOR

PI

DJ3A- 4BB

STANOARD HATNy COAlNeCTOR IEEEshyBUS

Figure 3-1_ DBA-488-SR400 Connection Diagram

3-2

SECTION 1

GENERAL DESCRIPTION

SCOPE OF MANUAL11

Sections 1 and 2 of this instruction manual describe the DBA-488 Data Bus Adapter (figure 1-1) manufactured by ILC Data Device Corporation Bohemia N Y Section 3 covers the DBA-488- ( ) the combination of the DBA-488 with one of DDCs synchro instruments (eg the DBA-488-SR103 DBA-488shySR400 DBA-488-SR202)

12 PURPOSE OF THE DBA-488 DATA BUS ADAPTER -The DBA-488 links DDCs synchro instruments to any programmable measurement instrument system such as computer controlled automatic test eqtlipment (ATE) or process controi system that operates from the IEEE-488-1975 General Purpose Interface Bus Operation of the DBA-488 is also fully compatible with the HewlettshyPackard HP-IB bus without programming changes Highlights of the IEEE-488shy1975 bus are included for reference in later paragraphs

-

Figure 1-1 DBA-488 Data Bus Adapter -1-1

13 PHYSICAL DESCRIPTION

The DBA-488 is eonfigured as a fully enclosed flat rectaIoular( assembly

81 X 61 X 17 (206 X 156 X 43 cm) that weighs less than 2-1 2 lbs (11 kg) Four holes in the lips of the eover facilitate mounting Two intershyface conneetors one for the IEEE-488 General Purpose Intcrfaee Bus (GPIB) and the other for the assoeiated instrument are mou nted on onc side of the unit Eight cA-ternally aeeessible miniature address seleet roeker switehcs are l-ocated between the two conncctors

14 THE IEEE-488 GPIB

The following abbreviated deseription of the IEEE-488 GPIB is ineluded for reference For eomplete bus details eonsult IEEE Standard 488-1975 Digital Interfaee for Programmable Instrumentation Copies of IEEE 488-1975 may be purchased from IEEE (Institute of Electrieal and Eleetronies Engineers) or from the American National Standards Institute both of whieh are loeated in New York N Y

141 BASIC STRUCTURE AND CONSTRAINTS

The IEEE bus is a byte-serial bit-parallel interfaee system It is structured with 16 lines consisting of the following

a Eight data bus lines for transmission of ASCII characters Data is asynchronous and gcncrally bidirectional

b Five bus management (control) signal lines

c Threc data byte transfer control lines (handshake)

The system includes constraints on the number of devices data rate total transmission length and is confincd to exchange of digital data

142 BASIC BUS TERlVllNOLOGY

aController - A devicc that can address other devices to listen or to talk

b Listener - A device that can be addressed through the bus to receive messhysages from another dcvice or the controller via the bus

c Talker - A device that can bc addressed through the bus to transmit messhysages to another device or the controller via the bus

NOTE

Controller listener and talker capabilitics may occur individually and collcetively in devices interconnected by the IEEE bus (See fig 1-2)

-

1-2

DATA OIOI- DI08

II I

DEVICE A

(TIUlt DAILY ) I ~ I ~ i- shy

II I

DEVCE B f----

(liSTEN ONLY) I

l II ~

I

DEICE C ( TALK liND r

LI5TEAI) I t-- shy

I II

DElleE D (TAL Ilt L5TEAJ I lAVD COIVTROL HIAlDSHAKE L-shy LINE S

III 1 NDACL~ N~FD

DAV-I

C EOI 5RGl 1lUJ- rnbull lfT1JJ

MA AJA6 EMENT (COAJTIiOL) L INeuro S

Figure 1-2 Interface Connections and Bus Structure

1-3

-

143 INTERFACE BUS SIGNAIB

NOTE

The IEEE Standard 488-1975 is defined for a negative logic format

Logic O Logic l

= =

False True

= =

High Low

(~2 OV) eO 8V)

a EOI (End or Identify) True levelon this bus management (control) line indicates end of multiple byte transfer When used with ATN performs parallel polling sequence

b SRQ (Service Request) Device sets this control line true when it requires service from the interface controller

c REN (Remote Enable) This controller driven line is used with other messhysages to select source of device programrning data (e g front panel or interface control)

d IFC (lnterface Clear) This controller driven Une is set true to place all ws-connected devices in their idle states

e ATN (Attentian) This control line specifies how data on the data lines are to be interpreted and which devices must respond to the data When ATN is true the DIOl-DI08 lines carry addresses or commands When ATN is set false the data lines carry data

f NDAC (Not Data Accepted) When set false by a device indicates that data has been accepted

this handshake line

g NRFD (Not Ready for Data) When set false by a device this handshake line indicates that the device is ready to accept data

h DAV (Data Valid) When set true this handshake line indicates that informashytion on the data lines is available and valid

i DIOl-m08 (Data Input-Output) These lines carry data in bit-parallel byteshyserial form Information on the lines represents either addresscommands or data depending on the logic state of the ATN line

j Unlisten Command This command is transrnitted on the data lines in conjunction with ATN true to terrninate the device listen function

k Untalk Command This command is transrnitted on the data lines in conjunction with ATN true to terrninate the device talk function

144 REMOTE MESSAGE CODING

Table l-l shows the coding of same of the control messages transmitted on the IEEE bus The l and O designatians refer to the logic states (negative logic convention) X = dont care Al-A5 specify the five address bits set within the device by the address select switches

1-4

) ] ] )) ) ] ] J J l J ) J J J J

~ I

CJ1

TABLE 1-1 MESSAGE CODING

IO Data Handshake Controi Message DI08 DI07 DI06 DI05 DI04 DI03 m02 mOl DAV NRFD NDAC ATN EOI SRQ IFC REN

ATN (Attention) x X X X X X X X X X X 1 X X X X

Data Byte D8 D7 D6 D5 D4 D3 D2 Dl X X X X X X X X

DAV (Data Available) X X X X X X X X 1 X X X X X X X

NRFD (Not Ready for Data) X X X X X X X X X 1 X X X X X X

NDAC (Not Data Accepted) X X X X X X X X X X 1 X X X X X

DCL (Device Clear) X ~ ~ 1 ~ 1 ~ ~ X X X X X X X X

End X X X X X X X X X X X X 1 X X X

Go to Local X O O O O O O 1 X X X X X X X X

Identify X X X X X X X X X X X X 1 X X X

IFC (Interface Clear) X X X X X X X X X X X X X X 1 X

MLA (My Listen Address) X ~ 1 A5 A4 A3 A2 Al X X X X X X X X

MTA (My Talk Address) X 1 ~ A5 A4 A3 A2 Al X X X X X X X X

REN (Remote Enable) X X X X X X X X X X X X X X X 1

SRQ (Service Required) X X X X X X X X X X X X X 1 X X

Unlisten X ~ 1 1 1 1 1 1 X X X X X X X X

Untalk X 1 ~ 1 1 1 1 1 X X X X X X X X

145 3-WIRE HANDSHAKE PROCEDURE

The 3-wire handshake procedure repeated for each byte transferred from a source to ot1e or more acceptors ensures that each listener is ready to accept data that the information on the data lines is valid and that the data has been accepted by all listeners The DAV line is controlled by the source (talker) the NDAC and NRFD lines are controlled by the acceptors (listeners)

FiglLre 1-3 illustrates the handshake cyc le for a source and several acceptors

a Both source and acceptors start in a known state The source initializes DA V to high (false data not valid) and the acceptors initialize NRFD to low (true none are ready for data) and NDAC to low (true none have accepted the data)

b The source checks that both NRFD and NDAC are not high then places the first data byte on the DIO lines (If both lines are sensed high the error condition ends the procedure)

c When all acceptors are ready to accept the first data byte NRFD goes high -d After data is settled and valid and the source has sensed NRFD high it sets DAV low (data is valid)

e The first acceptor sets NRFD low then accepts the f~rst byte receptors follow suit at their own rates

The other

f Each acceptor sets NDAC high to indicate that it has accepted

g When NDAC is sensed high by the source (after all acceptors have accepted the data byte) it sets DA V high (data on DIO lines no longer valid) At this point one data byte transfer has been completed

h Upon sensing DAV high the acceptors set NDAC low

i Source and acceptor initial conditions are now reestablished and the next handshake cycle may be initiated

1-6

ACCEPTOR OPERATiONSOURCE OPERATiON

READYNO TO ACCEPT DA TA

NO NRFD

DATA iS VALiD AND MAY NOW BE ACCEPTED

NO

YES --

Figure 1-3 Handshake Timing Sequence

1-7

-

-

-

SECTION 2

FUNCTIONAL DESCRIPTION OF DBA-488

INTRODUCTION21

This section provides a general functional description of the DBA-488 identifying the major input-output signals and covering basic signal flow Detailed step-byshystep operations within the DBA-488 are a function of the particular instrument and the stored program

22 BLOCK DIAGRAM DESCRIPTION (See figure 2-1)

Operation of the DBA-488 is supervised by a self-contained microprocessor in accordance with a program stored in an erasable programmable ROM Data transshyfer to and from the 16-line IEEE bus is mediated by the controller The 32 inputshyoutput lines at the instrument interface are independently programmed under microprocessor control for input or output data transfer according to the requireshyments of the particular instrument connected to the DBA-488 The device address preset manually by the user via the address select switches is transferred to the controller memory at power turn-on

23 FUNCTIONAL DESCRIPTION (See figure 2-2)

231 EQUIPMENT COMPLEMENT

The DBA-488 consists of four bus transceivers U1-U4 interface controller U5 microprocessor U6 tri-state buffers U7 and U8 ROM U9 and peripheral intershyface adapters (PIAs) U10 and Ull In addition a low voltage power supply consisting of power transformer T1 bridge rectifier CRA1 and voltage regulator VR1 provides 5 volts DC for operating the unit

232 TRANSCEIVERS U1 AND U2

Transceivers U1-U4 serve as the interface between the IEEE bus and the DBA-488 internal logic Transceivers U1 and U2 are used for bus management and handshake signals U3 and U4 accommodate the eight data lines Logic levels applied to the four transmit-receive inputs of each quad transceiver from controller U5 determine which section behaves as a bus driver or receiver for the associated bus line The T fR control for SRQ is always ired high (transmit) while those for REN 1FC and ATN are wired low (receive) The remaining signals are controlled by U5 The bus transceiver outputs meet all requirements of IEEE Std 488-1975

2-1

881T5512 Byr~ IO

ROM NTERshyB BITSFACE

tJ I BBIT

tJ ( DATA

INSTRUMENT IEEE INTERFACE488 32 10 UNS

BUS 8DITA LlNES 8 BIT5 PLUS

l DATA L JE S 8 CONT~

LINES 8 B I T 8 BITSL-----

mAlTROL IlDDRESStlleRO shySELECTPROCESSOR

SLJITCHES

Figure 2-1 DBA-488 Block Diagram bull

1 l ] ] I l J _J l l

-

-

-

233 INTERFACE CONTROLLER U5

Under the direction of microprocessor U6 interface controller U5 mediates the transfer of data between the DBA-488 and the IEEE bus Controller U5 decodes messages from the IEEE bus processes those directed to the DBA-488 and transshyfers messages to the internai data bus It should be noted that although the IEEE bus signals follow negative logic convention positive logic is used within the DBAshy488 (Thus the signal NRFD from the IEEE bus is designated RFD at the input of U5) The controller is equipped with internai registers that are selected by register select lines RSO RS1 and RS2 and chip select CS (via microprocessor address bits AO Al and A2 and Al4) in conjunction with the readwrite (RW) signals and ~2 clock from the microprocessor The registers accornmodate functions such as aringddress data in data out interrupt status etc Data transfer between U5 and U3 U4 is effected through the m - IB7 lines the DB~ - DB7 lines carry data between U5 and the internai data bus CS enables U5 and ~2 is a timing signal provided by U6

234 lVIICROPROCESSOR U6

The 8-bit microprocessor contains registers accumulators a 128 X 8 bit RAM and an internai clock The 16-line address bus (A~-A15) supervises the DBA-488 operations The 8-line bidirectional data bus (D~-D7) transfers data to and from memory and the peripheral devices Clock pulses at pin E (~2) are used for timing Upon receipt of an interrupt request (IRQ) from controller U5 (upon U5s receipt of DC L on the data lines) U6 completes its current instruction then cycles through an interrupt sequence that resets the microprocessor The read write (RW) output of U6 controls the read write status of controller U5 and PIAs U10 and Ull

235 ROM U9

Erasable prograrnmable ROM U9 stores the DBA-488 program in its 512 X 8 bit memory When enabled (CS input low) and strobed by a clock pulse from U6 (STR input) address bits A~-A8 are decoded and data transfer is effected on the DO~ - D07 lines

236 PIAS U10 AND Ull

PIAs U10 and Ull interface the DBA-488 with the DDC instrument Four 8-bit bidirectional data buses (PA~ - PA7 and PB~ - PB7) cornmunicate with the instrushyment an 8-bit bidirectional bus (D~ - D7) links the selected PIAs with the internai data bus Each chip is selected by ~ low via a U6 address routed through tri shystate buffer U8 Register select inputs (RS~ RS1) controlled by microprocessor U6 accress registers within each PIA which provide functions such as data direction control peripheral interface etc PIA readwrite operation is conshytrolled by the RIW input from U6

2-3

-------------------------------- I ISTR Ul-AENT 11rr E R r CE

P(gtG PM PAZ PA4 P80 PB+ PBz PB-p PAG PM PAz PAq PBlt PE ~-~PAl PA-5 PA~ PAI RESET PB7 PR - PS3 P81 PA PAS PA3 PAI PB Res PB Ps1

Po J I ~4+- ~a -0+ JJf- 1lt-+-14 ~1ls~ IIL 7 __ Z0 T2i l gt l ll ~J 2i1 ~ll~3 - - - ST l (T 3 T -41_3l-z let It f012Jtz2tz~t~d Z5

i2-1 I i I I (1 4 si 1111(1151 I~I iii lo

Po PO P O il 81 11 I si 4131 2 Ii I 11 151 141 b L) 8 1 1 2 141 121

Po UIO Ull Ull-j Ula

p AZ-BPIAI- 8 p IA2-APIAI-A $5i3ltgt(fJ $IB~~$ Coigt~~$6()CP

tgtrp D1 D21gt3 1gtlt 1gt5 D Di RfS RS0 RSI Cel R-w E c-S4gt cs 1 1gt1l1gt 1 DZ lgt3 D4- D5 [)( D7 RES es412S1C-SZ RW E CS(J CSI

3101 SSI 13III Il5l~ 2iI25~i13313lI3113121 251~712(13+1 J 3~ 135 r~ II SV ~~131 bl 281271211 3 +1 l u-fl 1 1elI

122 ~ -- t5V

~ t5V t5V bull Icamp tgtV I I bull 1 -O+shybull II 1 -- -----------+ ---- -------11--11-1---+------~c~ ~~ Al ~ ~IZ~~R3 AiIi

11 b14 aJ------t-U-~3DltPlO AfJ 32 DITIRI ze - cgtsltP ~~--t-- -~ J2 v 31 D2 U0

IlP e De1 30 D~ fp2 Eo I 2) DB2 ~ 2) 111-1----=--+-lt7 -~

(p SRQ 23 Jo [)8 3lt1 ~ Tl~ II i

Al

D-t~OSRQ lel ~1 -e DSIl REN 4 U I ID REN l2 ii DB4

bull 1 Ie Q __-=-2i--1 Dlt 1-i-1----+-lt7 -~ J IFC 1 ~J~ 14 IFe 21 11 DBS

bull I e-- l) us 1o-__2--i D7 13 D8ltu

I I I t~ ~~---t-ltJ -~ r-~======~~-~~~ ~_1 1= ~I L-_-4~--+------~4~O ReSI I I IN 1 8 3 -z AringT N = 2(P 6PI~bull I ( 37 E6 INDfgtC I l ( DAC Il 37 iCSO Al) I=-~---t-u -~ bull 1 bull ( lt136rp4J --____ 3=-4-1 RwiNRFOIO UL 0 RFD IS 3e iC51 Al I _ bull 1 (

--_--=30=-1 EXIll 14(1~lq _ i4- D- 1i1 3~ ilt 2- M 1 1 D7 1 0-- o-H bull I ( ~ M5B I - shy

I 3 c~ 1 I I-_---=3-11 XTALtO rPZGPIB I I III +gt

10

Rw

----J rGJll II 3~

1 D101 I~4 s

- D1o21 7 ---t-----~~t=t=~----~-~SV RE L I I 2 -HA-L-T3IDlogt 110 I U3 ASE

bull I I( )_ e 34 iP2 t5V --- 5 HR

4D1 04-I 15 1133 -- C4 1i111LI 4 IRQ I I I 1 +5 lgt 22 D() Vec ~ UlUe

Ibl C5 Pllltllto SoV

j3 1[)OW 2 IB4- -=- 32 Ph e I I I U~

L- el -- -NO

IB~ 3i U12shyIJ4 DlOl ~l 1ltgt T1gt I ~ F cp rP cp -=- (8V S~_ PIN 14- +sv~5D1071~2 U4 ) ID 1Bamp 3D DtvAGIA1oI1 --L ADAI Aringl A3 A~ Ar AIoA~ As 20 I - 35 ~NDPIN

~ D106 1 ~i iS 14- 1 B Z l eC i V C)C4 C3C2C Je ~3 AI5 t51

~ 2~

W I 11 e

1 2 I

zil u= 140 IRQ R- zo 1=-------- - ~TV

~ pto J 1 TI

4 tS~~

4 2

~gnlf[3EFI 13 c shy

121 Figure 2-2 1)BA-488 Data Bus (1] Ll- )4 Plt6 4 3 ~ 11-(NV Adapter ScWelnatic Diagram

2-4 1

237 POWER UP AND DEVICE ADDRESS

When power is applied to the DBA-488 the logic low level at test point TP2 (resulting from the uncharged state of C2) initializes U5 U10 UH and U6 The ASE (address select) output of U5 drops enabling the outputs of address switch S1 The five preset LSBs of Sl representing the primary device address are then transferred into a register in controller U5 for subsequent use

238 DATA TRANSFER

Controller U5 responds to the device address (applied via the data line inputs on the lE lines) when the IEEE bus sets ATN true Notified by U5 via the DB data lines U6 addresses ROM U9 which determines if talk or listen operation is reshyquired If the talk mode is selected U6 enables PIAs U10 and Ull and causes data from the instrument to be transferred through the PIAs to controller U5 which transfers the data through the IB lines to U3 and U4 These buffers enabled by a TR2 level from U5 transfer the required data to the IEEE bus Transmisshysion of the individual data bytes is accomplished in proper sequence as a function of the handshake procedure The bus management lines (ATN IFC SRQ EOI and REN) insure that information flows through the interface lines in orderly fashion When the last data bytes (ASCII carriage returnline feed) are transmitted the DBA-488 sets EOI true to signal the end of the data transfer This feature permits compatible operation of the DBA-488 with the HPIB system The entire sequence is terminated by an Untalk command from the controller

When the DBA-488 listen address is received data applied to U3 and U4 is transshyferred to controller U5 The microprocessor then transfers the data from U5 to the PIA s which pass the information to the instrument An EOI or carriage return line feed is received to indicate the end of the data transfer and the listen sequence is terminated by an Unlisten command

-

2-5

SECTION 3

DATA BUS ADAPTER DBA-488-SR400

31 EQUIPMENT SUPPLlED

311 DBA-488 ORDERED WITH SR-400

When the DBA-488 is ordered together with an SR-400 SynchroResolver Simulator the DBA-488 is bracket mounted at the rear of the SR-400 and both units are elecshytrically intercOIlllected through a cable (See figure 3-1) AC power is applied to the DBA-488 when the SR-400 is turned on The only component not supplied is the standard mating connector to the IEEE bus

31 2 DBA-488 ORDERED SEPARATE LY

When a DBA-488 is ordered separately (for retrofit to an SR-400) a mating conshynector for the instrument interface is supplied but is not wired The standard mating connector for the IEEE bus is not supplied Mounting hardware is included as required

The DBA-488 is not equipped with a power switch Line voltage (115 volts at 60 Hz) is applied via the instrument interface connector If the SR-400 front panel POWER switch is to controi the DBA-488 this switch must be wired to pins on the instrument This requires a modification to the SR-400 as shown in table 3-1

NOTE

The DBA-488 may be ordered for operation from 220 volts 5060 Hz

32 UNPACKING

Carefully remove the equipment from the packaging material and inspect for possible damage Should any unit show signs of damage notify the nearest ILC Data Device Corporation field representative immediately

33 INTERCONNECTIONS

Table 3-1 shows the interconnections between the DBA-488 and SR-400 and indicates the function of each lead For SR-400 units being retrofitted switched AC line voltage (115 volts) may be wired to pins 39 and 40 of instrument connector J2 Conshynect pin 39 of J2 to the switched terminal of POWER switch S8 and pin 40 to pin L of instrument connector J1 The interconnecting cable must be wired as shown in table 3-1

3-1

-

JS )foOHZ

J(

SR - 400

cJl pz

INSTRUt1EAJT ~I---------JYMCHRO OR REllI~ roNAlECro~ RESOLVER OUTPUT

I---------REF INPUT INTeuroRCONAlECTlN(J CA13LE ___

DBA-488 NS TRUI-feNT INrEliRIICE CONNECTOR

PI

DJ3A- 4BB

STANOARD HATNy COAlNeCTOR IEEEshyBUS

Figure 3-1_ DBA-488-SR400 Connection Diagram

3-2

13 PHYSICAL DESCRIPTION

The DBA-488 is eonfigured as a fully enclosed flat rectaIoular( assembly

81 X 61 X 17 (206 X 156 X 43 cm) that weighs less than 2-1 2 lbs (11 kg) Four holes in the lips of the eover facilitate mounting Two intershyface conneetors one for the IEEE-488 General Purpose Intcrfaee Bus (GPIB) and the other for the assoeiated instrument are mou nted on onc side of the unit Eight cA-ternally aeeessible miniature address seleet roeker switehcs are l-ocated between the two conncctors

14 THE IEEE-488 GPIB

The following abbreviated deseription of the IEEE-488 GPIB is ineluded for reference For eomplete bus details eonsult IEEE Standard 488-1975 Digital Interfaee for Programmable Instrumentation Copies of IEEE 488-1975 may be purchased from IEEE (Institute of Electrieal and Eleetronies Engineers) or from the American National Standards Institute both of whieh are loeated in New York N Y

141 BASIC STRUCTURE AND CONSTRAINTS

The IEEE bus is a byte-serial bit-parallel interfaee system It is structured with 16 lines consisting of the following

a Eight data bus lines for transmission of ASCII characters Data is asynchronous and gcncrally bidirectional

b Five bus management (control) signal lines

c Threc data byte transfer control lines (handshake)

The system includes constraints on the number of devices data rate total transmission length and is confincd to exchange of digital data

142 BASIC BUS TERlVllNOLOGY

aController - A devicc that can address other devices to listen or to talk

b Listener - A device that can be addressed through the bus to receive messhysages from another dcvice or the controller via the bus

c Talker - A device that can bc addressed through the bus to transmit messhysages to another device or the controller via the bus

NOTE

Controller listener and talker capabilitics may occur individually and collcetively in devices interconnected by the IEEE bus (See fig 1-2)

-

1-2

DATA OIOI- DI08

II I

DEVICE A

(TIUlt DAILY ) I ~ I ~ i- shy

II I

DEVCE B f----

(liSTEN ONLY) I

l II ~

I

DEICE C ( TALK liND r

LI5TEAI) I t-- shy

I II

DElleE D (TAL Ilt L5TEAJ I lAVD COIVTROL HIAlDSHAKE L-shy LINE S

III 1 NDACL~ N~FD

DAV-I

C EOI 5RGl 1lUJ- rnbull lfT1JJ

MA AJA6 EMENT (COAJTIiOL) L INeuro S

Figure 1-2 Interface Connections and Bus Structure

1-3

-

143 INTERFACE BUS SIGNAIB

NOTE

The IEEE Standard 488-1975 is defined for a negative logic format

Logic O Logic l

= =

False True

= =

High Low

(~2 OV) eO 8V)

a EOI (End or Identify) True levelon this bus management (control) line indicates end of multiple byte transfer When used with ATN performs parallel polling sequence

b SRQ (Service Request) Device sets this control line true when it requires service from the interface controller

c REN (Remote Enable) This controller driven line is used with other messhysages to select source of device programrning data (e g front panel or interface control)

d IFC (lnterface Clear) This controller driven Une is set true to place all ws-connected devices in their idle states

e ATN (Attentian) This control line specifies how data on the data lines are to be interpreted and which devices must respond to the data When ATN is true the DIOl-DI08 lines carry addresses or commands When ATN is set false the data lines carry data

f NDAC (Not Data Accepted) When set false by a device indicates that data has been accepted

this handshake line

g NRFD (Not Ready for Data) When set false by a device this handshake line indicates that the device is ready to accept data

h DAV (Data Valid) When set true this handshake line indicates that informashytion on the data lines is available and valid

i DIOl-m08 (Data Input-Output) These lines carry data in bit-parallel byteshyserial form Information on the lines represents either addresscommands or data depending on the logic state of the ATN line

j Unlisten Command This command is transrnitted on the data lines in conjunction with ATN true to terrninate the device listen function

k Untalk Command This command is transrnitted on the data lines in conjunction with ATN true to terrninate the device talk function

144 REMOTE MESSAGE CODING

Table l-l shows the coding of same of the control messages transmitted on the IEEE bus The l and O designatians refer to the logic states (negative logic convention) X = dont care Al-A5 specify the five address bits set within the device by the address select switches

1-4

) ] ] )) ) ] ] J J l J ) J J J J

~ I

CJ1

TABLE 1-1 MESSAGE CODING

IO Data Handshake Controi Message DI08 DI07 DI06 DI05 DI04 DI03 m02 mOl DAV NRFD NDAC ATN EOI SRQ IFC REN

ATN (Attention) x X X X X X X X X X X 1 X X X X

Data Byte D8 D7 D6 D5 D4 D3 D2 Dl X X X X X X X X

DAV (Data Available) X X X X X X X X 1 X X X X X X X

NRFD (Not Ready for Data) X X X X X X X X X 1 X X X X X X

NDAC (Not Data Accepted) X X X X X X X X X X 1 X X X X X

DCL (Device Clear) X ~ ~ 1 ~ 1 ~ ~ X X X X X X X X

End X X X X X X X X X X X X 1 X X X

Go to Local X O O O O O O 1 X X X X X X X X

Identify X X X X X X X X X X X X 1 X X X

IFC (Interface Clear) X X X X X X X X X X X X X X 1 X

MLA (My Listen Address) X ~ 1 A5 A4 A3 A2 Al X X X X X X X X

MTA (My Talk Address) X 1 ~ A5 A4 A3 A2 Al X X X X X X X X

REN (Remote Enable) X X X X X X X X X X X X X X X 1

SRQ (Service Required) X X X X X X X X X X X X X 1 X X

Unlisten X ~ 1 1 1 1 1 1 X X X X X X X X

Untalk X 1 ~ 1 1 1 1 1 X X X X X X X X

145 3-WIRE HANDSHAKE PROCEDURE

The 3-wire handshake procedure repeated for each byte transferred from a source to ot1e or more acceptors ensures that each listener is ready to accept data that the information on the data lines is valid and that the data has been accepted by all listeners The DAV line is controlled by the source (talker) the NDAC and NRFD lines are controlled by the acceptors (listeners)

FiglLre 1-3 illustrates the handshake cyc le for a source and several acceptors

a Both source and acceptors start in a known state The source initializes DA V to high (false data not valid) and the acceptors initialize NRFD to low (true none are ready for data) and NDAC to low (true none have accepted the data)

b The source checks that both NRFD and NDAC are not high then places the first data byte on the DIO lines (If both lines are sensed high the error condition ends the procedure)

c When all acceptors are ready to accept the first data byte NRFD goes high -d After data is settled and valid and the source has sensed NRFD high it sets DAV low (data is valid)

e The first acceptor sets NRFD low then accepts the f~rst byte receptors follow suit at their own rates

The other

f Each acceptor sets NDAC high to indicate that it has accepted

g When NDAC is sensed high by the source (after all acceptors have accepted the data byte) it sets DA V high (data on DIO lines no longer valid) At this point one data byte transfer has been completed

h Upon sensing DAV high the acceptors set NDAC low

i Source and acceptor initial conditions are now reestablished and the next handshake cycle may be initiated

1-6

ACCEPTOR OPERATiONSOURCE OPERATiON

READYNO TO ACCEPT DA TA

NO NRFD

DATA iS VALiD AND MAY NOW BE ACCEPTED

NO

YES --

Figure 1-3 Handshake Timing Sequence

1-7

-

-

-

SECTION 2

FUNCTIONAL DESCRIPTION OF DBA-488

INTRODUCTION21

This section provides a general functional description of the DBA-488 identifying the major input-output signals and covering basic signal flow Detailed step-byshystep operations within the DBA-488 are a function of the particular instrument and the stored program

22 BLOCK DIAGRAM DESCRIPTION (See figure 2-1)

Operation of the DBA-488 is supervised by a self-contained microprocessor in accordance with a program stored in an erasable programmable ROM Data transshyfer to and from the 16-line IEEE bus is mediated by the controller The 32 inputshyoutput lines at the instrument interface are independently programmed under microprocessor control for input or output data transfer according to the requireshyments of the particular instrument connected to the DBA-488 The device address preset manually by the user via the address select switches is transferred to the controller memory at power turn-on

23 FUNCTIONAL DESCRIPTION (See figure 2-2)

231 EQUIPMENT COMPLEMENT

The DBA-488 consists of four bus transceivers U1-U4 interface controller U5 microprocessor U6 tri-state buffers U7 and U8 ROM U9 and peripheral intershyface adapters (PIAs) U10 and Ull In addition a low voltage power supply consisting of power transformer T1 bridge rectifier CRA1 and voltage regulator VR1 provides 5 volts DC for operating the unit

232 TRANSCEIVERS U1 AND U2

Transceivers U1-U4 serve as the interface between the IEEE bus and the DBA-488 internal logic Transceivers U1 and U2 are used for bus management and handshake signals U3 and U4 accommodate the eight data lines Logic levels applied to the four transmit-receive inputs of each quad transceiver from controller U5 determine which section behaves as a bus driver or receiver for the associated bus line The T fR control for SRQ is always ired high (transmit) while those for REN 1FC and ATN are wired low (receive) The remaining signals are controlled by U5 The bus transceiver outputs meet all requirements of IEEE Std 488-1975

2-1

881T5512 Byr~ IO

ROM NTERshyB BITSFACE

tJ I BBIT

tJ ( DATA

INSTRUMENT IEEE INTERFACE488 32 10 UNS

BUS 8DITA LlNES 8 BIT5 PLUS

l DATA L JE S 8 CONT~

LINES 8 B I T 8 BITSL-----

mAlTROL IlDDRESStlleRO shySELECTPROCESSOR

SLJITCHES

Figure 2-1 DBA-488 Block Diagram bull

1 l ] ] I l J _J l l

-

-

-

233 INTERFACE CONTROLLER U5

Under the direction of microprocessor U6 interface controller U5 mediates the transfer of data between the DBA-488 and the IEEE bus Controller U5 decodes messages from the IEEE bus processes those directed to the DBA-488 and transshyfers messages to the internai data bus It should be noted that although the IEEE bus signals follow negative logic convention positive logic is used within the DBAshy488 (Thus the signal NRFD from the IEEE bus is designated RFD at the input of U5) The controller is equipped with internai registers that are selected by register select lines RSO RS1 and RS2 and chip select CS (via microprocessor address bits AO Al and A2 and Al4) in conjunction with the readwrite (RW) signals and ~2 clock from the microprocessor The registers accornmodate functions such as aringddress data in data out interrupt status etc Data transfer between U5 and U3 U4 is effected through the m - IB7 lines the DB~ - DB7 lines carry data between U5 and the internai data bus CS enables U5 and ~2 is a timing signal provided by U6

234 lVIICROPROCESSOR U6

The 8-bit microprocessor contains registers accumulators a 128 X 8 bit RAM and an internai clock The 16-line address bus (A~-A15) supervises the DBA-488 operations The 8-line bidirectional data bus (D~-D7) transfers data to and from memory and the peripheral devices Clock pulses at pin E (~2) are used for timing Upon receipt of an interrupt request (IRQ) from controller U5 (upon U5s receipt of DC L on the data lines) U6 completes its current instruction then cycles through an interrupt sequence that resets the microprocessor The read write (RW) output of U6 controls the read write status of controller U5 and PIAs U10 and Ull

235 ROM U9

Erasable prograrnmable ROM U9 stores the DBA-488 program in its 512 X 8 bit memory When enabled (CS input low) and strobed by a clock pulse from U6 (STR input) address bits A~-A8 are decoded and data transfer is effected on the DO~ - D07 lines

236 PIAS U10 AND Ull

PIAs U10 and Ull interface the DBA-488 with the DDC instrument Four 8-bit bidirectional data buses (PA~ - PA7 and PB~ - PB7) cornmunicate with the instrushyment an 8-bit bidirectional bus (D~ - D7) links the selected PIAs with the internai data bus Each chip is selected by ~ low via a U6 address routed through tri shystate buffer U8 Register select inputs (RS~ RS1) controlled by microprocessor U6 accress registers within each PIA which provide functions such as data direction control peripheral interface etc PIA readwrite operation is conshytrolled by the RIW input from U6

2-3

-------------------------------- I ISTR Ul-AENT 11rr E R r CE

P(gtG PM PAZ PA4 P80 PB+ PBz PB-p PAG PM PAz PAq PBlt PE ~-~PAl PA-5 PA~ PAI RESET PB7 PR - PS3 P81 PA PAS PA3 PAI PB Res PB Ps1

Po J I ~4+- ~a -0+ JJf- 1lt-+-14 ~1ls~ IIL 7 __ Z0 T2i l gt l ll ~J 2i1 ~ll~3 - - - ST l (T 3 T -41_3l-z let It f012Jtz2tz~t~d Z5

i2-1 I i I I (1 4 si 1111(1151 I~I iii lo

Po PO P O il 81 11 I si 4131 2 Ii I 11 151 141 b L) 8 1 1 2 141 121

Po UIO Ull Ull-j Ula

p AZ-BPIAI- 8 p IA2-APIAI-A $5i3ltgt(fJ $IB~~$ Coigt~~$6()CP

tgtrp D1 D21gt3 1gtlt 1gt5 D Di RfS RS0 RSI Cel R-w E c-S4gt cs 1 1gt1l1gt 1 DZ lgt3 D4- D5 [)( D7 RES es412S1C-SZ RW E CS(J CSI

3101 SSI 13III Il5l~ 2iI25~i13313lI3113121 251~712(13+1 J 3~ 135 r~ II SV ~~131 bl 281271211 3 +1 l u-fl 1 1elI

122 ~ -- t5V

~ t5V t5V bull Icamp tgtV I I bull 1 -O+shybull II 1 -- -----------+ ---- -------11--11-1---+------~c~ ~~ Al ~ ~IZ~~R3 AiIi

11 b14 aJ------t-U-~3DltPlO AfJ 32 DITIRI ze - cgtsltP ~~--t-- -~ J2 v 31 D2 U0

IlP e De1 30 D~ fp2 Eo I 2) DB2 ~ 2) 111-1----=--+-lt7 -~

(p SRQ 23 Jo [)8 3lt1 ~ Tl~ II i

Al

D-t~OSRQ lel ~1 -e DSIl REN 4 U I ID REN l2 ii DB4

bull 1 Ie Q __-=-2i--1 Dlt 1-i-1----+-lt7 -~ J IFC 1 ~J~ 14 IFe 21 11 DBS

bull I e-- l) us 1o-__2--i D7 13 D8ltu

I I I t~ ~~---t-ltJ -~ r-~======~~-~~~ ~_1 1= ~I L-_-4~--+------~4~O ReSI I I IN 1 8 3 -z AringT N = 2(P 6PI~bull I ( 37 E6 INDfgtC I l ( DAC Il 37 iCSO Al) I=-~---t-u -~ bull 1 bull ( lt136rp4J --____ 3=-4-1 RwiNRFOIO UL 0 RFD IS 3e iC51 Al I _ bull 1 (

--_--=30=-1 EXIll 14(1~lq _ i4- D- 1i1 3~ ilt 2- M 1 1 D7 1 0-- o-H bull I ( ~ M5B I - shy

I 3 c~ 1 I I-_---=3-11 XTALtO rPZGPIB I I III +gt

10

Rw

----J rGJll II 3~

1 D101 I~4 s

- D1o21 7 ---t-----~~t=t=~----~-~SV RE L I I 2 -HA-L-T3IDlogt 110 I U3 ASE

bull I I( )_ e 34 iP2 t5V --- 5 HR

4D1 04-I 15 1133 -- C4 1i111LI 4 IRQ I I I 1 +5 lgt 22 D() Vec ~ UlUe

Ibl C5 Pllltllto SoV

j3 1[)OW 2 IB4- -=- 32 Ph e I I I U~

L- el -- -NO

IB~ 3i U12shyIJ4 DlOl ~l 1ltgt T1gt I ~ F cp rP cp -=- (8V S~_ PIN 14- +sv~5D1071~2 U4 ) ID 1Bamp 3D DtvAGIA1oI1 --L ADAI Aringl A3 A~ Ar AIoA~ As 20 I - 35 ~NDPIN

~ D106 1 ~i iS 14- 1 B Z l eC i V C)C4 C3C2C Je ~3 AI5 t51

~ 2~

W I 11 e

1 2 I

zil u= 140 IRQ R- zo 1=-------- - ~TV

~ pto J 1 TI

4 tS~~

4 2

~gnlf[3EFI 13 c shy

121 Figure 2-2 1)BA-488 Data Bus (1] Ll- )4 Plt6 4 3 ~ 11-(NV Adapter ScWelnatic Diagram

2-4 1

237 POWER UP AND DEVICE ADDRESS

When power is applied to the DBA-488 the logic low level at test point TP2 (resulting from the uncharged state of C2) initializes U5 U10 UH and U6 The ASE (address select) output of U5 drops enabling the outputs of address switch S1 The five preset LSBs of Sl representing the primary device address are then transferred into a register in controller U5 for subsequent use

238 DATA TRANSFER

Controller U5 responds to the device address (applied via the data line inputs on the lE lines) when the IEEE bus sets ATN true Notified by U5 via the DB data lines U6 addresses ROM U9 which determines if talk or listen operation is reshyquired If the talk mode is selected U6 enables PIAs U10 and Ull and causes data from the instrument to be transferred through the PIAs to controller U5 which transfers the data through the IB lines to U3 and U4 These buffers enabled by a TR2 level from U5 transfer the required data to the IEEE bus Transmisshysion of the individual data bytes is accomplished in proper sequence as a function of the handshake procedure The bus management lines (ATN IFC SRQ EOI and REN) insure that information flows through the interface lines in orderly fashion When the last data bytes (ASCII carriage returnline feed) are transmitted the DBA-488 sets EOI true to signal the end of the data transfer This feature permits compatible operation of the DBA-488 with the HPIB system The entire sequence is terminated by an Untalk command from the controller

When the DBA-488 listen address is received data applied to U3 and U4 is transshyferred to controller U5 The microprocessor then transfers the data from U5 to the PIA s which pass the information to the instrument An EOI or carriage return line feed is received to indicate the end of the data transfer and the listen sequence is terminated by an Unlisten command

-

2-5

SECTION 3

DATA BUS ADAPTER DBA-488-SR400

31 EQUIPMENT SUPPLlED

311 DBA-488 ORDERED WITH SR-400

When the DBA-488 is ordered together with an SR-400 SynchroResolver Simulator the DBA-488 is bracket mounted at the rear of the SR-400 and both units are elecshytrically intercOIlllected through a cable (See figure 3-1) AC power is applied to the DBA-488 when the SR-400 is turned on The only component not supplied is the standard mating connector to the IEEE bus

31 2 DBA-488 ORDERED SEPARATE LY

When a DBA-488 is ordered separately (for retrofit to an SR-400) a mating conshynector for the instrument interface is supplied but is not wired The standard mating connector for the IEEE bus is not supplied Mounting hardware is included as required

The DBA-488 is not equipped with a power switch Line voltage (115 volts at 60 Hz) is applied via the instrument interface connector If the SR-400 front panel POWER switch is to controi the DBA-488 this switch must be wired to pins on the instrument This requires a modification to the SR-400 as shown in table 3-1

NOTE

The DBA-488 may be ordered for operation from 220 volts 5060 Hz

32 UNPACKING

Carefully remove the equipment from the packaging material and inspect for possible damage Should any unit show signs of damage notify the nearest ILC Data Device Corporation field representative immediately

33 INTERCONNECTIONS

Table 3-1 shows the interconnections between the DBA-488 and SR-400 and indicates the function of each lead For SR-400 units being retrofitted switched AC line voltage (115 volts) may be wired to pins 39 and 40 of instrument connector J2 Conshynect pin 39 of J2 to the switched terminal of POWER switch S8 and pin 40 to pin L of instrument connector J1 The interconnecting cable must be wired as shown in table 3-1

3-1

-

JS )foOHZ

J(

SR - 400

cJl pz

INSTRUt1EAJT ~I---------JYMCHRO OR REllI~ roNAlECro~ RESOLVER OUTPUT

I---------REF INPUT INTeuroRCONAlECTlN(J CA13LE ___

DBA-488 NS TRUI-feNT INrEliRIICE CONNECTOR

PI

DJ3A- 4BB

STANOARD HATNy COAlNeCTOR IEEEshyBUS

Figure 3-1_ DBA-488-SR400 Connection Diagram

3-2

DATA OIOI- DI08

II I

DEVICE A

(TIUlt DAILY ) I ~ I ~ i- shy

II I

DEVCE B f----

(liSTEN ONLY) I

l II ~

I

DEICE C ( TALK liND r

LI5TEAI) I t-- shy

I II

DElleE D (TAL Ilt L5TEAJ I lAVD COIVTROL HIAlDSHAKE L-shy LINE S

III 1 NDACL~ N~FD

DAV-I

C EOI 5RGl 1lUJ- rnbull lfT1JJ

MA AJA6 EMENT (COAJTIiOL) L INeuro S

Figure 1-2 Interface Connections and Bus Structure

1-3

-

143 INTERFACE BUS SIGNAIB

NOTE

The IEEE Standard 488-1975 is defined for a negative logic format

Logic O Logic l

= =

False True

= =

High Low

(~2 OV) eO 8V)

a EOI (End or Identify) True levelon this bus management (control) line indicates end of multiple byte transfer When used with ATN performs parallel polling sequence

b SRQ (Service Request) Device sets this control line true when it requires service from the interface controller

c REN (Remote Enable) This controller driven line is used with other messhysages to select source of device programrning data (e g front panel or interface control)

d IFC (lnterface Clear) This controller driven Une is set true to place all ws-connected devices in their idle states

e ATN (Attentian) This control line specifies how data on the data lines are to be interpreted and which devices must respond to the data When ATN is true the DIOl-DI08 lines carry addresses or commands When ATN is set false the data lines carry data

f NDAC (Not Data Accepted) When set false by a device indicates that data has been accepted

this handshake line

g NRFD (Not Ready for Data) When set false by a device this handshake line indicates that the device is ready to accept data

h DAV (Data Valid) When set true this handshake line indicates that informashytion on the data lines is available and valid

i DIOl-m08 (Data Input-Output) These lines carry data in bit-parallel byteshyserial form Information on the lines represents either addresscommands or data depending on the logic state of the ATN line

j Unlisten Command This command is transrnitted on the data lines in conjunction with ATN true to terrninate the device listen function

k Untalk Command This command is transrnitted on the data lines in conjunction with ATN true to terrninate the device talk function

144 REMOTE MESSAGE CODING

Table l-l shows the coding of same of the control messages transmitted on the IEEE bus The l and O designatians refer to the logic states (negative logic convention) X = dont care Al-A5 specify the five address bits set within the device by the address select switches

1-4

) ] ] )) ) ] ] J J l J ) J J J J

~ I

CJ1

TABLE 1-1 MESSAGE CODING

IO Data Handshake Controi Message DI08 DI07 DI06 DI05 DI04 DI03 m02 mOl DAV NRFD NDAC ATN EOI SRQ IFC REN

ATN (Attention) x X X X X X X X X X X 1 X X X X

Data Byte D8 D7 D6 D5 D4 D3 D2 Dl X X X X X X X X

DAV (Data Available) X X X X X X X X 1 X X X X X X X

NRFD (Not Ready for Data) X X X X X X X X X 1 X X X X X X

NDAC (Not Data Accepted) X X X X X X X X X X 1 X X X X X

DCL (Device Clear) X ~ ~ 1 ~ 1 ~ ~ X X X X X X X X

End X X X X X X X X X X X X 1 X X X

Go to Local X O O O O O O 1 X X X X X X X X

Identify X X X X X X X X X X X X 1 X X X

IFC (Interface Clear) X X X X X X X X X X X X X X 1 X

MLA (My Listen Address) X ~ 1 A5 A4 A3 A2 Al X X X X X X X X

MTA (My Talk Address) X 1 ~ A5 A4 A3 A2 Al X X X X X X X X

REN (Remote Enable) X X X X X X X X X X X X X X X 1

SRQ (Service Required) X X X X X X X X X X X X X 1 X X

Unlisten X ~ 1 1 1 1 1 1 X X X X X X X X

Untalk X 1 ~ 1 1 1 1 1 X X X X X X X X

145 3-WIRE HANDSHAKE PROCEDURE

The 3-wire handshake procedure repeated for each byte transferred from a source to ot1e or more acceptors ensures that each listener is ready to accept data that the information on the data lines is valid and that the data has been accepted by all listeners The DAV line is controlled by the source (talker) the NDAC and NRFD lines are controlled by the acceptors (listeners)

FiglLre 1-3 illustrates the handshake cyc le for a source and several acceptors

a Both source and acceptors start in a known state The source initializes DA V to high (false data not valid) and the acceptors initialize NRFD to low (true none are ready for data) and NDAC to low (true none have accepted the data)

b The source checks that both NRFD and NDAC are not high then places the first data byte on the DIO lines (If both lines are sensed high the error condition ends the procedure)

c When all acceptors are ready to accept the first data byte NRFD goes high -d After data is settled and valid and the source has sensed NRFD high it sets DAV low (data is valid)

e The first acceptor sets NRFD low then accepts the f~rst byte receptors follow suit at their own rates

The other

f Each acceptor sets NDAC high to indicate that it has accepted

g When NDAC is sensed high by the source (after all acceptors have accepted the data byte) it sets DA V high (data on DIO lines no longer valid) At this point one data byte transfer has been completed

h Upon sensing DAV high the acceptors set NDAC low

i Source and acceptor initial conditions are now reestablished and the next handshake cycle may be initiated

1-6

ACCEPTOR OPERATiONSOURCE OPERATiON

READYNO TO ACCEPT DA TA

NO NRFD

DATA iS VALiD AND MAY NOW BE ACCEPTED

NO

YES --

Figure 1-3 Handshake Timing Sequence

1-7

-

-

-

SECTION 2

FUNCTIONAL DESCRIPTION OF DBA-488

INTRODUCTION21

This section provides a general functional description of the DBA-488 identifying the major input-output signals and covering basic signal flow Detailed step-byshystep operations within the DBA-488 are a function of the particular instrument and the stored program

22 BLOCK DIAGRAM DESCRIPTION (See figure 2-1)

Operation of the DBA-488 is supervised by a self-contained microprocessor in accordance with a program stored in an erasable programmable ROM Data transshyfer to and from the 16-line IEEE bus is mediated by the controller The 32 inputshyoutput lines at the instrument interface are independently programmed under microprocessor control for input or output data transfer according to the requireshyments of the particular instrument connected to the DBA-488 The device address preset manually by the user via the address select switches is transferred to the controller memory at power turn-on

23 FUNCTIONAL DESCRIPTION (See figure 2-2)

231 EQUIPMENT COMPLEMENT

The DBA-488 consists of four bus transceivers U1-U4 interface controller U5 microprocessor U6 tri-state buffers U7 and U8 ROM U9 and peripheral intershyface adapters (PIAs) U10 and Ull In addition a low voltage power supply consisting of power transformer T1 bridge rectifier CRA1 and voltage regulator VR1 provides 5 volts DC for operating the unit

232 TRANSCEIVERS U1 AND U2

Transceivers U1-U4 serve as the interface between the IEEE bus and the DBA-488 internal logic Transceivers U1 and U2 are used for bus management and handshake signals U3 and U4 accommodate the eight data lines Logic levels applied to the four transmit-receive inputs of each quad transceiver from controller U5 determine which section behaves as a bus driver or receiver for the associated bus line The T fR control for SRQ is always ired high (transmit) while those for REN 1FC and ATN are wired low (receive) The remaining signals are controlled by U5 The bus transceiver outputs meet all requirements of IEEE Std 488-1975

2-1

881T5512 Byr~ IO

ROM NTERshyB BITSFACE

tJ I BBIT

tJ ( DATA

INSTRUMENT IEEE INTERFACE488 32 10 UNS

BUS 8DITA LlNES 8 BIT5 PLUS

l DATA L JE S 8 CONT~

LINES 8 B I T 8 BITSL-----

mAlTROL IlDDRESStlleRO shySELECTPROCESSOR

SLJITCHES

Figure 2-1 DBA-488 Block Diagram bull

1 l ] ] I l J _J l l

-

-

-

233 INTERFACE CONTROLLER U5

Under the direction of microprocessor U6 interface controller U5 mediates the transfer of data between the DBA-488 and the IEEE bus Controller U5 decodes messages from the IEEE bus processes those directed to the DBA-488 and transshyfers messages to the internai data bus It should be noted that although the IEEE bus signals follow negative logic convention positive logic is used within the DBAshy488 (Thus the signal NRFD from the IEEE bus is designated RFD at the input of U5) The controller is equipped with internai registers that are selected by register select lines RSO RS1 and RS2 and chip select CS (via microprocessor address bits AO Al and A2 and Al4) in conjunction with the readwrite (RW) signals and ~2 clock from the microprocessor The registers accornmodate functions such as aringddress data in data out interrupt status etc Data transfer between U5 and U3 U4 is effected through the m - IB7 lines the DB~ - DB7 lines carry data between U5 and the internai data bus CS enables U5 and ~2 is a timing signal provided by U6

234 lVIICROPROCESSOR U6

The 8-bit microprocessor contains registers accumulators a 128 X 8 bit RAM and an internai clock The 16-line address bus (A~-A15) supervises the DBA-488 operations The 8-line bidirectional data bus (D~-D7) transfers data to and from memory and the peripheral devices Clock pulses at pin E (~2) are used for timing Upon receipt of an interrupt request (IRQ) from controller U5 (upon U5s receipt of DC L on the data lines) U6 completes its current instruction then cycles through an interrupt sequence that resets the microprocessor The read write (RW) output of U6 controls the read write status of controller U5 and PIAs U10 and Ull

235 ROM U9

Erasable prograrnmable ROM U9 stores the DBA-488 program in its 512 X 8 bit memory When enabled (CS input low) and strobed by a clock pulse from U6 (STR input) address bits A~-A8 are decoded and data transfer is effected on the DO~ - D07 lines

236 PIAS U10 AND Ull

PIAs U10 and Ull interface the DBA-488 with the DDC instrument Four 8-bit bidirectional data buses (PA~ - PA7 and PB~ - PB7) cornmunicate with the instrushyment an 8-bit bidirectional bus (D~ - D7) links the selected PIAs with the internai data bus Each chip is selected by ~ low via a U6 address routed through tri shystate buffer U8 Register select inputs (RS~ RS1) controlled by microprocessor U6 accress registers within each PIA which provide functions such as data direction control peripheral interface etc PIA readwrite operation is conshytrolled by the RIW input from U6

2-3

-------------------------------- I ISTR Ul-AENT 11rr E R r CE

P(gtG PM PAZ PA4 P80 PB+ PBz PB-p PAG PM PAz PAq PBlt PE ~-~PAl PA-5 PA~ PAI RESET PB7 PR - PS3 P81 PA PAS PA3 PAI PB Res PB Ps1

Po J I ~4+- ~a -0+ JJf- 1lt-+-14 ~1ls~ IIL 7 __ Z0 T2i l gt l ll ~J 2i1 ~ll~3 - - - ST l (T 3 T -41_3l-z let It f012Jtz2tz~t~d Z5

i2-1 I i I I (1 4 si 1111(1151 I~I iii lo

Po PO P O il 81 11 I si 4131 2 Ii I 11 151 141 b L) 8 1 1 2 141 121

Po UIO Ull Ull-j Ula

p AZ-BPIAI- 8 p IA2-APIAI-A $5i3ltgt(fJ $IB~~$ Coigt~~$6()CP

tgtrp D1 D21gt3 1gtlt 1gt5 D Di RfS RS0 RSI Cel R-w E c-S4gt cs 1 1gt1l1gt 1 DZ lgt3 D4- D5 [)( D7 RES es412S1C-SZ RW E CS(J CSI

3101 SSI 13III Il5l~ 2iI25~i13313lI3113121 251~712(13+1 J 3~ 135 r~ II SV ~~131 bl 281271211 3 +1 l u-fl 1 1elI

122 ~ -- t5V

~ t5V t5V bull Icamp tgtV I I bull 1 -O+shybull II 1 -- -----------+ ---- -------11--11-1---+------~c~ ~~ Al ~ ~IZ~~R3 AiIi

11 b14 aJ------t-U-~3DltPlO AfJ 32 DITIRI ze - cgtsltP ~~--t-- -~ J2 v 31 D2 U0

IlP e De1 30 D~ fp2 Eo I 2) DB2 ~ 2) 111-1----=--+-lt7 -~

(p SRQ 23 Jo [)8 3lt1 ~ Tl~ II i

Al

D-t~OSRQ lel ~1 -e DSIl REN 4 U I ID REN l2 ii DB4

bull 1 Ie Q __-=-2i--1 Dlt 1-i-1----+-lt7 -~ J IFC 1 ~J~ 14 IFe 21 11 DBS

bull I e-- l) us 1o-__2--i D7 13 D8ltu

I I I t~ ~~---t-ltJ -~ r-~======~~-~~~ ~_1 1= ~I L-_-4~--+------~4~O ReSI I I IN 1 8 3 -z AringT N = 2(P 6PI~bull I ( 37 E6 INDfgtC I l ( DAC Il 37 iCSO Al) I=-~---t-u -~ bull 1 bull ( lt136rp4J --____ 3=-4-1 RwiNRFOIO UL 0 RFD IS 3e iC51 Al I _ bull 1 (

--_--=30=-1 EXIll 14(1~lq _ i4- D- 1i1 3~ ilt 2- M 1 1 D7 1 0-- o-H bull I ( ~ M5B I - shy

I 3 c~ 1 I I-_---=3-11 XTALtO rPZGPIB I I III +gt

10

Rw

----J rGJll II 3~

1 D101 I~4 s

- D1o21 7 ---t-----~~t=t=~----~-~SV RE L I I 2 -HA-L-T3IDlogt 110 I U3 ASE

bull I I( )_ e 34 iP2 t5V --- 5 HR

4D1 04-I 15 1133 -- C4 1i111LI 4 IRQ I I I 1 +5 lgt 22 D() Vec ~ UlUe

Ibl C5 Pllltllto SoV

j3 1[)OW 2 IB4- -=- 32 Ph e I I I U~

L- el -- -NO

IB~ 3i U12shyIJ4 DlOl ~l 1ltgt T1gt I ~ F cp rP cp -=- (8V S~_ PIN 14- +sv~5D1071~2 U4 ) ID 1Bamp 3D DtvAGIA1oI1 --L ADAI Aringl A3 A~ Ar AIoA~ As 20 I - 35 ~NDPIN

~ D106 1 ~i iS 14- 1 B Z l eC i V C)C4 C3C2C Je ~3 AI5 t51

~ 2~

W I 11 e

1 2 I

zil u= 140 IRQ R- zo 1=-------- - ~TV

~ pto J 1 TI

4 tS~~

4 2

~gnlf[3EFI 13 c shy

121 Figure 2-2 1)BA-488 Data Bus (1] Ll- )4 Plt6 4 3 ~ 11-(NV Adapter ScWelnatic Diagram

2-4 1

237 POWER UP AND DEVICE ADDRESS

When power is applied to the DBA-488 the logic low level at test point TP2 (resulting from the uncharged state of C2) initializes U5 U10 UH and U6 The ASE (address select) output of U5 drops enabling the outputs of address switch S1 The five preset LSBs of Sl representing the primary device address are then transferred into a register in controller U5 for subsequent use

238 DATA TRANSFER

Controller U5 responds to the device address (applied via the data line inputs on the lE lines) when the IEEE bus sets ATN true Notified by U5 via the DB data lines U6 addresses ROM U9 which determines if talk or listen operation is reshyquired If the talk mode is selected U6 enables PIAs U10 and Ull and causes data from the instrument to be transferred through the PIAs to controller U5 which transfers the data through the IB lines to U3 and U4 These buffers enabled by a TR2 level from U5 transfer the required data to the IEEE bus Transmisshysion of the individual data bytes is accomplished in proper sequence as a function of the handshake procedure The bus management lines (ATN IFC SRQ EOI and REN) insure that information flows through the interface lines in orderly fashion When the last data bytes (ASCII carriage returnline feed) are transmitted the DBA-488 sets EOI true to signal the end of the data transfer This feature permits compatible operation of the DBA-488 with the HPIB system The entire sequence is terminated by an Untalk command from the controller

When the DBA-488 listen address is received data applied to U3 and U4 is transshyferred to controller U5 The microprocessor then transfers the data from U5 to the PIA s which pass the information to the instrument An EOI or carriage return line feed is received to indicate the end of the data transfer and the listen sequence is terminated by an Unlisten command

-

2-5

SECTION 3

DATA BUS ADAPTER DBA-488-SR400

31 EQUIPMENT SUPPLlED

311 DBA-488 ORDERED WITH SR-400

When the DBA-488 is ordered together with an SR-400 SynchroResolver Simulator the DBA-488 is bracket mounted at the rear of the SR-400 and both units are elecshytrically intercOIlllected through a cable (See figure 3-1) AC power is applied to the DBA-488 when the SR-400 is turned on The only component not supplied is the standard mating connector to the IEEE bus

31 2 DBA-488 ORDERED SEPARATE LY

When a DBA-488 is ordered separately (for retrofit to an SR-400) a mating conshynector for the instrument interface is supplied but is not wired The standard mating connector for the IEEE bus is not supplied Mounting hardware is included as required

The DBA-488 is not equipped with a power switch Line voltage (115 volts at 60 Hz) is applied via the instrument interface connector If the SR-400 front panel POWER switch is to controi the DBA-488 this switch must be wired to pins on the instrument This requires a modification to the SR-400 as shown in table 3-1

NOTE

The DBA-488 may be ordered for operation from 220 volts 5060 Hz

32 UNPACKING

Carefully remove the equipment from the packaging material and inspect for possible damage Should any unit show signs of damage notify the nearest ILC Data Device Corporation field representative immediately

33 INTERCONNECTIONS

Table 3-1 shows the interconnections between the DBA-488 and SR-400 and indicates the function of each lead For SR-400 units being retrofitted switched AC line voltage (115 volts) may be wired to pins 39 and 40 of instrument connector J2 Conshynect pin 39 of J2 to the switched terminal of POWER switch S8 and pin 40 to pin L of instrument connector J1 The interconnecting cable must be wired as shown in table 3-1

3-1

-

JS )foOHZ

J(

SR - 400

cJl pz

INSTRUt1EAJT ~I---------JYMCHRO OR REllI~ roNAlECro~ RESOLVER OUTPUT

I---------REF INPUT INTeuroRCONAlECTlN(J CA13LE ___

DBA-488 NS TRUI-feNT INrEliRIICE CONNECTOR

PI

DJ3A- 4BB

STANOARD HATNy COAlNeCTOR IEEEshyBUS

Figure 3-1_ DBA-488-SR400 Connection Diagram

3-2

-

143 INTERFACE BUS SIGNAIB

NOTE

The IEEE Standard 488-1975 is defined for a negative logic format

Logic O Logic l

= =

False True

= =

High Low

(~2 OV) eO 8V)

a EOI (End or Identify) True levelon this bus management (control) line indicates end of multiple byte transfer When used with ATN performs parallel polling sequence

b SRQ (Service Request) Device sets this control line true when it requires service from the interface controller

c REN (Remote Enable) This controller driven line is used with other messhysages to select source of device programrning data (e g front panel or interface control)

d IFC (lnterface Clear) This controller driven Une is set true to place all ws-connected devices in their idle states

e ATN (Attentian) This control line specifies how data on the data lines are to be interpreted and which devices must respond to the data When ATN is true the DIOl-DI08 lines carry addresses or commands When ATN is set false the data lines carry data

f NDAC (Not Data Accepted) When set false by a device indicates that data has been accepted

this handshake line

g NRFD (Not Ready for Data) When set false by a device this handshake line indicates that the device is ready to accept data

h DAV (Data Valid) When set true this handshake line indicates that informashytion on the data lines is available and valid

i DIOl-m08 (Data Input-Output) These lines carry data in bit-parallel byteshyserial form Information on the lines represents either addresscommands or data depending on the logic state of the ATN line

j Unlisten Command This command is transrnitted on the data lines in conjunction with ATN true to terrninate the device listen function

k Untalk Command This command is transrnitted on the data lines in conjunction with ATN true to terrninate the device talk function

144 REMOTE MESSAGE CODING

Table l-l shows the coding of same of the control messages transmitted on the IEEE bus The l and O designatians refer to the logic states (negative logic convention) X = dont care Al-A5 specify the five address bits set within the device by the address select switches

1-4

) ] ] )) ) ] ] J J l J ) J J J J

~ I

CJ1

TABLE 1-1 MESSAGE CODING

IO Data Handshake Controi Message DI08 DI07 DI06 DI05 DI04 DI03 m02 mOl DAV NRFD NDAC ATN EOI SRQ IFC REN

ATN (Attention) x X X X X X X X X X X 1 X X X X

Data Byte D8 D7 D6 D5 D4 D3 D2 Dl X X X X X X X X

DAV (Data Available) X X X X X X X X 1 X X X X X X X

NRFD (Not Ready for Data) X X X X X X X X X 1 X X X X X X

NDAC (Not Data Accepted) X X X X X X X X X X 1 X X X X X

DCL (Device Clear) X ~ ~ 1 ~ 1 ~ ~ X X X X X X X X

End X X X X X X X X X X X X 1 X X X

Go to Local X O O O O O O 1 X X X X X X X X

Identify X X X X X X X X X X X X 1 X X X

IFC (Interface Clear) X X X X X X X X X X X X X X 1 X

MLA (My Listen Address) X ~ 1 A5 A4 A3 A2 Al X X X X X X X X

MTA (My Talk Address) X 1 ~ A5 A4 A3 A2 Al X X X X X X X X

REN (Remote Enable) X X X X X X X X X X X X X X X 1

SRQ (Service Required) X X X X X X X X X X X X X 1 X X

Unlisten X ~ 1 1 1 1 1 1 X X X X X X X X

Untalk X 1 ~ 1 1 1 1 1 X X X X X X X X

145 3-WIRE HANDSHAKE PROCEDURE

The 3-wire handshake procedure repeated for each byte transferred from a source to ot1e or more acceptors ensures that each listener is ready to accept data that the information on the data lines is valid and that the data has been accepted by all listeners The DAV line is controlled by the source (talker) the NDAC and NRFD lines are controlled by the acceptors (listeners)

FiglLre 1-3 illustrates the handshake cyc le for a source and several acceptors

a Both source and acceptors start in a known state The source initializes DA V to high (false data not valid) and the acceptors initialize NRFD to low (true none are ready for data) and NDAC to low (true none have accepted the data)

b The source checks that both NRFD and NDAC are not high then places the first data byte on the DIO lines (If both lines are sensed high the error condition ends the procedure)

c When all acceptors are ready to accept the first data byte NRFD goes high -d After data is settled and valid and the source has sensed NRFD high it sets DAV low (data is valid)

e The first acceptor sets NRFD low then accepts the f~rst byte receptors follow suit at their own rates

The other

f Each acceptor sets NDAC high to indicate that it has accepted

g When NDAC is sensed high by the source (after all acceptors have accepted the data byte) it sets DA V high (data on DIO lines no longer valid) At this point one data byte transfer has been completed

h Upon sensing DAV high the acceptors set NDAC low

i Source and acceptor initial conditions are now reestablished and the next handshake cycle may be initiated

1-6

ACCEPTOR OPERATiONSOURCE OPERATiON

READYNO TO ACCEPT DA TA

NO NRFD

DATA iS VALiD AND MAY NOW BE ACCEPTED

NO

YES --

Figure 1-3 Handshake Timing Sequence

1-7

-

-

-

SECTION 2

FUNCTIONAL DESCRIPTION OF DBA-488

INTRODUCTION21

This section provides a general functional description of the DBA-488 identifying the major input-output signals and covering basic signal flow Detailed step-byshystep operations within the DBA-488 are a function of the particular instrument and the stored program

22 BLOCK DIAGRAM DESCRIPTION (See figure 2-1)

Operation of the DBA-488 is supervised by a self-contained microprocessor in accordance with a program stored in an erasable programmable ROM Data transshyfer to and from the 16-line IEEE bus is mediated by the controller The 32 inputshyoutput lines at the instrument interface are independently programmed under microprocessor control for input or output data transfer according to the requireshyments of the particular instrument connected to the DBA-488 The device address preset manually by the user via the address select switches is transferred to the controller memory at power turn-on

23 FUNCTIONAL DESCRIPTION (See figure 2-2)

231 EQUIPMENT COMPLEMENT

The DBA-488 consists of four bus transceivers U1-U4 interface controller U5 microprocessor U6 tri-state buffers U7 and U8 ROM U9 and peripheral intershyface adapters (PIAs) U10 and Ull In addition a low voltage power supply consisting of power transformer T1 bridge rectifier CRA1 and voltage regulator VR1 provides 5 volts DC for operating the unit

232 TRANSCEIVERS U1 AND U2

Transceivers U1-U4 serve as the interface between the IEEE bus and the DBA-488 internal logic Transceivers U1 and U2 are used for bus management and handshake signals U3 and U4 accommodate the eight data lines Logic levels applied to the four transmit-receive inputs of each quad transceiver from controller U5 determine which section behaves as a bus driver or receiver for the associated bus line The T fR control for SRQ is always ired high (transmit) while those for REN 1FC and ATN are wired low (receive) The remaining signals are controlled by U5 The bus transceiver outputs meet all requirements of IEEE Std 488-1975

2-1

881T5512 Byr~ IO

ROM NTERshyB BITSFACE

tJ I BBIT

tJ ( DATA

INSTRUMENT IEEE INTERFACE488 32 10 UNS

BUS 8DITA LlNES 8 BIT5 PLUS

l DATA L JE S 8 CONT~

LINES 8 B I T 8 BITSL-----

mAlTROL IlDDRESStlleRO shySELECTPROCESSOR

SLJITCHES

Figure 2-1 DBA-488 Block Diagram bull

1 l ] ] I l J _J l l

-

-

-

233 INTERFACE CONTROLLER U5

Under the direction of microprocessor U6 interface controller U5 mediates the transfer of data between the DBA-488 and the IEEE bus Controller U5 decodes messages from the IEEE bus processes those directed to the DBA-488 and transshyfers messages to the internai data bus It should be noted that although the IEEE bus signals follow negative logic convention positive logic is used within the DBAshy488 (Thus the signal NRFD from the IEEE bus is designated RFD at the input of U5) The controller is equipped with internai registers that are selected by register select lines RSO RS1 and RS2 and chip select CS (via microprocessor address bits AO Al and A2 and Al4) in conjunction with the readwrite (RW) signals and ~2 clock from the microprocessor The registers accornmodate functions such as aringddress data in data out interrupt status etc Data transfer between U5 and U3 U4 is effected through the m - IB7 lines the DB~ - DB7 lines carry data between U5 and the internai data bus CS enables U5 and ~2 is a timing signal provided by U6

234 lVIICROPROCESSOR U6

The 8-bit microprocessor contains registers accumulators a 128 X 8 bit RAM and an internai clock The 16-line address bus (A~-A15) supervises the DBA-488 operations The 8-line bidirectional data bus (D~-D7) transfers data to and from memory and the peripheral devices Clock pulses at pin E (~2) are used for timing Upon receipt of an interrupt request (IRQ) from controller U5 (upon U5s receipt of DC L on the data lines) U6 completes its current instruction then cycles through an interrupt sequence that resets the microprocessor The read write (RW) output of U6 controls the read write status of controller U5 and PIAs U10 and Ull

235 ROM U9

Erasable prograrnmable ROM U9 stores the DBA-488 program in its 512 X 8 bit memory When enabled (CS input low) and strobed by a clock pulse from U6 (STR input) address bits A~-A8 are decoded and data transfer is effected on the DO~ - D07 lines

236 PIAS U10 AND Ull

PIAs U10 and Ull interface the DBA-488 with the DDC instrument Four 8-bit bidirectional data buses (PA~ - PA7 and PB~ - PB7) cornmunicate with the instrushyment an 8-bit bidirectional bus (D~ - D7) links the selected PIAs with the internai data bus Each chip is selected by ~ low via a U6 address routed through tri shystate buffer U8 Register select inputs (RS~ RS1) controlled by microprocessor U6 accress registers within each PIA which provide functions such as data direction control peripheral interface etc PIA readwrite operation is conshytrolled by the RIW input from U6

2-3

-------------------------------- I ISTR Ul-AENT 11rr E R r CE

P(gtG PM PAZ PA4 P80 PB+ PBz PB-p PAG PM PAz PAq PBlt PE ~-~PAl PA-5 PA~ PAI RESET PB7 PR - PS3 P81 PA PAS PA3 PAI PB Res PB Ps1

Po J I ~4+- ~a -0+ JJf- 1lt-+-14 ~1ls~ IIL 7 __ Z0 T2i l gt l ll ~J 2i1 ~ll~3 - - - ST l (T 3 T -41_3l-z let It f012Jtz2tz~t~d Z5

i2-1 I i I I (1 4 si 1111(1151 I~I iii lo

Po PO P O il 81 11 I si 4131 2 Ii I 11 151 141 b L) 8 1 1 2 141 121

Po UIO Ull Ull-j Ula

p AZ-BPIAI- 8 p IA2-APIAI-A $5i3ltgt(fJ $IB~~$ Coigt~~$6()CP

tgtrp D1 D21gt3 1gtlt 1gt5 D Di RfS RS0 RSI Cel R-w E c-S4gt cs 1 1gt1l1gt 1 DZ lgt3 D4- D5 [)( D7 RES es412S1C-SZ RW E CS(J CSI

3101 SSI 13III Il5l~ 2iI25~i13313lI3113121 251~712(13+1 J 3~ 135 r~ II SV ~~131 bl 281271211 3 +1 l u-fl 1 1elI

122 ~ -- t5V

~ t5V t5V bull Icamp tgtV I I bull 1 -O+shybull II 1 -- -----------+ ---- -------11--11-1---+------~c~ ~~ Al ~ ~IZ~~R3 AiIi

11 b14 aJ------t-U-~3DltPlO AfJ 32 DITIRI ze - cgtsltP ~~--t-- -~ J2 v 31 D2 U0

IlP e De1 30 D~ fp2 Eo I 2) DB2 ~ 2) 111-1----=--+-lt7 -~

(p SRQ 23 Jo [)8 3lt1 ~ Tl~ II i

Al

D-t~OSRQ lel ~1 -e DSIl REN 4 U I ID REN l2 ii DB4

bull 1 Ie Q __-=-2i--1 Dlt 1-i-1----+-lt7 -~ J IFC 1 ~J~ 14 IFe 21 11 DBS

bull I e-- l) us 1o-__2--i D7 13 D8ltu

I I I t~ ~~---t-ltJ -~ r-~======~~-~~~ ~_1 1= ~I L-_-4~--+------~4~O ReSI I I IN 1 8 3 -z AringT N = 2(P 6PI~bull I ( 37 E6 INDfgtC I l ( DAC Il 37 iCSO Al) I=-~---t-u -~ bull 1 bull ( lt136rp4J --____ 3=-4-1 RwiNRFOIO UL 0 RFD IS 3e iC51 Al I _ bull 1 (

--_--=30=-1 EXIll 14(1~lq _ i4- D- 1i1 3~ ilt 2- M 1 1 D7 1 0-- o-H bull I ( ~ M5B I - shy

I 3 c~ 1 I I-_---=3-11 XTALtO rPZGPIB I I III +gt

10

Rw

----J rGJll II 3~

1 D101 I~4 s

- D1o21 7 ---t-----~~t=t=~----~-~SV RE L I I 2 -HA-L-T3IDlogt 110 I U3 ASE

bull I I( )_ e 34 iP2 t5V --- 5 HR

4D1 04-I 15 1133 -- C4 1i111LI 4 IRQ I I I 1 +5 lgt 22 D() Vec ~ UlUe

Ibl C5 Pllltllto SoV

j3 1[)OW 2 IB4- -=- 32 Ph e I I I U~

L- el -- -NO

IB~ 3i U12shyIJ4 DlOl ~l 1ltgt T1gt I ~ F cp rP cp -=- (8V S~_ PIN 14- +sv~5D1071~2 U4 ) ID 1Bamp 3D DtvAGIA1oI1 --L ADAI Aringl A3 A~ Ar AIoA~ As 20 I - 35 ~NDPIN

~ D106 1 ~i iS 14- 1 B Z l eC i V C)C4 C3C2C Je ~3 AI5 t51

~ 2~

W I 11 e

1 2 I

zil u= 140 IRQ R- zo 1=-------- - ~TV

~ pto J 1 TI

4 tS~~

4 2

~gnlf[3EFI 13 c shy

121 Figure 2-2 1)BA-488 Data Bus (1] Ll- )4 Plt6 4 3 ~ 11-(NV Adapter ScWelnatic Diagram

2-4 1

237 POWER UP AND DEVICE ADDRESS

When power is applied to the DBA-488 the logic low level at test point TP2 (resulting from the uncharged state of C2) initializes U5 U10 UH and U6 The ASE (address select) output of U5 drops enabling the outputs of address switch S1 The five preset LSBs of Sl representing the primary device address are then transferred into a register in controller U5 for subsequent use

238 DATA TRANSFER

Controller U5 responds to the device address (applied via the data line inputs on the lE lines) when the IEEE bus sets ATN true Notified by U5 via the DB data lines U6 addresses ROM U9 which determines if talk or listen operation is reshyquired If the talk mode is selected U6 enables PIAs U10 and Ull and causes data from the instrument to be transferred through the PIAs to controller U5 which transfers the data through the IB lines to U3 and U4 These buffers enabled by a TR2 level from U5 transfer the required data to the IEEE bus Transmisshysion of the individual data bytes is accomplished in proper sequence as a function of the handshake procedure The bus management lines (ATN IFC SRQ EOI and REN) insure that information flows through the interface lines in orderly fashion When the last data bytes (ASCII carriage returnline feed) are transmitted the DBA-488 sets EOI true to signal the end of the data transfer This feature permits compatible operation of the DBA-488 with the HPIB system The entire sequence is terminated by an Untalk command from the controller

When the DBA-488 listen address is received data applied to U3 and U4 is transshyferred to controller U5 The microprocessor then transfers the data from U5 to the PIA s which pass the information to the instrument An EOI or carriage return line feed is received to indicate the end of the data transfer and the listen sequence is terminated by an Unlisten command

-

2-5

SECTION 3

DATA BUS ADAPTER DBA-488-SR400

31 EQUIPMENT SUPPLlED

311 DBA-488 ORDERED WITH SR-400

When the DBA-488 is ordered together with an SR-400 SynchroResolver Simulator the DBA-488 is bracket mounted at the rear of the SR-400 and both units are elecshytrically intercOIlllected through a cable (See figure 3-1) AC power is applied to the DBA-488 when the SR-400 is turned on The only component not supplied is the standard mating connector to the IEEE bus

31 2 DBA-488 ORDERED SEPARATE LY

When a DBA-488 is ordered separately (for retrofit to an SR-400) a mating conshynector for the instrument interface is supplied but is not wired The standard mating connector for the IEEE bus is not supplied Mounting hardware is included as required

The DBA-488 is not equipped with a power switch Line voltage (115 volts at 60 Hz) is applied via the instrument interface connector If the SR-400 front panel POWER switch is to controi the DBA-488 this switch must be wired to pins on the instrument This requires a modification to the SR-400 as shown in table 3-1

NOTE

The DBA-488 may be ordered for operation from 220 volts 5060 Hz

32 UNPACKING

Carefully remove the equipment from the packaging material and inspect for possible damage Should any unit show signs of damage notify the nearest ILC Data Device Corporation field representative immediately

33 INTERCONNECTIONS

Table 3-1 shows the interconnections between the DBA-488 and SR-400 and indicates the function of each lead For SR-400 units being retrofitted switched AC line voltage (115 volts) may be wired to pins 39 and 40 of instrument connector J2 Conshynect pin 39 of J2 to the switched terminal of POWER switch S8 and pin 40 to pin L of instrument connector J1 The interconnecting cable must be wired as shown in table 3-1

3-1

-

JS )foOHZ

J(

SR - 400

cJl pz

INSTRUt1EAJT ~I---------JYMCHRO OR REllI~ roNAlECro~ RESOLVER OUTPUT

I---------REF INPUT INTeuroRCONAlECTlN(J CA13LE ___

DBA-488 NS TRUI-feNT INrEliRIICE CONNECTOR

PI

DJ3A- 4BB

STANOARD HATNy COAlNeCTOR IEEEshyBUS

Figure 3-1_ DBA-488-SR400 Connection Diagram

3-2

) ] ] )) ) ] ] J J l J ) J J J J

~ I

CJ1

TABLE 1-1 MESSAGE CODING

IO Data Handshake Controi Message DI08 DI07 DI06 DI05 DI04 DI03 m02 mOl DAV NRFD NDAC ATN EOI SRQ IFC REN

ATN (Attention) x X X X X X X X X X X 1 X X X X

Data Byte D8 D7 D6 D5 D4 D3 D2 Dl X X X X X X X X

DAV (Data Available) X X X X X X X X 1 X X X X X X X

NRFD (Not Ready for Data) X X X X X X X X X 1 X X X X X X

NDAC (Not Data Accepted) X X X X X X X X X X 1 X X X X X

DCL (Device Clear) X ~ ~ 1 ~ 1 ~ ~ X X X X X X X X

End X X X X X X X X X X X X 1 X X X

Go to Local X O O O O O O 1 X X X X X X X X

Identify X X X X X X X X X X X X 1 X X X

IFC (Interface Clear) X X X X X X X X X X X X X X 1 X

MLA (My Listen Address) X ~ 1 A5 A4 A3 A2 Al X X X X X X X X

MTA (My Talk Address) X 1 ~ A5 A4 A3 A2 Al X X X X X X X X

REN (Remote Enable) X X X X X X X X X X X X X X X 1

SRQ (Service Required) X X X X X X X X X X X X X 1 X X

Unlisten X ~ 1 1 1 1 1 1 X X X X X X X X

Untalk X 1 ~ 1 1 1 1 1 X X X X X X X X

145 3-WIRE HANDSHAKE PROCEDURE

The 3-wire handshake procedure repeated for each byte transferred from a source to ot1e or more acceptors ensures that each listener is ready to accept data that the information on the data lines is valid and that the data has been accepted by all listeners The DAV line is controlled by the source (talker) the NDAC and NRFD lines are controlled by the acceptors (listeners)

FiglLre 1-3 illustrates the handshake cyc le for a source and several acceptors

a Both source and acceptors start in a known state The source initializes DA V to high (false data not valid) and the acceptors initialize NRFD to low (true none are ready for data) and NDAC to low (true none have accepted the data)

b The source checks that both NRFD and NDAC are not high then places the first data byte on the DIO lines (If both lines are sensed high the error condition ends the procedure)

c When all acceptors are ready to accept the first data byte NRFD goes high -d After data is settled and valid and the source has sensed NRFD high it sets DAV low (data is valid)

e The first acceptor sets NRFD low then accepts the f~rst byte receptors follow suit at their own rates

The other

f Each acceptor sets NDAC high to indicate that it has accepted

g When NDAC is sensed high by the source (after all acceptors have accepted the data byte) it sets DA V high (data on DIO lines no longer valid) At this point one data byte transfer has been completed

h Upon sensing DAV high the acceptors set NDAC low

i Source and acceptor initial conditions are now reestablished and the next handshake cycle may be initiated

1-6

ACCEPTOR OPERATiONSOURCE OPERATiON

READYNO TO ACCEPT DA TA

NO NRFD

DATA iS VALiD AND MAY NOW BE ACCEPTED

NO

YES --

Figure 1-3 Handshake Timing Sequence

1-7

-

-

-

SECTION 2

FUNCTIONAL DESCRIPTION OF DBA-488

INTRODUCTION21

This section provides a general functional description of the DBA-488 identifying the major input-output signals and covering basic signal flow Detailed step-byshystep operations within the DBA-488 are a function of the particular instrument and the stored program

22 BLOCK DIAGRAM DESCRIPTION (See figure 2-1)

Operation of the DBA-488 is supervised by a self-contained microprocessor in accordance with a program stored in an erasable programmable ROM Data transshyfer to and from the 16-line IEEE bus is mediated by the controller The 32 inputshyoutput lines at the instrument interface are independently programmed under microprocessor control for input or output data transfer according to the requireshyments of the particular instrument connected to the DBA-488 The device address preset manually by the user via the address select switches is transferred to the controller memory at power turn-on

23 FUNCTIONAL DESCRIPTION (See figure 2-2)

231 EQUIPMENT COMPLEMENT

The DBA-488 consists of four bus transceivers U1-U4 interface controller U5 microprocessor U6 tri-state buffers U7 and U8 ROM U9 and peripheral intershyface adapters (PIAs) U10 and Ull In addition a low voltage power supply consisting of power transformer T1 bridge rectifier CRA1 and voltage regulator VR1 provides 5 volts DC for operating the unit

232 TRANSCEIVERS U1 AND U2

Transceivers U1-U4 serve as the interface between the IEEE bus and the DBA-488 internal logic Transceivers U1 and U2 are used for bus management and handshake signals U3 and U4 accommodate the eight data lines Logic levels applied to the four transmit-receive inputs of each quad transceiver from controller U5 determine which section behaves as a bus driver or receiver for the associated bus line The T fR control for SRQ is always ired high (transmit) while those for REN 1FC and ATN are wired low (receive) The remaining signals are controlled by U5 The bus transceiver outputs meet all requirements of IEEE Std 488-1975

2-1

881T5512 Byr~ IO

ROM NTERshyB BITSFACE

tJ I BBIT

tJ ( DATA

INSTRUMENT IEEE INTERFACE488 32 10 UNS

BUS 8DITA LlNES 8 BIT5 PLUS

l DATA L JE S 8 CONT~

LINES 8 B I T 8 BITSL-----

mAlTROL IlDDRESStlleRO shySELECTPROCESSOR

SLJITCHES

Figure 2-1 DBA-488 Block Diagram bull

1 l ] ] I l J _J l l

-

-

-

233 INTERFACE CONTROLLER U5

Under the direction of microprocessor U6 interface controller U5 mediates the transfer of data between the DBA-488 and the IEEE bus Controller U5 decodes messages from the IEEE bus processes those directed to the DBA-488 and transshyfers messages to the internai data bus It should be noted that although the IEEE bus signals follow negative logic convention positive logic is used within the DBAshy488 (Thus the signal NRFD from the IEEE bus is designated RFD at the input of U5) The controller is equipped with internai registers that are selected by register select lines RSO RS1 and RS2 and chip select CS (via microprocessor address bits AO Al and A2 and Al4) in conjunction with the readwrite (RW) signals and ~2 clock from the microprocessor The registers accornmodate functions such as aringddress data in data out interrupt status etc Data transfer between U5 and U3 U4 is effected through the m - IB7 lines the DB~ - DB7 lines carry data between U5 and the internai data bus CS enables U5 and ~2 is a timing signal provided by U6

234 lVIICROPROCESSOR U6

The 8-bit microprocessor contains registers accumulators a 128 X 8 bit RAM and an internai clock The 16-line address bus (A~-A15) supervises the DBA-488 operations The 8-line bidirectional data bus (D~-D7) transfers data to and from memory and the peripheral devices Clock pulses at pin E (~2) are used for timing Upon receipt of an interrupt request (IRQ) from controller U5 (upon U5s receipt of DC L on the data lines) U6 completes its current instruction then cycles through an interrupt sequence that resets the microprocessor The read write (RW) output of U6 controls the read write status of controller U5 and PIAs U10 and Ull

235 ROM U9

Erasable prograrnmable ROM U9 stores the DBA-488 program in its 512 X 8 bit memory When enabled (CS input low) and strobed by a clock pulse from U6 (STR input) address bits A~-A8 are decoded and data transfer is effected on the DO~ - D07 lines

236 PIAS U10 AND Ull

PIAs U10 and Ull interface the DBA-488 with the DDC instrument Four 8-bit bidirectional data buses (PA~ - PA7 and PB~ - PB7) cornmunicate with the instrushyment an 8-bit bidirectional bus (D~ - D7) links the selected PIAs with the internai data bus Each chip is selected by ~ low via a U6 address routed through tri shystate buffer U8 Register select inputs (RS~ RS1) controlled by microprocessor U6 accress registers within each PIA which provide functions such as data direction control peripheral interface etc PIA readwrite operation is conshytrolled by the RIW input from U6

2-3

-------------------------------- I ISTR Ul-AENT 11rr E R r CE

P(gtG PM PAZ PA4 P80 PB+ PBz PB-p PAG PM PAz PAq PBlt PE ~-~PAl PA-5 PA~ PAI RESET PB7 PR - PS3 P81 PA PAS PA3 PAI PB Res PB Ps1

Po J I ~4+- ~a -0+ JJf- 1lt-+-14 ~1ls~ IIL 7 __ Z0 T2i l gt l ll ~J 2i1 ~ll~3 - - - ST l (T 3 T -41_3l-z let It f012Jtz2tz~t~d Z5

i2-1 I i I I (1 4 si 1111(1151 I~I iii lo

Po PO P O il 81 11 I si 4131 2 Ii I 11 151 141 b L) 8 1 1 2 141 121

Po UIO Ull Ull-j Ula

p AZ-BPIAI- 8 p IA2-APIAI-A $5i3ltgt(fJ $IB~~$ Coigt~~$6()CP

tgtrp D1 D21gt3 1gtlt 1gt5 D Di RfS RS0 RSI Cel R-w E c-S4gt cs 1 1gt1l1gt 1 DZ lgt3 D4- D5 [)( D7 RES es412S1C-SZ RW E CS(J CSI

3101 SSI 13III Il5l~ 2iI25~i13313lI3113121 251~712(13+1 J 3~ 135 r~ II SV ~~131 bl 281271211 3 +1 l u-fl 1 1elI

122 ~ -- t5V

~ t5V t5V bull Icamp tgtV I I bull 1 -O+shybull II 1 -- -----------+ ---- -------11--11-1---+------~c~ ~~ Al ~ ~IZ~~R3 AiIi

11 b14 aJ------t-U-~3DltPlO AfJ 32 DITIRI ze - cgtsltP ~~--t-- -~ J2 v 31 D2 U0

IlP e De1 30 D~ fp2 Eo I 2) DB2 ~ 2) 111-1----=--+-lt7 -~

(p SRQ 23 Jo [)8 3lt1 ~ Tl~ II i

Al

D-t~OSRQ lel ~1 -e DSIl REN 4 U I ID REN l2 ii DB4

bull 1 Ie Q __-=-2i--1 Dlt 1-i-1----+-lt7 -~ J IFC 1 ~J~ 14 IFe 21 11 DBS

bull I e-- l) us 1o-__2--i D7 13 D8ltu

I I I t~ ~~---t-ltJ -~ r-~======~~-~~~ ~_1 1= ~I L-_-4~--+------~4~O ReSI I I IN 1 8 3 -z AringT N = 2(P 6PI~bull I ( 37 E6 INDfgtC I l ( DAC Il 37 iCSO Al) I=-~---t-u -~ bull 1 bull ( lt136rp4J --____ 3=-4-1 RwiNRFOIO UL 0 RFD IS 3e iC51 Al I _ bull 1 (

--_--=30=-1 EXIll 14(1~lq _ i4- D- 1i1 3~ ilt 2- M 1 1 D7 1 0-- o-H bull I ( ~ M5B I - shy

I 3 c~ 1 I I-_---=3-11 XTALtO rPZGPIB I I III +gt

10

Rw

----J rGJll II 3~

1 D101 I~4 s

- D1o21 7 ---t-----~~t=t=~----~-~SV RE L I I 2 -HA-L-T3IDlogt 110 I U3 ASE

bull I I( )_ e 34 iP2 t5V --- 5 HR

4D1 04-I 15 1133 -- C4 1i111LI 4 IRQ I I I 1 +5 lgt 22 D() Vec ~ UlUe

Ibl C5 Pllltllto SoV

j3 1[)OW 2 IB4- -=- 32 Ph e I I I U~

L- el -- -NO

IB~ 3i U12shyIJ4 DlOl ~l 1ltgt T1gt I ~ F cp rP cp -=- (8V S~_ PIN 14- +sv~5D1071~2 U4 ) ID 1Bamp 3D DtvAGIA1oI1 --L ADAI Aringl A3 A~ Ar AIoA~ As 20 I - 35 ~NDPIN

~ D106 1 ~i iS 14- 1 B Z l eC i V C)C4 C3C2C Je ~3 AI5 t51

~ 2~

W I 11 e

1 2 I

zil u= 140 IRQ R- zo 1=-------- - ~TV

~ pto J 1 TI

4 tS~~

4 2

~gnlf[3EFI 13 c shy

121 Figure 2-2 1)BA-488 Data Bus (1] Ll- )4 Plt6 4 3 ~ 11-(NV Adapter ScWelnatic Diagram

2-4 1

237 POWER UP AND DEVICE ADDRESS

When power is applied to the DBA-488 the logic low level at test point TP2 (resulting from the uncharged state of C2) initializes U5 U10 UH and U6 The ASE (address select) output of U5 drops enabling the outputs of address switch S1 The five preset LSBs of Sl representing the primary device address are then transferred into a register in controller U5 for subsequent use

238 DATA TRANSFER

Controller U5 responds to the device address (applied via the data line inputs on the lE lines) when the IEEE bus sets ATN true Notified by U5 via the DB data lines U6 addresses ROM U9 which determines if talk or listen operation is reshyquired If the talk mode is selected U6 enables PIAs U10 and Ull and causes data from the instrument to be transferred through the PIAs to controller U5 which transfers the data through the IB lines to U3 and U4 These buffers enabled by a TR2 level from U5 transfer the required data to the IEEE bus Transmisshysion of the individual data bytes is accomplished in proper sequence as a function of the handshake procedure The bus management lines (ATN IFC SRQ EOI and REN) insure that information flows through the interface lines in orderly fashion When the last data bytes (ASCII carriage returnline feed) are transmitted the DBA-488 sets EOI true to signal the end of the data transfer This feature permits compatible operation of the DBA-488 with the HPIB system The entire sequence is terminated by an Untalk command from the controller

When the DBA-488 listen address is received data applied to U3 and U4 is transshyferred to controller U5 The microprocessor then transfers the data from U5 to the PIA s which pass the information to the instrument An EOI or carriage return line feed is received to indicate the end of the data transfer and the listen sequence is terminated by an Unlisten command

-

2-5

SECTION 3

DATA BUS ADAPTER DBA-488-SR400

31 EQUIPMENT SUPPLlED

311 DBA-488 ORDERED WITH SR-400

When the DBA-488 is ordered together with an SR-400 SynchroResolver Simulator the DBA-488 is bracket mounted at the rear of the SR-400 and both units are elecshytrically intercOIlllected through a cable (See figure 3-1) AC power is applied to the DBA-488 when the SR-400 is turned on The only component not supplied is the standard mating connector to the IEEE bus

31 2 DBA-488 ORDERED SEPARATE LY

When a DBA-488 is ordered separately (for retrofit to an SR-400) a mating conshynector for the instrument interface is supplied but is not wired The standard mating connector for the IEEE bus is not supplied Mounting hardware is included as required

The DBA-488 is not equipped with a power switch Line voltage (115 volts at 60 Hz) is applied via the instrument interface connector If the SR-400 front panel POWER switch is to controi the DBA-488 this switch must be wired to pins on the instrument This requires a modification to the SR-400 as shown in table 3-1

NOTE

The DBA-488 may be ordered for operation from 220 volts 5060 Hz

32 UNPACKING

Carefully remove the equipment from the packaging material and inspect for possible damage Should any unit show signs of damage notify the nearest ILC Data Device Corporation field representative immediately

33 INTERCONNECTIONS

Table 3-1 shows the interconnections between the DBA-488 and SR-400 and indicates the function of each lead For SR-400 units being retrofitted switched AC line voltage (115 volts) may be wired to pins 39 and 40 of instrument connector J2 Conshynect pin 39 of J2 to the switched terminal of POWER switch S8 and pin 40 to pin L of instrument connector J1 The interconnecting cable must be wired as shown in table 3-1

3-1

-

JS )foOHZ

J(

SR - 400

cJl pz

INSTRUt1EAJT ~I---------JYMCHRO OR REllI~ roNAlECro~ RESOLVER OUTPUT

I---------REF INPUT INTeuroRCONAlECTlN(J CA13LE ___

DBA-488 NS TRUI-feNT INrEliRIICE CONNECTOR

PI

DJ3A- 4BB

STANOARD HATNy COAlNeCTOR IEEEshyBUS

Figure 3-1_ DBA-488-SR400 Connection Diagram

3-2

145 3-WIRE HANDSHAKE PROCEDURE

The 3-wire handshake procedure repeated for each byte transferred from a source to ot1e or more acceptors ensures that each listener is ready to accept data that the information on the data lines is valid and that the data has been accepted by all listeners The DAV line is controlled by the source (talker) the NDAC and NRFD lines are controlled by the acceptors (listeners)

FiglLre 1-3 illustrates the handshake cyc le for a source and several acceptors

a Both source and acceptors start in a known state The source initializes DA V to high (false data not valid) and the acceptors initialize NRFD to low (true none are ready for data) and NDAC to low (true none have accepted the data)

b The source checks that both NRFD and NDAC are not high then places the first data byte on the DIO lines (If both lines are sensed high the error condition ends the procedure)

c When all acceptors are ready to accept the first data byte NRFD goes high -d After data is settled and valid and the source has sensed NRFD high it sets DAV low (data is valid)

e The first acceptor sets NRFD low then accepts the f~rst byte receptors follow suit at their own rates

The other

f Each acceptor sets NDAC high to indicate that it has accepted

g When NDAC is sensed high by the source (after all acceptors have accepted the data byte) it sets DA V high (data on DIO lines no longer valid) At this point one data byte transfer has been completed

h Upon sensing DAV high the acceptors set NDAC low

i Source and acceptor initial conditions are now reestablished and the next handshake cycle may be initiated

1-6

ACCEPTOR OPERATiONSOURCE OPERATiON

READYNO TO ACCEPT DA TA

NO NRFD

DATA iS VALiD AND MAY NOW BE ACCEPTED

NO

YES --

Figure 1-3 Handshake Timing Sequence

1-7

-

-

-

SECTION 2

FUNCTIONAL DESCRIPTION OF DBA-488

INTRODUCTION21

This section provides a general functional description of the DBA-488 identifying the major input-output signals and covering basic signal flow Detailed step-byshystep operations within the DBA-488 are a function of the particular instrument and the stored program

22 BLOCK DIAGRAM DESCRIPTION (See figure 2-1)

Operation of the DBA-488 is supervised by a self-contained microprocessor in accordance with a program stored in an erasable programmable ROM Data transshyfer to and from the 16-line IEEE bus is mediated by the controller The 32 inputshyoutput lines at the instrument interface are independently programmed under microprocessor control for input or output data transfer according to the requireshyments of the particular instrument connected to the DBA-488 The device address preset manually by the user via the address select switches is transferred to the controller memory at power turn-on

23 FUNCTIONAL DESCRIPTION (See figure 2-2)

231 EQUIPMENT COMPLEMENT

The DBA-488 consists of four bus transceivers U1-U4 interface controller U5 microprocessor U6 tri-state buffers U7 and U8 ROM U9 and peripheral intershyface adapters (PIAs) U10 and Ull In addition a low voltage power supply consisting of power transformer T1 bridge rectifier CRA1 and voltage regulator VR1 provides 5 volts DC for operating the unit

232 TRANSCEIVERS U1 AND U2

Transceivers U1-U4 serve as the interface between the IEEE bus and the DBA-488 internal logic Transceivers U1 and U2 are used for bus management and handshake signals U3 and U4 accommodate the eight data lines Logic levels applied to the four transmit-receive inputs of each quad transceiver from controller U5 determine which section behaves as a bus driver or receiver for the associated bus line The T fR control for SRQ is always ired high (transmit) while those for REN 1FC and ATN are wired low (receive) The remaining signals are controlled by U5 The bus transceiver outputs meet all requirements of IEEE Std 488-1975

2-1

881T5512 Byr~ IO

ROM NTERshyB BITSFACE

tJ I BBIT

tJ ( DATA

INSTRUMENT IEEE INTERFACE488 32 10 UNS

BUS 8DITA LlNES 8 BIT5 PLUS

l DATA L JE S 8 CONT~

LINES 8 B I T 8 BITSL-----

mAlTROL IlDDRESStlleRO shySELECTPROCESSOR

SLJITCHES

Figure 2-1 DBA-488 Block Diagram bull

1 l ] ] I l J _J l l

-

-

-

233 INTERFACE CONTROLLER U5

Under the direction of microprocessor U6 interface controller U5 mediates the transfer of data between the DBA-488 and the IEEE bus Controller U5 decodes messages from the IEEE bus processes those directed to the DBA-488 and transshyfers messages to the internai data bus It should be noted that although the IEEE bus signals follow negative logic convention positive logic is used within the DBAshy488 (Thus the signal NRFD from the IEEE bus is designated RFD at the input of U5) The controller is equipped with internai registers that are selected by register select lines RSO RS1 and RS2 and chip select CS (via microprocessor address bits AO Al and A2 and Al4) in conjunction with the readwrite (RW) signals and ~2 clock from the microprocessor The registers accornmodate functions such as aringddress data in data out interrupt status etc Data transfer between U5 and U3 U4 is effected through the m - IB7 lines the DB~ - DB7 lines carry data between U5 and the internai data bus CS enables U5 and ~2 is a timing signal provided by U6

234 lVIICROPROCESSOR U6

The 8-bit microprocessor contains registers accumulators a 128 X 8 bit RAM and an internai clock The 16-line address bus (A~-A15) supervises the DBA-488 operations The 8-line bidirectional data bus (D~-D7) transfers data to and from memory and the peripheral devices Clock pulses at pin E (~2) are used for timing Upon receipt of an interrupt request (IRQ) from controller U5 (upon U5s receipt of DC L on the data lines) U6 completes its current instruction then cycles through an interrupt sequence that resets the microprocessor The read write (RW) output of U6 controls the read write status of controller U5 and PIAs U10 and Ull

235 ROM U9

Erasable prograrnmable ROM U9 stores the DBA-488 program in its 512 X 8 bit memory When enabled (CS input low) and strobed by a clock pulse from U6 (STR input) address bits A~-A8 are decoded and data transfer is effected on the DO~ - D07 lines

236 PIAS U10 AND Ull

PIAs U10 and Ull interface the DBA-488 with the DDC instrument Four 8-bit bidirectional data buses (PA~ - PA7 and PB~ - PB7) cornmunicate with the instrushyment an 8-bit bidirectional bus (D~ - D7) links the selected PIAs with the internai data bus Each chip is selected by ~ low via a U6 address routed through tri shystate buffer U8 Register select inputs (RS~ RS1) controlled by microprocessor U6 accress registers within each PIA which provide functions such as data direction control peripheral interface etc PIA readwrite operation is conshytrolled by the RIW input from U6

2-3

-------------------------------- I ISTR Ul-AENT 11rr E R r CE

P(gtG PM PAZ PA4 P80 PB+ PBz PB-p PAG PM PAz PAq PBlt PE ~-~PAl PA-5 PA~ PAI RESET PB7 PR - PS3 P81 PA PAS PA3 PAI PB Res PB Ps1

Po J I ~4+- ~a -0+ JJf- 1lt-+-14 ~1ls~ IIL 7 __ Z0 T2i l gt l ll ~J 2i1 ~ll~3 - - - ST l (T 3 T -41_3l-z let It f012Jtz2tz~t~d Z5

i2-1 I i I I (1 4 si 1111(1151 I~I iii lo

Po PO P O il 81 11 I si 4131 2 Ii I 11 151 141 b L) 8 1 1 2 141 121

Po UIO Ull Ull-j Ula

p AZ-BPIAI- 8 p IA2-APIAI-A $5i3ltgt(fJ $IB~~$ Coigt~~$6()CP

tgtrp D1 D21gt3 1gtlt 1gt5 D Di RfS RS0 RSI Cel R-w E c-S4gt cs 1 1gt1l1gt 1 DZ lgt3 D4- D5 [)( D7 RES es412S1C-SZ RW E CS(J CSI

3101 SSI 13III Il5l~ 2iI25~i13313lI3113121 251~712(13+1 J 3~ 135 r~ II SV ~~131 bl 281271211 3 +1 l u-fl 1 1elI

122 ~ -- t5V

~ t5V t5V bull Icamp tgtV I I bull 1 -O+shybull II 1 -- -----------+ ---- -------11--11-1---+------~c~ ~~ Al ~ ~IZ~~R3 AiIi

11 b14 aJ------t-U-~3DltPlO AfJ 32 DITIRI ze - cgtsltP ~~--t-- -~ J2 v 31 D2 U0

IlP e De1 30 D~ fp2 Eo I 2) DB2 ~ 2) 111-1----=--+-lt7 -~

(p SRQ 23 Jo [)8 3lt1 ~ Tl~ II i

Al

D-t~OSRQ lel ~1 -e DSIl REN 4 U I ID REN l2 ii DB4

bull 1 Ie Q __-=-2i--1 Dlt 1-i-1----+-lt7 -~ J IFC 1 ~J~ 14 IFe 21 11 DBS

bull I e-- l) us 1o-__2--i D7 13 D8ltu

I I I t~ ~~---t-ltJ -~ r-~======~~-~~~ ~_1 1= ~I L-_-4~--+------~4~O ReSI I I IN 1 8 3 -z AringT N = 2(P 6PI~bull I ( 37 E6 INDfgtC I l ( DAC Il 37 iCSO Al) I=-~---t-u -~ bull 1 bull ( lt136rp4J --____ 3=-4-1 RwiNRFOIO UL 0 RFD IS 3e iC51 Al I _ bull 1 (

--_--=30=-1 EXIll 14(1~lq _ i4- D- 1i1 3~ ilt 2- M 1 1 D7 1 0-- o-H bull I ( ~ M5B I - shy

I 3 c~ 1 I I-_---=3-11 XTALtO rPZGPIB I I III +gt

10

Rw

----J rGJll II 3~

1 D101 I~4 s

- D1o21 7 ---t-----~~t=t=~----~-~SV RE L I I 2 -HA-L-T3IDlogt 110 I U3 ASE

bull I I( )_ e 34 iP2 t5V --- 5 HR

4D1 04-I 15 1133 -- C4 1i111LI 4 IRQ I I I 1 +5 lgt 22 D() Vec ~ UlUe

Ibl C5 Pllltllto SoV

j3 1[)OW 2 IB4- -=- 32 Ph e I I I U~

L- el -- -NO

IB~ 3i U12shyIJ4 DlOl ~l 1ltgt T1gt I ~ F cp rP cp -=- (8V S~_ PIN 14- +sv~5D1071~2 U4 ) ID 1Bamp 3D DtvAGIA1oI1 --L ADAI Aringl A3 A~ Ar AIoA~ As 20 I - 35 ~NDPIN

~ D106 1 ~i iS 14- 1 B Z l eC i V C)C4 C3C2C Je ~3 AI5 t51

~ 2~

W I 11 e

1 2 I

zil u= 140 IRQ R- zo 1=-------- - ~TV

~ pto J 1 TI

4 tS~~

4 2

~gnlf[3EFI 13 c shy

121 Figure 2-2 1)BA-488 Data Bus (1] Ll- )4 Plt6 4 3 ~ 11-(NV Adapter ScWelnatic Diagram

2-4 1

237 POWER UP AND DEVICE ADDRESS

When power is applied to the DBA-488 the logic low level at test point TP2 (resulting from the uncharged state of C2) initializes U5 U10 UH and U6 The ASE (address select) output of U5 drops enabling the outputs of address switch S1 The five preset LSBs of Sl representing the primary device address are then transferred into a register in controller U5 for subsequent use

238 DATA TRANSFER

Controller U5 responds to the device address (applied via the data line inputs on the lE lines) when the IEEE bus sets ATN true Notified by U5 via the DB data lines U6 addresses ROM U9 which determines if talk or listen operation is reshyquired If the talk mode is selected U6 enables PIAs U10 and Ull and causes data from the instrument to be transferred through the PIAs to controller U5 which transfers the data through the IB lines to U3 and U4 These buffers enabled by a TR2 level from U5 transfer the required data to the IEEE bus Transmisshysion of the individual data bytes is accomplished in proper sequence as a function of the handshake procedure The bus management lines (ATN IFC SRQ EOI and REN) insure that information flows through the interface lines in orderly fashion When the last data bytes (ASCII carriage returnline feed) are transmitted the DBA-488 sets EOI true to signal the end of the data transfer This feature permits compatible operation of the DBA-488 with the HPIB system The entire sequence is terminated by an Untalk command from the controller

When the DBA-488 listen address is received data applied to U3 and U4 is transshyferred to controller U5 The microprocessor then transfers the data from U5 to the PIA s which pass the information to the instrument An EOI or carriage return line feed is received to indicate the end of the data transfer and the listen sequence is terminated by an Unlisten command

-

2-5

SECTION 3

DATA BUS ADAPTER DBA-488-SR400

31 EQUIPMENT SUPPLlED

311 DBA-488 ORDERED WITH SR-400

When the DBA-488 is ordered together with an SR-400 SynchroResolver Simulator the DBA-488 is bracket mounted at the rear of the SR-400 and both units are elecshytrically intercOIlllected through a cable (See figure 3-1) AC power is applied to the DBA-488 when the SR-400 is turned on The only component not supplied is the standard mating connector to the IEEE bus

31 2 DBA-488 ORDERED SEPARATE LY

When a DBA-488 is ordered separately (for retrofit to an SR-400) a mating conshynector for the instrument interface is supplied but is not wired The standard mating connector for the IEEE bus is not supplied Mounting hardware is included as required

The DBA-488 is not equipped with a power switch Line voltage (115 volts at 60 Hz) is applied via the instrument interface connector If the SR-400 front panel POWER switch is to controi the DBA-488 this switch must be wired to pins on the instrument This requires a modification to the SR-400 as shown in table 3-1

NOTE

The DBA-488 may be ordered for operation from 220 volts 5060 Hz

32 UNPACKING

Carefully remove the equipment from the packaging material and inspect for possible damage Should any unit show signs of damage notify the nearest ILC Data Device Corporation field representative immediately

33 INTERCONNECTIONS

Table 3-1 shows the interconnections between the DBA-488 and SR-400 and indicates the function of each lead For SR-400 units being retrofitted switched AC line voltage (115 volts) may be wired to pins 39 and 40 of instrument connector J2 Conshynect pin 39 of J2 to the switched terminal of POWER switch S8 and pin 40 to pin L of instrument connector J1 The interconnecting cable must be wired as shown in table 3-1

3-1

-

JS )foOHZ

J(

SR - 400

cJl pz

INSTRUt1EAJT ~I---------JYMCHRO OR REllI~ roNAlECro~ RESOLVER OUTPUT

I---------REF INPUT INTeuroRCONAlECTlN(J CA13LE ___

DBA-488 NS TRUI-feNT INrEliRIICE CONNECTOR

PI

DJ3A- 4BB

STANOARD HATNy COAlNeCTOR IEEEshyBUS

Figure 3-1_ DBA-488-SR400 Connection Diagram

3-2

ACCEPTOR OPERATiONSOURCE OPERATiON

READYNO TO ACCEPT DA TA

NO NRFD

DATA iS VALiD AND MAY NOW BE ACCEPTED

NO

YES --

Figure 1-3 Handshake Timing Sequence

1-7

-

-

-

SECTION 2

FUNCTIONAL DESCRIPTION OF DBA-488

INTRODUCTION21

This section provides a general functional description of the DBA-488 identifying the major input-output signals and covering basic signal flow Detailed step-byshystep operations within the DBA-488 are a function of the particular instrument and the stored program

22 BLOCK DIAGRAM DESCRIPTION (See figure 2-1)

Operation of the DBA-488 is supervised by a self-contained microprocessor in accordance with a program stored in an erasable programmable ROM Data transshyfer to and from the 16-line IEEE bus is mediated by the controller The 32 inputshyoutput lines at the instrument interface are independently programmed under microprocessor control for input or output data transfer according to the requireshyments of the particular instrument connected to the DBA-488 The device address preset manually by the user via the address select switches is transferred to the controller memory at power turn-on

23 FUNCTIONAL DESCRIPTION (See figure 2-2)

231 EQUIPMENT COMPLEMENT

The DBA-488 consists of four bus transceivers U1-U4 interface controller U5 microprocessor U6 tri-state buffers U7 and U8 ROM U9 and peripheral intershyface adapters (PIAs) U10 and Ull In addition a low voltage power supply consisting of power transformer T1 bridge rectifier CRA1 and voltage regulator VR1 provides 5 volts DC for operating the unit

232 TRANSCEIVERS U1 AND U2

Transceivers U1-U4 serve as the interface between the IEEE bus and the DBA-488 internal logic Transceivers U1 and U2 are used for bus management and handshake signals U3 and U4 accommodate the eight data lines Logic levels applied to the four transmit-receive inputs of each quad transceiver from controller U5 determine which section behaves as a bus driver or receiver for the associated bus line The T fR control for SRQ is always ired high (transmit) while those for REN 1FC and ATN are wired low (receive) The remaining signals are controlled by U5 The bus transceiver outputs meet all requirements of IEEE Std 488-1975

2-1

881T5512 Byr~ IO

ROM NTERshyB BITSFACE

tJ I BBIT

tJ ( DATA

INSTRUMENT IEEE INTERFACE488 32 10 UNS

BUS 8DITA LlNES 8 BIT5 PLUS

l DATA L JE S 8 CONT~

LINES 8 B I T 8 BITSL-----

mAlTROL IlDDRESStlleRO shySELECTPROCESSOR

SLJITCHES

Figure 2-1 DBA-488 Block Diagram bull

1 l ] ] I l J _J l l

-

-

-

233 INTERFACE CONTROLLER U5

Under the direction of microprocessor U6 interface controller U5 mediates the transfer of data between the DBA-488 and the IEEE bus Controller U5 decodes messages from the IEEE bus processes those directed to the DBA-488 and transshyfers messages to the internai data bus It should be noted that although the IEEE bus signals follow negative logic convention positive logic is used within the DBAshy488 (Thus the signal NRFD from the IEEE bus is designated RFD at the input of U5) The controller is equipped with internai registers that are selected by register select lines RSO RS1 and RS2 and chip select CS (via microprocessor address bits AO Al and A2 and Al4) in conjunction with the readwrite (RW) signals and ~2 clock from the microprocessor The registers accornmodate functions such as aringddress data in data out interrupt status etc Data transfer between U5 and U3 U4 is effected through the m - IB7 lines the DB~ - DB7 lines carry data between U5 and the internai data bus CS enables U5 and ~2 is a timing signal provided by U6

234 lVIICROPROCESSOR U6

The 8-bit microprocessor contains registers accumulators a 128 X 8 bit RAM and an internai clock The 16-line address bus (A~-A15) supervises the DBA-488 operations The 8-line bidirectional data bus (D~-D7) transfers data to and from memory and the peripheral devices Clock pulses at pin E (~2) are used for timing Upon receipt of an interrupt request (IRQ) from controller U5 (upon U5s receipt of DC L on the data lines) U6 completes its current instruction then cycles through an interrupt sequence that resets the microprocessor The read write (RW) output of U6 controls the read write status of controller U5 and PIAs U10 and Ull

235 ROM U9

Erasable prograrnmable ROM U9 stores the DBA-488 program in its 512 X 8 bit memory When enabled (CS input low) and strobed by a clock pulse from U6 (STR input) address bits A~-A8 are decoded and data transfer is effected on the DO~ - D07 lines

236 PIAS U10 AND Ull

PIAs U10 and Ull interface the DBA-488 with the DDC instrument Four 8-bit bidirectional data buses (PA~ - PA7 and PB~ - PB7) cornmunicate with the instrushyment an 8-bit bidirectional bus (D~ - D7) links the selected PIAs with the internai data bus Each chip is selected by ~ low via a U6 address routed through tri shystate buffer U8 Register select inputs (RS~ RS1) controlled by microprocessor U6 accress registers within each PIA which provide functions such as data direction control peripheral interface etc PIA readwrite operation is conshytrolled by the RIW input from U6

2-3

-------------------------------- I ISTR Ul-AENT 11rr E R r CE

P(gtG PM PAZ PA4 P80 PB+ PBz PB-p PAG PM PAz PAq PBlt PE ~-~PAl PA-5 PA~ PAI RESET PB7 PR - PS3 P81 PA PAS PA3 PAI PB Res PB Ps1

Po J I ~4+- ~a -0+ JJf- 1lt-+-14 ~1ls~ IIL 7 __ Z0 T2i l gt l ll ~J 2i1 ~ll~3 - - - ST l (T 3 T -41_3l-z let It f012Jtz2tz~t~d Z5

i2-1 I i I I (1 4 si 1111(1151 I~I iii lo

Po PO P O il 81 11 I si 4131 2 Ii I 11 151 141 b L) 8 1 1 2 141 121

Po UIO Ull Ull-j Ula

p AZ-BPIAI- 8 p IA2-APIAI-A $5i3ltgt(fJ $IB~~$ Coigt~~$6()CP

tgtrp D1 D21gt3 1gtlt 1gt5 D Di RfS RS0 RSI Cel R-w E c-S4gt cs 1 1gt1l1gt 1 DZ lgt3 D4- D5 [)( D7 RES es412S1C-SZ RW E CS(J CSI

3101 SSI 13III Il5l~ 2iI25~i13313lI3113121 251~712(13+1 J 3~ 135 r~ II SV ~~131 bl 281271211 3 +1 l u-fl 1 1elI

122 ~ -- t5V

~ t5V t5V bull Icamp tgtV I I bull 1 -O+shybull II 1 -- -----------+ ---- -------11--11-1---+------~c~ ~~ Al ~ ~IZ~~R3 AiIi

11 b14 aJ------t-U-~3DltPlO AfJ 32 DITIRI ze - cgtsltP ~~--t-- -~ J2 v 31 D2 U0

IlP e De1 30 D~ fp2 Eo I 2) DB2 ~ 2) 111-1----=--+-lt7 -~

(p SRQ 23 Jo [)8 3lt1 ~ Tl~ II i

Al

D-t~OSRQ lel ~1 -e DSIl REN 4 U I ID REN l2 ii DB4

bull 1 Ie Q __-=-2i--1 Dlt 1-i-1----+-lt7 -~ J IFC 1 ~J~ 14 IFe 21 11 DBS

bull I e-- l) us 1o-__2--i D7 13 D8ltu

I I I t~ ~~---t-ltJ -~ r-~======~~-~~~ ~_1 1= ~I L-_-4~--+------~4~O ReSI I I IN 1 8 3 -z AringT N = 2(P 6PI~bull I ( 37 E6 INDfgtC I l ( DAC Il 37 iCSO Al) I=-~---t-u -~ bull 1 bull ( lt136rp4J --____ 3=-4-1 RwiNRFOIO UL 0 RFD IS 3e iC51 Al I _ bull 1 (

--_--=30=-1 EXIll 14(1~lq _ i4- D- 1i1 3~ ilt 2- M 1 1 D7 1 0-- o-H bull I ( ~ M5B I - shy

I 3 c~ 1 I I-_---=3-11 XTALtO rPZGPIB I I III +gt

10

Rw

----J rGJll II 3~

1 D101 I~4 s

- D1o21 7 ---t-----~~t=t=~----~-~SV RE L I I 2 -HA-L-T3IDlogt 110 I U3 ASE

bull I I( )_ e 34 iP2 t5V --- 5 HR

4D1 04-I 15 1133 -- C4 1i111LI 4 IRQ I I I 1 +5 lgt 22 D() Vec ~ UlUe

Ibl C5 Pllltllto SoV

j3 1[)OW 2 IB4- -=- 32 Ph e I I I U~

L- el -- -NO

IB~ 3i U12shyIJ4 DlOl ~l 1ltgt T1gt I ~ F cp rP cp -=- (8V S~_ PIN 14- +sv~5D1071~2 U4 ) ID 1Bamp 3D DtvAGIA1oI1 --L ADAI Aringl A3 A~ Ar AIoA~ As 20 I - 35 ~NDPIN

~ D106 1 ~i iS 14- 1 B Z l eC i V C)C4 C3C2C Je ~3 AI5 t51

~ 2~

W I 11 e

1 2 I

zil u= 140 IRQ R- zo 1=-------- - ~TV

~ pto J 1 TI

4 tS~~

4 2

~gnlf[3EFI 13 c shy

121 Figure 2-2 1)BA-488 Data Bus (1] Ll- )4 Plt6 4 3 ~ 11-(NV Adapter ScWelnatic Diagram

2-4 1

237 POWER UP AND DEVICE ADDRESS

When power is applied to the DBA-488 the logic low level at test point TP2 (resulting from the uncharged state of C2) initializes U5 U10 UH and U6 The ASE (address select) output of U5 drops enabling the outputs of address switch S1 The five preset LSBs of Sl representing the primary device address are then transferred into a register in controller U5 for subsequent use

238 DATA TRANSFER

Controller U5 responds to the device address (applied via the data line inputs on the lE lines) when the IEEE bus sets ATN true Notified by U5 via the DB data lines U6 addresses ROM U9 which determines if talk or listen operation is reshyquired If the talk mode is selected U6 enables PIAs U10 and Ull and causes data from the instrument to be transferred through the PIAs to controller U5 which transfers the data through the IB lines to U3 and U4 These buffers enabled by a TR2 level from U5 transfer the required data to the IEEE bus Transmisshysion of the individual data bytes is accomplished in proper sequence as a function of the handshake procedure The bus management lines (ATN IFC SRQ EOI and REN) insure that information flows through the interface lines in orderly fashion When the last data bytes (ASCII carriage returnline feed) are transmitted the DBA-488 sets EOI true to signal the end of the data transfer This feature permits compatible operation of the DBA-488 with the HPIB system The entire sequence is terminated by an Untalk command from the controller

When the DBA-488 listen address is received data applied to U3 and U4 is transshyferred to controller U5 The microprocessor then transfers the data from U5 to the PIA s which pass the information to the instrument An EOI or carriage return line feed is received to indicate the end of the data transfer and the listen sequence is terminated by an Unlisten command

-

2-5

SECTION 3

DATA BUS ADAPTER DBA-488-SR400

31 EQUIPMENT SUPPLlED

311 DBA-488 ORDERED WITH SR-400

When the DBA-488 is ordered together with an SR-400 SynchroResolver Simulator the DBA-488 is bracket mounted at the rear of the SR-400 and both units are elecshytrically intercOIlllected through a cable (See figure 3-1) AC power is applied to the DBA-488 when the SR-400 is turned on The only component not supplied is the standard mating connector to the IEEE bus

31 2 DBA-488 ORDERED SEPARATE LY

When a DBA-488 is ordered separately (for retrofit to an SR-400) a mating conshynector for the instrument interface is supplied but is not wired The standard mating connector for the IEEE bus is not supplied Mounting hardware is included as required

The DBA-488 is not equipped with a power switch Line voltage (115 volts at 60 Hz) is applied via the instrument interface connector If the SR-400 front panel POWER switch is to controi the DBA-488 this switch must be wired to pins on the instrument This requires a modification to the SR-400 as shown in table 3-1

NOTE

The DBA-488 may be ordered for operation from 220 volts 5060 Hz

32 UNPACKING

Carefully remove the equipment from the packaging material and inspect for possible damage Should any unit show signs of damage notify the nearest ILC Data Device Corporation field representative immediately

33 INTERCONNECTIONS

Table 3-1 shows the interconnections between the DBA-488 and SR-400 and indicates the function of each lead For SR-400 units being retrofitted switched AC line voltage (115 volts) may be wired to pins 39 and 40 of instrument connector J2 Conshynect pin 39 of J2 to the switched terminal of POWER switch S8 and pin 40 to pin L of instrument connector J1 The interconnecting cable must be wired as shown in table 3-1

3-1

-

JS )foOHZ

J(

SR - 400

cJl pz

INSTRUt1EAJT ~I---------JYMCHRO OR REllI~ roNAlECro~ RESOLVER OUTPUT

I---------REF INPUT INTeuroRCONAlECTlN(J CA13LE ___

DBA-488 NS TRUI-feNT INrEliRIICE CONNECTOR

PI

DJ3A- 4BB

STANOARD HATNy COAlNeCTOR IEEEshyBUS

Figure 3-1_ DBA-488-SR400 Connection Diagram

3-2

-

-

SECTION 2

FUNCTIONAL DESCRIPTION OF DBA-488

INTRODUCTION21

This section provides a general functional description of the DBA-488 identifying the major input-output signals and covering basic signal flow Detailed step-byshystep operations within the DBA-488 are a function of the particular instrument and the stored program

22 BLOCK DIAGRAM DESCRIPTION (See figure 2-1)

Operation of the DBA-488 is supervised by a self-contained microprocessor in accordance with a program stored in an erasable programmable ROM Data transshyfer to and from the 16-line IEEE bus is mediated by the controller The 32 inputshyoutput lines at the instrument interface are independently programmed under microprocessor control for input or output data transfer according to the requireshyments of the particular instrument connected to the DBA-488 The device address preset manually by the user via the address select switches is transferred to the controller memory at power turn-on

23 FUNCTIONAL DESCRIPTION (See figure 2-2)

231 EQUIPMENT COMPLEMENT

The DBA-488 consists of four bus transceivers U1-U4 interface controller U5 microprocessor U6 tri-state buffers U7 and U8 ROM U9 and peripheral intershyface adapters (PIAs) U10 and Ull In addition a low voltage power supply consisting of power transformer T1 bridge rectifier CRA1 and voltage regulator VR1 provides 5 volts DC for operating the unit

232 TRANSCEIVERS U1 AND U2

Transceivers U1-U4 serve as the interface between the IEEE bus and the DBA-488 internal logic Transceivers U1 and U2 are used for bus management and handshake signals U3 and U4 accommodate the eight data lines Logic levels applied to the four transmit-receive inputs of each quad transceiver from controller U5 determine which section behaves as a bus driver or receiver for the associated bus line The T fR control for SRQ is always ired high (transmit) while those for REN 1FC and ATN are wired low (receive) The remaining signals are controlled by U5 The bus transceiver outputs meet all requirements of IEEE Std 488-1975

2-1

881T5512 Byr~ IO

ROM NTERshyB BITSFACE

tJ I BBIT

tJ ( DATA

INSTRUMENT IEEE INTERFACE488 32 10 UNS

BUS 8DITA LlNES 8 BIT5 PLUS

l DATA L JE S 8 CONT~

LINES 8 B I T 8 BITSL-----

mAlTROL IlDDRESStlleRO shySELECTPROCESSOR

SLJITCHES

Figure 2-1 DBA-488 Block Diagram bull

1 l ] ] I l J _J l l

-

-

-

233 INTERFACE CONTROLLER U5

Under the direction of microprocessor U6 interface controller U5 mediates the transfer of data between the DBA-488 and the IEEE bus Controller U5 decodes messages from the IEEE bus processes those directed to the DBA-488 and transshyfers messages to the internai data bus It should be noted that although the IEEE bus signals follow negative logic convention positive logic is used within the DBAshy488 (Thus the signal NRFD from the IEEE bus is designated RFD at the input of U5) The controller is equipped with internai registers that are selected by register select lines RSO RS1 and RS2 and chip select CS (via microprocessor address bits AO Al and A2 and Al4) in conjunction with the readwrite (RW) signals and ~2 clock from the microprocessor The registers accornmodate functions such as aringddress data in data out interrupt status etc Data transfer between U5 and U3 U4 is effected through the m - IB7 lines the DB~ - DB7 lines carry data between U5 and the internai data bus CS enables U5 and ~2 is a timing signal provided by U6

234 lVIICROPROCESSOR U6

The 8-bit microprocessor contains registers accumulators a 128 X 8 bit RAM and an internai clock The 16-line address bus (A~-A15) supervises the DBA-488 operations The 8-line bidirectional data bus (D~-D7) transfers data to and from memory and the peripheral devices Clock pulses at pin E (~2) are used for timing Upon receipt of an interrupt request (IRQ) from controller U5 (upon U5s receipt of DC L on the data lines) U6 completes its current instruction then cycles through an interrupt sequence that resets the microprocessor The read write (RW) output of U6 controls the read write status of controller U5 and PIAs U10 and Ull

235 ROM U9

Erasable prograrnmable ROM U9 stores the DBA-488 program in its 512 X 8 bit memory When enabled (CS input low) and strobed by a clock pulse from U6 (STR input) address bits A~-A8 are decoded and data transfer is effected on the DO~ - D07 lines

236 PIAS U10 AND Ull

PIAs U10 and Ull interface the DBA-488 with the DDC instrument Four 8-bit bidirectional data buses (PA~ - PA7 and PB~ - PB7) cornmunicate with the instrushyment an 8-bit bidirectional bus (D~ - D7) links the selected PIAs with the internai data bus Each chip is selected by ~ low via a U6 address routed through tri shystate buffer U8 Register select inputs (RS~ RS1) controlled by microprocessor U6 accress registers within each PIA which provide functions such as data direction control peripheral interface etc PIA readwrite operation is conshytrolled by the RIW input from U6

2-3

-------------------------------- I ISTR Ul-AENT 11rr E R r CE

P(gtG PM PAZ PA4 P80 PB+ PBz PB-p PAG PM PAz PAq PBlt PE ~-~PAl PA-5 PA~ PAI RESET PB7 PR - PS3 P81 PA PAS PA3 PAI PB Res PB Ps1

Po J I ~4+- ~a -0+ JJf- 1lt-+-14 ~1ls~ IIL 7 __ Z0 T2i l gt l ll ~J 2i1 ~ll~3 - - - ST l (T 3 T -41_3l-z let It f012Jtz2tz~t~d Z5

i2-1 I i I I (1 4 si 1111(1151 I~I iii lo

Po PO P O il 81 11 I si 4131 2 Ii I 11 151 141 b L) 8 1 1 2 141 121

Po UIO Ull Ull-j Ula

p AZ-BPIAI- 8 p IA2-APIAI-A $5i3ltgt(fJ $IB~~$ Coigt~~$6()CP

tgtrp D1 D21gt3 1gtlt 1gt5 D Di RfS RS0 RSI Cel R-w E c-S4gt cs 1 1gt1l1gt 1 DZ lgt3 D4- D5 [)( D7 RES es412S1C-SZ RW E CS(J CSI

3101 SSI 13III Il5l~ 2iI25~i13313lI3113121 251~712(13+1 J 3~ 135 r~ II SV ~~131 bl 281271211 3 +1 l u-fl 1 1elI

122 ~ -- t5V

~ t5V t5V bull Icamp tgtV I I bull 1 -O+shybull II 1 -- -----------+ ---- -------11--11-1---+------~c~ ~~ Al ~ ~IZ~~R3 AiIi

11 b14 aJ------t-U-~3DltPlO AfJ 32 DITIRI ze - cgtsltP ~~--t-- -~ J2 v 31 D2 U0

IlP e De1 30 D~ fp2 Eo I 2) DB2 ~ 2) 111-1----=--+-lt7 -~

(p SRQ 23 Jo [)8 3lt1 ~ Tl~ II i

Al

D-t~OSRQ lel ~1 -e DSIl REN 4 U I ID REN l2 ii DB4

bull 1 Ie Q __-=-2i--1 Dlt 1-i-1----+-lt7 -~ J IFC 1 ~J~ 14 IFe 21 11 DBS

bull I e-- l) us 1o-__2--i D7 13 D8ltu

I I I t~ ~~---t-ltJ -~ r-~======~~-~~~ ~_1 1= ~I L-_-4~--+------~4~O ReSI I I IN 1 8 3 -z AringT N = 2(P 6PI~bull I ( 37 E6 INDfgtC I l ( DAC Il 37 iCSO Al) I=-~---t-u -~ bull 1 bull ( lt136rp4J --____ 3=-4-1 RwiNRFOIO UL 0 RFD IS 3e iC51 Al I _ bull 1 (

--_--=30=-1 EXIll 14(1~lq _ i4- D- 1i1 3~ ilt 2- M 1 1 D7 1 0-- o-H bull I ( ~ M5B I - shy

I 3 c~ 1 I I-_---=3-11 XTALtO rPZGPIB I I III +gt

10

Rw

----J rGJll II 3~

1 D101 I~4 s

- D1o21 7 ---t-----~~t=t=~----~-~SV RE L I I 2 -HA-L-T3IDlogt 110 I U3 ASE

bull I I( )_ e 34 iP2 t5V --- 5 HR

4D1 04-I 15 1133 -- C4 1i111LI 4 IRQ I I I 1 +5 lgt 22 D() Vec ~ UlUe

Ibl C5 Pllltllto SoV

j3 1[)OW 2 IB4- -=- 32 Ph e I I I U~

L- el -- -NO

IB~ 3i U12shyIJ4 DlOl ~l 1ltgt T1gt I ~ F cp rP cp -=- (8V S~_ PIN 14- +sv~5D1071~2 U4 ) ID 1Bamp 3D DtvAGIA1oI1 --L ADAI Aringl A3 A~ Ar AIoA~ As 20 I - 35 ~NDPIN

~ D106 1 ~i iS 14- 1 B Z l eC i V C)C4 C3C2C Je ~3 AI5 t51

~ 2~

W I 11 e

1 2 I

zil u= 140 IRQ R- zo 1=-------- - ~TV

~ pto J 1 TI

4 tS~~

4 2

~gnlf[3EFI 13 c shy

121 Figure 2-2 1)BA-488 Data Bus (1] Ll- )4 Plt6 4 3 ~ 11-(NV Adapter ScWelnatic Diagram

2-4 1

237 POWER UP AND DEVICE ADDRESS

When power is applied to the DBA-488 the logic low level at test point TP2 (resulting from the uncharged state of C2) initializes U5 U10 UH and U6 The ASE (address select) output of U5 drops enabling the outputs of address switch S1 The five preset LSBs of Sl representing the primary device address are then transferred into a register in controller U5 for subsequent use

238 DATA TRANSFER

Controller U5 responds to the device address (applied via the data line inputs on the lE lines) when the IEEE bus sets ATN true Notified by U5 via the DB data lines U6 addresses ROM U9 which determines if talk or listen operation is reshyquired If the talk mode is selected U6 enables PIAs U10 and Ull and causes data from the instrument to be transferred through the PIAs to controller U5 which transfers the data through the IB lines to U3 and U4 These buffers enabled by a TR2 level from U5 transfer the required data to the IEEE bus Transmisshysion of the individual data bytes is accomplished in proper sequence as a function of the handshake procedure The bus management lines (ATN IFC SRQ EOI and REN) insure that information flows through the interface lines in orderly fashion When the last data bytes (ASCII carriage returnline feed) are transmitted the DBA-488 sets EOI true to signal the end of the data transfer This feature permits compatible operation of the DBA-488 with the HPIB system The entire sequence is terminated by an Untalk command from the controller

When the DBA-488 listen address is received data applied to U3 and U4 is transshyferred to controller U5 The microprocessor then transfers the data from U5 to the PIA s which pass the information to the instrument An EOI or carriage return line feed is received to indicate the end of the data transfer and the listen sequence is terminated by an Unlisten command

-

2-5

SECTION 3

DATA BUS ADAPTER DBA-488-SR400

31 EQUIPMENT SUPPLlED

311 DBA-488 ORDERED WITH SR-400

When the DBA-488 is ordered together with an SR-400 SynchroResolver Simulator the DBA-488 is bracket mounted at the rear of the SR-400 and both units are elecshytrically intercOIlllected through a cable (See figure 3-1) AC power is applied to the DBA-488 when the SR-400 is turned on The only component not supplied is the standard mating connector to the IEEE bus

31 2 DBA-488 ORDERED SEPARATE LY

When a DBA-488 is ordered separately (for retrofit to an SR-400) a mating conshynector for the instrument interface is supplied but is not wired The standard mating connector for the IEEE bus is not supplied Mounting hardware is included as required

The DBA-488 is not equipped with a power switch Line voltage (115 volts at 60 Hz) is applied via the instrument interface connector If the SR-400 front panel POWER switch is to controi the DBA-488 this switch must be wired to pins on the instrument This requires a modification to the SR-400 as shown in table 3-1

NOTE

The DBA-488 may be ordered for operation from 220 volts 5060 Hz

32 UNPACKING

Carefully remove the equipment from the packaging material and inspect for possible damage Should any unit show signs of damage notify the nearest ILC Data Device Corporation field representative immediately

33 INTERCONNECTIONS

Table 3-1 shows the interconnections between the DBA-488 and SR-400 and indicates the function of each lead For SR-400 units being retrofitted switched AC line voltage (115 volts) may be wired to pins 39 and 40 of instrument connector J2 Conshynect pin 39 of J2 to the switched terminal of POWER switch S8 and pin 40 to pin L of instrument connector J1 The interconnecting cable must be wired as shown in table 3-1

3-1

-

JS )foOHZ

J(

SR - 400

cJl pz

INSTRUt1EAJT ~I---------JYMCHRO OR REllI~ roNAlECro~ RESOLVER OUTPUT

I---------REF INPUT INTeuroRCONAlECTlN(J CA13LE ___

DBA-488 NS TRUI-feNT INrEliRIICE CONNECTOR

PI

DJ3A- 4BB

STANOARD HATNy COAlNeCTOR IEEEshyBUS

Figure 3-1_ DBA-488-SR400 Connection Diagram

3-2

881T5512 Byr~ IO

ROM NTERshyB BITSFACE

tJ I BBIT

tJ ( DATA

INSTRUMENT IEEE INTERFACE488 32 10 UNS

BUS 8DITA LlNES 8 BIT5 PLUS

l DATA L JE S 8 CONT~

LINES 8 B I T 8 BITSL-----

mAlTROL IlDDRESStlleRO shySELECTPROCESSOR

SLJITCHES

Figure 2-1 DBA-488 Block Diagram bull

1 l ] ] I l J _J l l

-

-

-

233 INTERFACE CONTROLLER U5

Under the direction of microprocessor U6 interface controller U5 mediates the transfer of data between the DBA-488 and the IEEE bus Controller U5 decodes messages from the IEEE bus processes those directed to the DBA-488 and transshyfers messages to the internai data bus It should be noted that although the IEEE bus signals follow negative logic convention positive logic is used within the DBAshy488 (Thus the signal NRFD from the IEEE bus is designated RFD at the input of U5) The controller is equipped with internai registers that are selected by register select lines RSO RS1 and RS2 and chip select CS (via microprocessor address bits AO Al and A2 and Al4) in conjunction with the readwrite (RW) signals and ~2 clock from the microprocessor The registers accornmodate functions such as aringddress data in data out interrupt status etc Data transfer between U5 and U3 U4 is effected through the m - IB7 lines the DB~ - DB7 lines carry data between U5 and the internai data bus CS enables U5 and ~2 is a timing signal provided by U6

234 lVIICROPROCESSOR U6

The 8-bit microprocessor contains registers accumulators a 128 X 8 bit RAM and an internai clock The 16-line address bus (A~-A15) supervises the DBA-488 operations The 8-line bidirectional data bus (D~-D7) transfers data to and from memory and the peripheral devices Clock pulses at pin E (~2) are used for timing Upon receipt of an interrupt request (IRQ) from controller U5 (upon U5s receipt of DC L on the data lines) U6 completes its current instruction then cycles through an interrupt sequence that resets the microprocessor The read write (RW) output of U6 controls the read write status of controller U5 and PIAs U10 and Ull

235 ROM U9

Erasable prograrnmable ROM U9 stores the DBA-488 program in its 512 X 8 bit memory When enabled (CS input low) and strobed by a clock pulse from U6 (STR input) address bits A~-A8 are decoded and data transfer is effected on the DO~ - D07 lines

236 PIAS U10 AND Ull

PIAs U10 and Ull interface the DBA-488 with the DDC instrument Four 8-bit bidirectional data buses (PA~ - PA7 and PB~ - PB7) cornmunicate with the instrushyment an 8-bit bidirectional bus (D~ - D7) links the selected PIAs with the internai data bus Each chip is selected by ~ low via a U6 address routed through tri shystate buffer U8 Register select inputs (RS~ RS1) controlled by microprocessor U6 accress registers within each PIA which provide functions such as data direction control peripheral interface etc PIA readwrite operation is conshytrolled by the RIW input from U6

2-3

-------------------------------- I ISTR Ul-AENT 11rr E R r CE

P(gtG PM PAZ PA4 P80 PB+ PBz PB-p PAG PM PAz PAq PBlt PE ~-~PAl PA-5 PA~ PAI RESET PB7 PR - PS3 P81 PA PAS PA3 PAI PB Res PB Ps1

Po J I ~4+- ~a -0+ JJf- 1lt-+-14 ~1ls~ IIL 7 __ Z0 T2i l gt l ll ~J 2i1 ~ll~3 - - - ST l (T 3 T -41_3l-z let It f012Jtz2tz~t~d Z5

i2-1 I i I I (1 4 si 1111(1151 I~I iii lo

Po PO P O il 81 11 I si 4131 2 Ii I 11 151 141 b L) 8 1 1 2 141 121

Po UIO Ull Ull-j Ula

p AZ-BPIAI- 8 p IA2-APIAI-A $5i3ltgt(fJ $IB~~$ Coigt~~$6()CP

tgtrp D1 D21gt3 1gtlt 1gt5 D Di RfS RS0 RSI Cel R-w E c-S4gt cs 1 1gt1l1gt 1 DZ lgt3 D4- D5 [)( D7 RES es412S1C-SZ RW E CS(J CSI

3101 SSI 13III Il5l~ 2iI25~i13313lI3113121 251~712(13+1 J 3~ 135 r~ II SV ~~131 bl 281271211 3 +1 l u-fl 1 1elI

122 ~ -- t5V

~ t5V t5V bull Icamp tgtV I I bull 1 -O+shybull II 1 -- -----------+ ---- -------11--11-1---+------~c~ ~~ Al ~ ~IZ~~R3 AiIi

11 b14 aJ------t-U-~3DltPlO AfJ 32 DITIRI ze - cgtsltP ~~--t-- -~ J2 v 31 D2 U0

IlP e De1 30 D~ fp2 Eo I 2) DB2 ~ 2) 111-1----=--+-lt7 -~

(p SRQ 23 Jo [)8 3lt1 ~ Tl~ II i

Al

D-t~OSRQ lel ~1 -e DSIl REN 4 U I ID REN l2 ii DB4

bull 1 Ie Q __-=-2i--1 Dlt 1-i-1----+-lt7 -~ J IFC 1 ~J~ 14 IFe 21 11 DBS

bull I e-- l) us 1o-__2--i D7 13 D8ltu

I I I t~ ~~---t-ltJ -~ r-~======~~-~~~ ~_1 1= ~I L-_-4~--+------~4~O ReSI I I IN 1 8 3 -z AringT N = 2(P 6PI~bull I ( 37 E6 INDfgtC I l ( DAC Il 37 iCSO Al) I=-~---t-u -~ bull 1 bull ( lt136rp4J --____ 3=-4-1 RwiNRFOIO UL 0 RFD IS 3e iC51 Al I _ bull 1 (

--_--=30=-1 EXIll 14(1~lq _ i4- D- 1i1 3~ ilt 2- M 1 1 D7 1 0-- o-H bull I ( ~ M5B I - shy

I 3 c~ 1 I I-_---=3-11 XTALtO rPZGPIB I I III +gt

10

Rw

----J rGJll II 3~

1 D101 I~4 s

- D1o21 7 ---t-----~~t=t=~----~-~SV RE L I I 2 -HA-L-T3IDlogt 110 I U3 ASE

bull I I( )_ e 34 iP2 t5V --- 5 HR

4D1 04-I 15 1133 -- C4 1i111LI 4 IRQ I I I 1 +5 lgt 22 D() Vec ~ UlUe

Ibl C5 Pllltllto SoV

j3 1[)OW 2 IB4- -=- 32 Ph e I I I U~

L- el -- -NO

IB~ 3i U12shyIJ4 DlOl ~l 1ltgt T1gt I ~ F cp rP cp -=- (8V S~_ PIN 14- +sv~5D1071~2 U4 ) ID 1Bamp 3D DtvAGIA1oI1 --L ADAI Aringl A3 A~ Ar AIoA~ As 20 I - 35 ~NDPIN

~ D106 1 ~i iS 14- 1 B Z l eC i V C)C4 C3C2C Je ~3 AI5 t51

~ 2~

W I 11 e

1 2 I

zil u= 140 IRQ R- zo 1=-------- - ~TV

~ pto J 1 TI

4 tS~~

4 2

~gnlf[3EFI 13 c shy

121 Figure 2-2 1)BA-488 Data Bus (1] Ll- )4 Plt6 4 3 ~ 11-(NV Adapter ScWelnatic Diagram

2-4 1

237 POWER UP AND DEVICE ADDRESS

When power is applied to the DBA-488 the logic low level at test point TP2 (resulting from the uncharged state of C2) initializes U5 U10 UH and U6 The ASE (address select) output of U5 drops enabling the outputs of address switch S1 The five preset LSBs of Sl representing the primary device address are then transferred into a register in controller U5 for subsequent use

238 DATA TRANSFER

Controller U5 responds to the device address (applied via the data line inputs on the lE lines) when the IEEE bus sets ATN true Notified by U5 via the DB data lines U6 addresses ROM U9 which determines if talk or listen operation is reshyquired If the talk mode is selected U6 enables PIAs U10 and Ull and causes data from the instrument to be transferred through the PIAs to controller U5 which transfers the data through the IB lines to U3 and U4 These buffers enabled by a TR2 level from U5 transfer the required data to the IEEE bus Transmisshysion of the individual data bytes is accomplished in proper sequence as a function of the handshake procedure The bus management lines (ATN IFC SRQ EOI and REN) insure that information flows through the interface lines in orderly fashion When the last data bytes (ASCII carriage returnline feed) are transmitted the DBA-488 sets EOI true to signal the end of the data transfer This feature permits compatible operation of the DBA-488 with the HPIB system The entire sequence is terminated by an Untalk command from the controller

When the DBA-488 listen address is received data applied to U3 and U4 is transshyferred to controller U5 The microprocessor then transfers the data from U5 to the PIA s which pass the information to the instrument An EOI or carriage return line feed is received to indicate the end of the data transfer and the listen sequence is terminated by an Unlisten command

-

2-5

SECTION 3

DATA BUS ADAPTER DBA-488-SR400

31 EQUIPMENT SUPPLlED

311 DBA-488 ORDERED WITH SR-400

When the DBA-488 is ordered together with an SR-400 SynchroResolver Simulator the DBA-488 is bracket mounted at the rear of the SR-400 and both units are elecshytrically intercOIlllected through a cable (See figure 3-1) AC power is applied to the DBA-488 when the SR-400 is turned on The only component not supplied is the standard mating connector to the IEEE bus

31 2 DBA-488 ORDERED SEPARATE LY

When a DBA-488 is ordered separately (for retrofit to an SR-400) a mating conshynector for the instrument interface is supplied but is not wired The standard mating connector for the IEEE bus is not supplied Mounting hardware is included as required

The DBA-488 is not equipped with a power switch Line voltage (115 volts at 60 Hz) is applied via the instrument interface connector If the SR-400 front panel POWER switch is to controi the DBA-488 this switch must be wired to pins on the instrument This requires a modification to the SR-400 as shown in table 3-1

NOTE

The DBA-488 may be ordered for operation from 220 volts 5060 Hz

32 UNPACKING

Carefully remove the equipment from the packaging material and inspect for possible damage Should any unit show signs of damage notify the nearest ILC Data Device Corporation field representative immediately

33 INTERCONNECTIONS

Table 3-1 shows the interconnections between the DBA-488 and SR-400 and indicates the function of each lead For SR-400 units being retrofitted switched AC line voltage (115 volts) may be wired to pins 39 and 40 of instrument connector J2 Conshynect pin 39 of J2 to the switched terminal of POWER switch S8 and pin 40 to pin L of instrument connector J1 The interconnecting cable must be wired as shown in table 3-1

3-1

-

JS )foOHZ

J(

SR - 400

cJl pz

INSTRUt1EAJT ~I---------JYMCHRO OR REllI~ roNAlECro~ RESOLVER OUTPUT

I---------REF INPUT INTeuroRCONAlECTlN(J CA13LE ___

DBA-488 NS TRUI-feNT INrEliRIICE CONNECTOR

PI

DJ3A- 4BB

STANOARD HATNy COAlNeCTOR IEEEshyBUS

Figure 3-1_ DBA-488-SR400 Connection Diagram

3-2

-

-

-

233 INTERFACE CONTROLLER U5

Under the direction of microprocessor U6 interface controller U5 mediates the transfer of data between the DBA-488 and the IEEE bus Controller U5 decodes messages from the IEEE bus processes those directed to the DBA-488 and transshyfers messages to the internai data bus It should be noted that although the IEEE bus signals follow negative logic convention positive logic is used within the DBAshy488 (Thus the signal NRFD from the IEEE bus is designated RFD at the input of U5) The controller is equipped with internai registers that are selected by register select lines RSO RS1 and RS2 and chip select CS (via microprocessor address bits AO Al and A2 and Al4) in conjunction with the readwrite (RW) signals and ~2 clock from the microprocessor The registers accornmodate functions such as aringddress data in data out interrupt status etc Data transfer between U5 and U3 U4 is effected through the m - IB7 lines the DB~ - DB7 lines carry data between U5 and the internai data bus CS enables U5 and ~2 is a timing signal provided by U6

234 lVIICROPROCESSOR U6

The 8-bit microprocessor contains registers accumulators a 128 X 8 bit RAM and an internai clock The 16-line address bus (A~-A15) supervises the DBA-488 operations The 8-line bidirectional data bus (D~-D7) transfers data to and from memory and the peripheral devices Clock pulses at pin E (~2) are used for timing Upon receipt of an interrupt request (IRQ) from controller U5 (upon U5s receipt of DC L on the data lines) U6 completes its current instruction then cycles through an interrupt sequence that resets the microprocessor The read write (RW) output of U6 controls the read write status of controller U5 and PIAs U10 and Ull

235 ROM U9

Erasable prograrnmable ROM U9 stores the DBA-488 program in its 512 X 8 bit memory When enabled (CS input low) and strobed by a clock pulse from U6 (STR input) address bits A~-A8 are decoded and data transfer is effected on the DO~ - D07 lines

236 PIAS U10 AND Ull

PIAs U10 and Ull interface the DBA-488 with the DDC instrument Four 8-bit bidirectional data buses (PA~ - PA7 and PB~ - PB7) cornmunicate with the instrushyment an 8-bit bidirectional bus (D~ - D7) links the selected PIAs with the internai data bus Each chip is selected by ~ low via a U6 address routed through tri shystate buffer U8 Register select inputs (RS~ RS1) controlled by microprocessor U6 accress registers within each PIA which provide functions such as data direction control peripheral interface etc PIA readwrite operation is conshytrolled by the RIW input from U6

2-3

-------------------------------- I ISTR Ul-AENT 11rr E R r CE

P(gtG PM PAZ PA4 P80 PB+ PBz PB-p PAG PM PAz PAq PBlt PE ~-~PAl PA-5 PA~ PAI RESET PB7 PR - PS3 P81 PA PAS PA3 PAI PB Res PB Ps1

Po J I ~4+- ~a -0+ JJf- 1lt-+-14 ~1ls~ IIL 7 __ Z0 T2i l gt l ll ~J 2i1 ~ll~3 - - - ST l (T 3 T -41_3l-z let It f012Jtz2tz~t~d Z5

i2-1 I i I I (1 4 si 1111(1151 I~I iii lo

Po PO P O il 81 11 I si 4131 2 Ii I 11 151 141 b L) 8 1 1 2 141 121

Po UIO Ull Ull-j Ula

p AZ-BPIAI- 8 p IA2-APIAI-A $5i3ltgt(fJ $IB~~$ Coigt~~$6()CP

tgtrp D1 D21gt3 1gtlt 1gt5 D Di RfS RS0 RSI Cel R-w E c-S4gt cs 1 1gt1l1gt 1 DZ lgt3 D4- D5 [)( D7 RES es412S1C-SZ RW E CS(J CSI

3101 SSI 13III Il5l~ 2iI25~i13313lI3113121 251~712(13+1 J 3~ 135 r~ II SV ~~131 bl 281271211 3 +1 l u-fl 1 1elI

122 ~ -- t5V

~ t5V t5V bull Icamp tgtV I I bull 1 -O+shybull II 1 -- -----------+ ---- -------11--11-1---+------~c~ ~~ Al ~ ~IZ~~R3 AiIi

11 b14 aJ------t-U-~3DltPlO AfJ 32 DITIRI ze - cgtsltP ~~--t-- -~ J2 v 31 D2 U0

IlP e De1 30 D~ fp2 Eo I 2) DB2 ~ 2) 111-1----=--+-lt7 -~

(p SRQ 23 Jo [)8 3lt1 ~ Tl~ II i

Al

D-t~OSRQ lel ~1 -e DSIl REN 4 U I ID REN l2 ii DB4

bull 1 Ie Q __-=-2i--1 Dlt 1-i-1----+-lt7 -~ J IFC 1 ~J~ 14 IFe 21 11 DBS

bull I e-- l) us 1o-__2--i D7 13 D8ltu

I I I t~ ~~---t-ltJ -~ r-~======~~-~~~ ~_1 1= ~I L-_-4~--+------~4~O ReSI I I IN 1 8 3 -z AringT N = 2(P 6PI~bull I ( 37 E6 INDfgtC I l ( DAC Il 37 iCSO Al) I=-~---t-u -~ bull 1 bull ( lt136rp4J --____ 3=-4-1 RwiNRFOIO UL 0 RFD IS 3e iC51 Al I _ bull 1 (

--_--=30=-1 EXIll 14(1~lq _ i4- D- 1i1 3~ ilt 2- M 1 1 D7 1 0-- o-H bull I ( ~ M5B I - shy

I 3 c~ 1 I I-_---=3-11 XTALtO rPZGPIB I I III +gt

10

Rw

----J rGJll II 3~

1 D101 I~4 s

- D1o21 7 ---t-----~~t=t=~----~-~SV RE L I I 2 -HA-L-T3IDlogt 110 I U3 ASE

bull I I( )_ e 34 iP2 t5V --- 5 HR

4D1 04-I 15 1133 -- C4 1i111LI 4 IRQ I I I 1 +5 lgt 22 D() Vec ~ UlUe

Ibl C5 Pllltllto SoV

j3 1[)OW 2 IB4- -=- 32 Ph e I I I U~

L- el -- -NO

IB~ 3i U12shyIJ4 DlOl ~l 1ltgt T1gt I ~ F cp rP cp -=- (8V S~_ PIN 14- +sv~5D1071~2 U4 ) ID 1Bamp 3D DtvAGIA1oI1 --L ADAI Aringl A3 A~ Ar AIoA~ As 20 I - 35 ~NDPIN

~ D106 1 ~i iS 14- 1 B Z l eC i V C)C4 C3C2C Je ~3 AI5 t51

~ 2~

W I 11 e

1 2 I

zil u= 140 IRQ R- zo 1=-------- - ~TV

~ pto J 1 TI

4 tS~~

4 2

~gnlf[3EFI 13 c shy

121 Figure 2-2 1)BA-488 Data Bus (1] Ll- )4 Plt6 4 3 ~ 11-(NV Adapter ScWelnatic Diagram

2-4 1

237 POWER UP AND DEVICE ADDRESS

When power is applied to the DBA-488 the logic low level at test point TP2 (resulting from the uncharged state of C2) initializes U5 U10 UH and U6 The ASE (address select) output of U5 drops enabling the outputs of address switch S1 The five preset LSBs of Sl representing the primary device address are then transferred into a register in controller U5 for subsequent use

238 DATA TRANSFER

Controller U5 responds to the device address (applied via the data line inputs on the lE lines) when the IEEE bus sets ATN true Notified by U5 via the DB data lines U6 addresses ROM U9 which determines if talk or listen operation is reshyquired If the talk mode is selected U6 enables PIAs U10 and Ull and causes data from the instrument to be transferred through the PIAs to controller U5 which transfers the data through the IB lines to U3 and U4 These buffers enabled by a TR2 level from U5 transfer the required data to the IEEE bus Transmisshysion of the individual data bytes is accomplished in proper sequence as a function of the handshake procedure The bus management lines (ATN IFC SRQ EOI and REN) insure that information flows through the interface lines in orderly fashion When the last data bytes (ASCII carriage returnline feed) are transmitted the DBA-488 sets EOI true to signal the end of the data transfer This feature permits compatible operation of the DBA-488 with the HPIB system The entire sequence is terminated by an Untalk command from the controller

When the DBA-488 listen address is received data applied to U3 and U4 is transshyferred to controller U5 The microprocessor then transfers the data from U5 to the PIA s which pass the information to the instrument An EOI or carriage return line feed is received to indicate the end of the data transfer and the listen sequence is terminated by an Unlisten command

-

2-5

SECTION 3

DATA BUS ADAPTER DBA-488-SR400

31 EQUIPMENT SUPPLlED

311 DBA-488 ORDERED WITH SR-400

When the DBA-488 is ordered together with an SR-400 SynchroResolver Simulator the DBA-488 is bracket mounted at the rear of the SR-400 and both units are elecshytrically intercOIlllected through a cable (See figure 3-1) AC power is applied to the DBA-488 when the SR-400 is turned on The only component not supplied is the standard mating connector to the IEEE bus

31 2 DBA-488 ORDERED SEPARATE LY

When a DBA-488 is ordered separately (for retrofit to an SR-400) a mating conshynector for the instrument interface is supplied but is not wired The standard mating connector for the IEEE bus is not supplied Mounting hardware is included as required

The DBA-488 is not equipped with a power switch Line voltage (115 volts at 60 Hz) is applied via the instrument interface connector If the SR-400 front panel POWER switch is to controi the DBA-488 this switch must be wired to pins on the instrument This requires a modification to the SR-400 as shown in table 3-1

NOTE

The DBA-488 may be ordered for operation from 220 volts 5060 Hz

32 UNPACKING

Carefully remove the equipment from the packaging material and inspect for possible damage Should any unit show signs of damage notify the nearest ILC Data Device Corporation field representative immediately

33 INTERCONNECTIONS

Table 3-1 shows the interconnections between the DBA-488 and SR-400 and indicates the function of each lead For SR-400 units being retrofitted switched AC line voltage (115 volts) may be wired to pins 39 and 40 of instrument connector J2 Conshynect pin 39 of J2 to the switched terminal of POWER switch S8 and pin 40 to pin L of instrument connector J1 The interconnecting cable must be wired as shown in table 3-1

3-1

-

JS )foOHZ

J(

SR - 400

cJl pz

INSTRUt1EAJT ~I---------JYMCHRO OR REllI~ roNAlECro~ RESOLVER OUTPUT

I---------REF INPUT INTeuroRCONAlECTlN(J CA13LE ___

DBA-488 NS TRUI-feNT INrEliRIICE CONNECTOR

PI

DJ3A- 4BB

STANOARD HATNy COAlNeCTOR IEEEshyBUS

Figure 3-1_ DBA-488-SR400 Connection Diagram

3-2

-------------------------------- I ISTR Ul-AENT 11rr E R r CE

P(gtG PM PAZ PA4 P80 PB+ PBz PB-p PAG PM PAz PAq PBlt PE ~-~PAl PA-5 PA~ PAI RESET PB7 PR - PS3 P81 PA PAS PA3 PAI PB Res PB Ps1

Po J I ~4+- ~a -0+ JJf- 1lt-+-14 ~1ls~ IIL 7 __ Z0 T2i l gt l ll ~J 2i1 ~ll~3 - - - ST l (T 3 T -41_3l-z let It f012Jtz2tz~t~d Z5

i2-1 I i I I (1 4 si 1111(1151 I~I iii lo

Po PO P O il 81 11 I si 4131 2 Ii I 11 151 141 b L) 8 1 1 2 141 121

Po UIO Ull Ull-j Ula

p AZ-BPIAI- 8 p IA2-APIAI-A $5i3ltgt(fJ $IB~~$ Coigt~~$6()CP

tgtrp D1 D21gt3 1gtlt 1gt5 D Di RfS RS0 RSI Cel R-w E c-S4gt cs 1 1gt1l1gt 1 DZ lgt3 D4- D5 [)( D7 RES es412S1C-SZ RW E CS(J CSI

3101 SSI 13III Il5l~ 2iI25~i13313lI3113121 251~712(13+1 J 3~ 135 r~ II SV ~~131 bl 281271211 3 +1 l u-fl 1 1elI

122 ~ -- t5V

~ t5V t5V bull Icamp tgtV I I bull 1 -O+shybull II 1 -- -----------+ ---- -------11--11-1---+------~c~ ~~ Al ~ ~IZ~~R3 AiIi

11 b14 aJ------t-U-~3DltPlO AfJ 32 DITIRI ze - cgtsltP ~~--t-- -~ J2 v 31 D2 U0

IlP e De1 30 D~ fp2 Eo I 2) DB2 ~ 2) 111-1----=--+-lt7 -~

(p SRQ 23 Jo [)8 3lt1 ~ Tl~ II i

Al

D-t~OSRQ lel ~1 -e DSIl REN 4 U I ID REN l2 ii DB4

bull 1 Ie Q __-=-2i--1 Dlt 1-i-1----+-lt7 -~ J IFC 1 ~J~ 14 IFe 21 11 DBS

bull I e-- l) us 1o-__2--i D7 13 D8ltu

I I I t~ ~~---t-ltJ -~ r-~======~~-~~~ ~_1 1= ~I L-_-4~--+------~4~O ReSI I I IN 1 8 3 -z AringT N = 2(P 6PI~bull I ( 37 E6 INDfgtC I l ( DAC Il 37 iCSO Al) I=-~---t-u -~ bull 1 bull ( lt136rp4J --____ 3=-4-1 RwiNRFOIO UL 0 RFD IS 3e iC51 Al I _ bull 1 (

--_--=30=-1 EXIll 14(1~lq _ i4- D- 1i1 3~ ilt 2- M 1 1 D7 1 0-- o-H bull I ( ~ M5B I - shy

I 3 c~ 1 I I-_---=3-11 XTALtO rPZGPIB I I III +gt

10

Rw

----J rGJll II 3~

1 D101 I~4 s

- D1o21 7 ---t-----~~t=t=~----~-~SV RE L I I 2 -HA-L-T3IDlogt 110 I U3 ASE

bull I I( )_ e 34 iP2 t5V --- 5 HR

4D1 04-I 15 1133 -- C4 1i111LI 4 IRQ I I I 1 +5 lgt 22 D() Vec ~ UlUe

Ibl C5 Pllltllto SoV

j3 1[)OW 2 IB4- -=- 32 Ph e I I I U~

L- el -- -NO

IB~ 3i U12shyIJ4 DlOl ~l 1ltgt T1gt I ~ F cp rP cp -=- (8V S~_ PIN 14- +sv~5D1071~2 U4 ) ID 1Bamp 3D DtvAGIA1oI1 --L ADAI Aringl A3 A~ Ar AIoA~ As 20 I - 35 ~NDPIN

~ D106 1 ~i iS 14- 1 B Z l eC i V C)C4 C3C2C Je ~3 AI5 t51

~ 2~

W I 11 e

1 2 I

zil u= 140 IRQ R- zo 1=-------- - ~TV

~ pto J 1 TI

4 tS~~

4 2

~gnlf[3EFI 13 c shy

121 Figure 2-2 1)BA-488 Data Bus (1] Ll- )4 Plt6 4 3 ~ 11-(NV Adapter ScWelnatic Diagram

2-4 1

237 POWER UP AND DEVICE ADDRESS

When power is applied to the DBA-488 the logic low level at test point TP2 (resulting from the uncharged state of C2) initializes U5 U10 UH and U6 The ASE (address select) output of U5 drops enabling the outputs of address switch S1 The five preset LSBs of Sl representing the primary device address are then transferred into a register in controller U5 for subsequent use

238 DATA TRANSFER

Controller U5 responds to the device address (applied via the data line inputs on the lE lines) when the IEEE bus sets ATN true Notified by U5 via the DB data lines U6 addresses ROM U9 which determines if talk or listen operation is reshyquired If the talk mode is selected U6 enables PIAs U10 and Ull and causes data from the instrument to be transferred through the PIAs to controller U5 which transfers the data through the IB lines to U3 and U4 These buffers enabled by a TR2 level from U5 transfer the required data to the IEEE bus Transmisshysion of the individual data bytes is accomplished in proper sequence as a function of the handshake procedure The bus management lines (ATN IFC SRQ EOI and REN) insure that information flows through the interface lines in orderly fashion When the last data bytes (ASCII carriage returnline feed) are transmitted the DBA-488 sets EOI true to signal the end of the data transfer This feature permits compatible operation of the DBA-488 with the HPIB system The entire sequence is terminated by an Untalk command from the controller

When the DBA-488 listen address is received data applied to U3 and U4 is transshyferred to controller U5 The microprocessor then transfers the data from U5 to the PIA s which pass the information to the instrument An EOI or carriage return line feed is received to indicate the end of the data transfer and the listen sequence is terminated by an Unlisten command

-

2-5

SECTION 3

DATA BUS ADAPTER DBA-488-SR400

31 EQUIPMENT SUPPLlED

311 DBA-488 ORDERED WITH SR-400

When the DBA-488 is ordered together with an SR-400 SynchroResolver Simulator the DBA-488 is bracket mounted at the rear of the SR-400 and both units are elecshytrically intercOIlllected through a cable (See figure 3-1) AC power is applied to the DBA-488 when the SR-400 is turned on The only component not supplied is the standard mating connector to the IEEE bus

31 2 DBA-488 ORDERED SEPARATE LY

When a DBA-488 is ordered separately (for retrofit to an SR-400) a mating conshynector for the instrument interface is supplied but is not wired The standard mating connector for the IEEE bus is not supplied Mounting hardware is included as required

The DBA-488 is not equipped with a power switch Line voltage (115 volts at 60 Hz) is applied via the instrument interface connector If the SR-400 front panel POWER switch is to controi the DBA-488 this switch must be wired to pins on the instrument This requires a modification to the SR-400 as shown in table 3-1

NOTE

The DBA-488 may be ordered for operation from 220 volts 5060 Hz

32 UNPACKING

Carefully remove the equipment from the packaging material and inspect for possible damage Should any unit show signs of damage notify the nearest ILC Data Device Corporation field representative immediately

33 INTERCONNECTIONS

Table 3-1 shows the interconnections between the DBA-488 and SR-400 and indicates the function of each lead For SR-400 units being retrofitted switched AC line voltage (115 volts) may be wired to pins 39 and 40 of instrument connector J2 Conshynect pin 39 of J2 to the switched terminal of POWER switch S8 and pin 40 to pin L of instrument connector J1 The interconnecting cable must be wired as shown in table 3-1

3-1

-

JS )foOHZ

J(

SR - 400

cJl pz

INSTRUt1EAJT ~I---------JYMCHRO OR REllI~ roNAlECro~ RESOLVER OUTPUT

I---------REF INPUT INTeuroRCONAlECTlN(J CA13LE ___

DBA-488 NS TRUI-feNT INrEliRIICE CONNECTOR

PI

DJ3A- 4BB

STANOARD HATNy COAlNeCTOR IEEEshyBUS

Figure 3-1_ DBA-488-SR400 Connection Diagram

3-2

237 POWER UP AND DEVICE ADDRESS

When power is applied to the DBA-488 the logic low level at test point TP2 (resulting from the uncharged state of C2) initializes U5 U10 UH and U6 The ASE (address select) output of U5 drops enabling the outputs of address switch S1 The five preset LSBs of Sl representing the primary device address are then transferred into a register in controller U5 for subsequent use

238 DATA TRANSFER

Controller U5 responds to the device address (applied via the data line inputs on the lE lines) when the IEEE bus sets ATN true Notified by U5 via the DB data lines U6 addresses ROM U9 which determines if talk or listen operation is reshyquired If the talk mode is selected U6 enables PIAs U10 and Ull and causes data from the instrument to be transferred through the PIAs to controller U5 which transfers the data through the IB lines to U3 and U4 These buffers enabled by a TR2 level from U5 transfer the required data to the IEEE bus Transmisshysion of the individual data bytes is accomplished in proper sequence as a function of the handshake procedure The bus management lines (ATN IFC SRQ EOI and REN) insure that information flows through the interface lines in orderly fashion When the last data bytes (ASCII carriage returnline feed) are transmitted the DBA-488 sets EOI true to signal the end of the data transfer This feature permits compatible operation of the DBA-488 with the HPIB system The entire sequence is terminated by an Untalk command from the controller

When the DBA-488 listen address is received data applied to U3 and U4 is transshyferred to controller U5 The microprocessor then transfers the data from U5 to the PIA s which pass the information to the instrument An EOI or carriage return line feed is received to indicate the end of the data transfer and the listen sequence is terminated by an Unlisten command

-

2-5

SECTION 3

DATA BUS ADAPTER DBA-488-SR400

31 EQUIPMENT SUPPLlED

311 DBA-488 ORDERED WITH SR-400

When the DBA-488 is ordered together with an SR-400 SynchroResolver Simulator the DBA-488 is bracket mounted at the rear of the SR-400 and both units are elecshytrically intercOIlllected through a cable (See figure 3-1) AC power is applied to the DBA-488 when the SR-400 is turned on The only component not supplied is the standard mating connector to the IEEE bus

31 2 DBA-488 ORDERED SEPARATE LY

When a DBA-488 is ordered separately (for retrofit to an SR-400) a mating conshynector for the instrument interface is supplied but is not wired The standard mating connector for the IEEE bus is not supplied Mounting hardware is included as required

The DBA-488 is not equipped with a power switch Line voltage (115 volts at 60 Hz) is applied via the instrument interface connector If the SR-400 front panel POWER switch is to controi the DBA-488 this switch must be wired to pins on the instrument This requires a modification to the SR-400 as shown in table 3-1

NOTE

The DBA-488 may be ordered for operation from 220 volts 5060 Hz

32 UNPACKING

Carefully remove the equipment from the packaging material and inspect for possible damage Should any unit show signs of damage notify the nearest ILC Data Device Corporation field representative immediately

33 INTERCONNECTIONS

Table 3-1 shows the interconnections between the DBA-488 and SR-400 and indicates the function of each lead For SR-400 units being retrofitted switched AC line voltage (115 volts) may be wired to pins 39 and 40 of instrument connector J2 Conshynect pin 39 of J2 to the switched terminal of POWER switch S8 and pin 40 to pin L of instrument connector J1 The interconnecting cable must be wired as shown in table 3-1

3-1

-

JS )foOHZ

J(

SR - 400

cJl pz

INSTRUt1EAJT ~I---------JYMCHRO OR REllI~ roNAlECro~ RESOLVER OUTPUT

I---------REF INPUT INTeuroRCONAlECTlN(J CA13LE ___

DBA-488 NS TRUI-feNT INrEliRIICE CONNECTOR

PI

DJ3A- 4BB

STANOARD HATNy COAlNeCTOR IEEEshyBUS

Figure 3-1_ DBA-488-SR400 Connection Diagram

3-2

SECTION 3

DATA BUS ADAPTER DBA-488-SR400

31 EQUIPMENT SUPPLlED

311 DBA-488 ORDERED WITH SR-400

When the DBA-488 is ordered together with an SR-400 SynchroResolver Simulator the DBA-488 is bracket mounted at the rear of the SR-400 and both units are elecshytrically intercOIlllected through a cable (See figure 3-1) AC power is applied to the DBA-488 when the SR-400 is turned on The only component not supplied is the standard mating connector to the IEEE bus

31 2 DBA-488 ORDERED SEPARATE LY

When a DBA-488 is ordered separately (for retrofit to an SR-400) a mating conshynector for the instrument interface is supplied but is not wired The standard mating connector for the IEEE bus is not supplied Mounting hardware is included as required

The DBA-488 is not equipped with a power switch Line voltage (115 volts at 60 Hz) is applied via the instrument interface connector If the SR-400 front panel POWER switch is to controi the DBA-488 this switch must be wired to pins on the instrument This requires a modification to the SR-400 as shown in table 3-1

NOTE

The DBA-488 may be ordered for operation from 220 volts 5060 Hz

32 UNPACKING

Carefully remove the equipment from the packaging material and inspect for possible damage Should any unit show signs of damage notify the nearest ILC Data Device Corporation field representative immediately

33 INTERCONNECTIONS

Table 3-1 shows the interconnections between the DBA-488 and SR-400 and indicates the function of each lead For SR-400 units being retrofitted switched AC line voltage (115 volts) may be wired to pins 39 and 40 of instrument connector J2 Conshynect pin 39 of J2 to the switched terminal of POWER switch S8 and pin 40 to pin L of instrument connector J1 The interconnecting cable must be wired as shown in table 3-1

3-1

-

JS )foOHZ

J(

SR - 400

cJl pz

INSTRUt1EAJT ~I---------JYMCHRO OR REllI~ roNAlECro~ RESOLVER OUTPUT

I---------REF INPUT INTeuroRCONAlECTlN(J CA13LE ___

DBA-488 NS TRUI-feNT INrEliRIICE CONNECTOR

PI

DJ3A- 4BB

STANOARD HATNy COAlNeCTOR IEEEshyBUS

Figure 3-1_ DBA-488-SR400 Connection Diagram

3-2

-

JS )foOHZ

J(

SR - 400

cJl pz

INSTRUt1EAJT ~I---------JYMCHRO OR REllI~ roNAlECro~ RESOLVER OUTPUT

I---------REF INPUT INTeuroRCONAlECTlN(J CA13LE ___

DBA-488 NS TRUI-feNT INrEliRIICE CONNECTOR

PI

DJ3A- 4BB

STANOARD HATNy COAlNeCTOR IEEEshyBUS

Figure 3-1_ DBA-488-SR400 Connection Diagram

3-2

34 SETTING THE PRIMARY DEVICE ADDRESS

The five lBBs of the eight ADR SELECT switches on the DBA-488 determine the device address Set these switches to the required bus address lBB to MSB as marked before applying power

35 OPERATING PROCEDURE

Once the SR-400 is connected as shown in figure 3-1 it is only necessary to depress the REMOTE pushbutton and the POWER switch on the SR-400 front panel The SR-400 resolver or synchro output should track the digital input angle applied from the IEEE bus via the DBA-488 The LED display will indicate the angular values To turn off both the SR-400 and DBA-488 depress the POWER pushbutton on the SR-400

36 COMMAND CODES

When operating from the IEEE bus the SR-400 is controlled by bus commands apshyplied via the DBA-488 Table 3-2 lists the codes applicable to the SR-400 Each command is ASCII encoded and applied to the DBA-488 via the bus data lines When addressed to listen the unit responds to the commands

37 CONTROL WORD OR DAT A COMMAND SEQUENCE (LISTEN)

Figure 3-2 depicts the operations that occur when the bus controller transmits controi words or data to the DBA-488-SR400

a Controller sets ATN (Attention) Une to true

b Controller transmits SR-400 listen address (MLA) on the data lines When controi words are to be transmitted the lBB is set true when data is to be transferred the lBB is set false

c Controller returns ATN to false

d Controller (or device activated by controller) transmits ASCII encoded controi words or data on the data lines

e Controller (or other device) signals end of transmission by transmitting an ASCII carriage returnline feed on the data lines or by setting EOI line to true with the last data byte

f Controller sets ATN line to true

g Controller transmits an Unlisten command on the data lines

3-3

TABLE 3-1

DBA-488 TO SR-400 CONNECTIONS

DBA-488 INSTRUMENT INTERFACE CONNECTOR FUNCTION

1 Reset

2 Internal Connection

3 Internal Connection

4 Internal Connection

5 Internal Connection

6 100deg

7 200deg

8 Internal Connection

9 Internal Connection

10 8deg

11 40

12 2deg

13 1deg

14 08deg

15 04deg

16 02deg

17 01deg

18 Internal Connection

19 Internal Connection

20 SynchroRes Select

21 Strobe

22 Lamp Test

23 Internal Connection

24 Input Level Control 2

INSTRUMENT REAR CONNECTOR

33

17

30

47

13

29

46

12

28

45

1

6

26

42

1

~

3-4

TABLE 3-1 (CONTD)

DBA-488 TO SR-400 CONNECTIONS

DBA-488 INSTRUMENT INSTRUMENT REAR INTERFACE CONNECTOR FUNCTION CONNECTOR

25 Input Level ControI 1 41

26 80deg 50

27 40deg 16

28 20deg 32

29 10deg 49

30 8deg 15

31 4deg 31

32 2deg 48

33 1deg 14

34 Gnd 9

35 Gnd 9

36 Power Hi 39

37 Power Lo 40

38-50 SpLre

Switched AC line voltage may be wired to these pins from the power switch on the instrument front panel

38 MAINTENANCE

Maintenance of the SR-400 is described in the associated DDC instruction manual Maintenance of the DBA-488 in the field is limited since its operations occur under controI of the IEEE bus controller and the internaI stored program Check that the self contained power supply (T1 CR1A YR1 and CII through C13) is delivering +5volts

39 DBA-488 PARTS IJST

All DBA-488 parts are listed in table 3-3 Each part is identified by reference designation part number description and manufacturer Location of parts on the printed circuit board is shown in figure 3-3

3-5

Command Code

p

1

2

9

S

R

I

F

T

D

TABLE 3-2

COMMAND CODE FUNCTIONS -Functlon

Preset SR-400 output to 26V L-L

Set output to 11 SV L- L

Set output to 26V L- L

Set output to 90V L- L

Select synchro outIAlt

Select resolver output

Inhibit converter traclting

Enable converter tracking of data input

Test lamps

Set display to read data

I I

3-6

--

ATN=~

CONTROL WORDS OR DATA

EOI=l ANDOR CARRIAGE

RN

ATN=l

Controller set s ATN (Attention) line to true

Controller transmits device listen address on the data lines For the SR-400 (SR-460) the LSB is set either to true to indicate that controI words will be sent or to false to indicate that a data word will be sent

Controller returns ATN line to false

Controller (or another device activated by the controller) transmits ACCII encoded controI words or data on the data lines

Controller or other device signals end of transmission by setting EOI (End or Identify) line to true during the last word or command or by transmitting a Carriage Return after the last word command

Controller sets ATN line to true

Controller transmits a UNL (unIisten) command on the data lines

Controller returns ATN line to false

Figure 3-2 Listen Command Sequence Flow Chart

3-7 Revised 15 December 1981

SR-400DBA-4aa PROGRAMMING

ADDRESS SWITCH SETTING S8 S7 S6 S5 S4 S2 SI

DONT LISTEN WILL LISTEN CARE S ADDRESS REGARDLESS

OF POSITION

TO SEND COMMANDS EXAMPLE S = SYNCHRO R = RESOLVE~ (SYNCHRO 118V) l = 118V 2 = 26V 9 = 90V LINE TO LINB

P = PRESET (SYNCHRO 26V LINE TO LINE)

ASSERTED CONTROL LINES DATA BUS INFORMATION

DIOa DI07 DI06 DI05 DI04 DI03 DI02 DIOl ATN (MY LISTEN ADDRESS) O O l S5 S4 S3 S2 O -- (SEliDING ASCII-S=SYNCHRO) O l O l O O l l

EOI (SENDING ASCII-l= 118V AND TERMINATING) O O l l O O O l

ATN (UNLISTEN) O O l l l l l l

OR CR (CARRIAGE RETURN) O O O O l l O l

LF (LINE FEED) O O O O l O l O

EXAMPLE SENDING ANGLE 34215 DEGREES ~

DI08 DI07 DI06 DI05 DI04 DI03 DI02 DIOl

ATN (MLA ) O O l S5 S4 S3 S2 O

(SEND DATA) ~

MSB FIRS~~ ETC

3 (100) O O l l O O l l

4 (10) O O l l O l O O

2 ( l) O O l l O O l O

l (01) O O l l O O O l

5 (OCll) O O l l O l O l

CR O O O O l l O l

LF O O O O l O l O

ATN (UNLISTEN) O O l l l l l l

NOTE LSB POSITION IS O TO SEND DATA l TO SEND COMMANDS

3-7A Addendum 15 December 1981

TABLE 3-3

DBA-488 PARTS IJST

Ref Part Desig No Descri2tion

Cl-C6 C14 VK33 Capacitor 01 uf 20

C7 VK33 Capacitor 047 uf 10

C8 C12 C13 VK33 Capacitor 01 uf 20

C9 ClO VK23 Capacitor 27 pf 10

Cll 39D Capacitor 8000 uf l5V

CRAl VH-148 Rectifier bridge

CRl lN4l48 Diode

Jl 205869-1 Connector

Rl-R3R7shyR9 RCR07 Resistor 22K 14W 5

R4 RCR07 Resistor llOK 14W 5

R5R6 RCR07 Resistor 5lK 14W 5

SI 76PB08 Switch Dip

Tl LP16-700 Transformer

Ul-U4 MC 3448AP Bus Transceiver

U5 MC68488P lnterface Controller

U6 MC6802P Microprocessor

U7 U8 70L97N Tri-State Buffer

U9 lM6604lJG Read Only Memory

UlO Ull MC682lP Peripheral lnterface Adapter

U12 7404 lnverter Driver

VRl UA7805 Voltage Regulator

Yl SCM-18(4MHz) Crystal

C22933 Printed Circuit Board

C22934 Printed Circuit Board Assy

Specify C22934 for SR-400 or SR-460

Revised 983 3-8

Manufacturer

Sprague

Varo

Amp

Grayhill

Signal

Motorola

Motorola

Motorola

National

lntersil

Motorola

Texas Instrument

Fairchild

Sentry

DDC

DDC

bull bull

~

I I I -[ I

51~~ - -0lt -o~ oj 1 II l --- I~ JI~ VCY ~ PUOD OD [J M

UIO lU ll I I

[u3 UIZq IR3

us USI l I ~ C7 C6

RS el ~ ~apoD~~ D TPI O I ~ g elgJD C9

R8

R7 ClO

I lt

U6 I l ISshyCamp

~ D bull

R5 --c=r- O Tt

ltO 2R CRII I

8 4

= C I F= 7 3

1 l CJ (13 ~~ ~

Figure 3-3 DBA-488 Location of Parts

3-9

• DDC-1pdf
• Framsida
• DDC-A3
• Baksida

TABLE 3-1

DBA-488 TO SR-400 CONNECTIONS

DBA-488 INSTRUMENT INTERFACE CONNECTOR FUNCTION

1 Reset

2 Internal Connection

3 Internal Connection

4 Internal Connection

5 Internal Connection

6 100deg

7 200deg

8 Internal Connection

9 Internal Connection

10 8deg

11 40

12 2deg

13 1deg

14 08deg

15 04deg

16 02deg

17 01deg

18 Internal Connection

19 Internal Connection

20 SynchroRes Select

21 Strobe

22 Lamp Test

23 Internal Connection

24 Input Level Control 2

INSTRUMENT REAR CONNECTOR

33

17

30

47

13

29

46

12

28

45

1

6

26

42

1

~

3-4

TABLE 3-1 (CONTD)

DBA-488 TO SR-400 CONNECTIONS

DBA-488 INSTRUMENT INSTRUMENT REAR INTERFACE CONNECTOR FUNCTION CONNECTOR

25 Input Level ControI 1 41

26 80deg 50

27 40deg 16

28 20deg 32

29 10deg 49

30 8deg 15

31 4deg 31

32 2deg 48

33 1deg 14

34 Gnd 9

35 Gnd 9

36 Power Hi 39

37 Power Lo 40

38-50 SpLre

Switched AC line voltage may be wired to these pins from the power switch on the instrument front panel

38 MAINTENANCE

Maintenance of the SR-400 is described in the associated DDC instruction manual Maintenance of the DBA-488 in the field is limited since its operations occur under controI of the IEEE bus controller and the internaI stored program Check that the self contained power supply (T1 CR1A YR1 and CII through C13) is delivering +5volts

39 DBA-488 PARTS IJST

All DBA-488 parts are listed in table 3-3 Each part is identified by reference designation part number description and manufacturer Location of parts on the printed circuit board is shown in figure 3-3

3-5

Command Code

p

1

2

9

S

R

I

F

T

D

TABLE 3-2

COMMAND CODE FUNCTIONS -Functlon

Preset SR-400 output to 26V L-L

Set output to 11 SV L- L

Set output to 26V L- L

Set output to 90V L- L

Select synchro outIAlt

Select resolver output

Inhibit converter traclting

Enable converter tracking of data input

Test lamps

Set display to read data

I I

3-6

--

ATN=~

CONTROL WORDS OR DATA

EOI=l ANDOR CARRIAGE

RN

ATN=l

Controller set s ATN (Attention) line to true

Controller transmits device listen address on the data lines For the SR-400 (SR-460) the LSB is set either to true to indicate that controI words will be sent or to false to indicate that a data word will be sent

Controller returns ATN line to false

Controller (or another device activated by the controller) transmits ACCII encoded controI words or data on the data lines

Controller or other device signals end of transmission by setting EOI (End or Identify) line to true during the last word or command or by transmitting a Carriage Return after the last word command

Controller sets ATN line to true

Controller transmits a UNL (unIisten) command on the data lines

Controller returns ATN line to false

Figure 3-2 Listen Command Sequence Flow Chart

3-7 Revised 15 December 1981

SR-400DBA-4aa PROGRAMMING

ADDRESS SWITCH SETTING S8 S7 S6 S5 S4 S2 SI

DONT LISTEN WILL LISTEN CARE S ADDRESS REGARDLESS

OF POSITION

TO SEND COMMANDS EXAMPLE S = SYNCHRO R = RESOLVE~ (SYNCHRO 118V) l = 118V 2 = 26V 9 = 90V LINE TO LINB

P = PRESET (SYNCHRO 26V LINE TO LINE)

ASSERTED CONTROL LINES DATA BUS INFORMATION

DIOa DI07 DI06 DI05 DI04 DI03 DI02 DIOl ATN (MY LISTEN ADDRESS) O O l S5 S4 S3 S2 O -- (SEliDING ASCII-S=SYNCHRO) O l O l O O l l

EOI (SENDING ASCII-l= 118V AND TERMINATING) O O l l O O O l

ATN (UNLISTEN) O O l l l l l l

OR CR (CARRIAGE RETURN) O O O O l l O l

LF (LINE FEED) O O O O l O l O

EXAMPLE SENDING ANGLE 34215 DEGREES ~

DI08 DI07 DI06 DI05 DI04 DI03 DI02 DIOl

ATN (MLA ) O O l S5 S4 S3 S2 O

(SEND DATA) ~

MSB FIRS~~ ETC

3 (100) O O l l O O l l

4 (10) O O l l O l O O

2 ( l) O O l l O O l O

l (01) O O l l O O O l

5 (OCll) O O l l O l O l

CR O O O O l l O l

LF O O O O l O l O

ATN (UNLISTEN) O O l l l l l l

NOTE LSB POSITION IS O TO SEND DATA l TO SEND COMMANDS

3-7A Addendum 15 December 1981

TABLE 3-3

DBA-488 PARTS IJST

Ref Part Desig No Descri2tion

Cl-C6 C14 VK33 Capacitor 01 uf 20

C7 VK33 Capacitor 047 uf 10

C8 C12 C13 VK33 Capacitor 01 uf 20

C9 ClO VK23 Capacitor 27 pf 10

Cll 39D Capacitor 8000 uf l5V

CRAl VH-148 Rectifier bridge

CRl lN4l48 Diode

Jl 205869-1 Connector

Rl-R3R7shyR9 RCR07 Resistor 22K 14W 5

R4 RCR07 Resistor llOK 14W 5

R5R6 RCR07 Resistor 5lK 14W 5

SI 76PB08 Switch Dip

Tl LP16-700 Transformer

Ul-U4 MC 3448AP Bus Transceiver

U5 MC68488P lnterface Controller

U6 MC6802P Microprocessor

U7 U8 70L97N Tri-State Buffer

U9 lM6604lJG Read Only Memory

UlO Ull MC682lP Peripheral lnterface Adapter

U12 7404 lnverter Driver

VRl UA7805 Voltage Regulator

Yl SCM-18(4MHz) Crystal

C22933 Printed Circuit Board

C22934 Printed Circuit Board Assy

Specify C22934 for SR-400 or SR-460

Revised 983 3-8

Manufacturer

Sprague

Varo

Amp

Grayhill

Signal

Motorola

Motorola

Motorola

National

lntersil

Motorola

Texas Instrument

Fairchild

Sentry

DDC

DDC

bull bull

~

I I I -[ I

51~~ - -0lt -o~ oj 1 II l --- I~ JI~ VCY ~ PUOD OD [J M

UIO lU ll I I

[u3 UIZq IR3

us USI l I ~ C7 C6

RS el ~ ~apoD~~ D TPI O I ~ g elgJD C9

R8

R7 ClO

I lt

U6 I l ISshyCamp

~ D bull

R5 --c=r- O Tt

ltO 2R CRII I

8 4

= C I F= 7 3

1 l CJ (13 ~~ ~

Figure 3-3 DBA-488 Location of Parts

3-9

• DDC-1pdf
• Framsida
• DDC-A3
• Baksida

TABLE 3-1 (CONTD)

DBA-488 TO SR-400 CONNECTIONS

DBA-488 INSTRUMENT INSTRUMENT REAR INTERFACE CONNECTOR FUNCTION CONNECTOR

25 Input Level ControI 1 41

26 80deg 50

27 40deg 16

28 20deg 32

29 10deg 49

30 8deg 15

31 4deg 31

32 2deg 48

33 1deg 14

34 Gnd 9

35 Gnd 9

36 Power Hi 39

37 Power Lo 40

38-50 SpLre

Switched AC line voltage may be wired to these pins from the power switch on the instrument front panel

38 MAINTENANCE

Maintenance of the SR-400 is described in the associated DDC instruction manual Maintenance of the DBA-488 in the field is limited since its operations occur under controI of the IEEE bus controller and the internaI stored program Check that the self contained power supply (T1 CR1A YR1 and CII through C13) is delivering +5volts

39 DBA-488 PARTS IJST

All DBA-488 parts are listed in table 3-3 Each part is identified by reference designation part number description and manufacturer Location of parts on the printed circuit board is shown in figure 3-3

3-5

Command Code

p

1

2

9

S

R

I

F

T

D

TABLE 3-2

COMMAND CODE FUNCTIONS -Functlon

Preset SR-400 output to 26V L-L

Set output to 11 SV L- L

Set output to 26V L- L

Set output to 90V L- L

Select synchro outIAlt

Select resolver output

Inhibit converter traclting

Enable converter tracking of data input

Test lamps

Set display to read data

I I

3-6

--

ATN=~

CONTROL WORDS OR DATA

EOI=l ANDOR CARRIAGE

RN

ATN=l

Controller set s ATN (Attention) line to true

Controller transmits device listen address on the data lines For the SR-400 (SR-460) the LSB is set either to true to indicate that controI words will be sent or to false to indicate that a data word will be sent

Controller returns ATN line to false

Controller (or another device activated by the controller) transmits ACCII encoded controI words or data on the data lines

Controller or other device signals end of transmission by setting EOI (End or Identify) line to true during the last word or command or by transmitting a Carriage Return after the last word command

Controller sets ATN line to true

Controller transmits a UNL (unIisten) command on the data lines

Controller returns ATN line to false

Figure 3-2 Listen Command Sequence Flow Chart

3-7 Revised 15 December 1981

SR-400DBA-4aa PROGRAMMING

ADDRESS SWITCH SETTING S8 S7 S6 S5 S4 S2 SI

DONT LISTEN WILL LISTEN CARE S ADDRESS REGARDLESS

OF POSITION

TO SEND COMMANDS EXAMPLE S = SYNCHRO R = RESOLVE~ (SYNCHRO 118V) l = 118V 2 = 26V 9 = 90V LINE TO LINB

P = PRESET (SYNCHRO 26V LINE TO LINE)

ASSERTED CONTROL LINES DATA BUS INFORMATION

DIOa DI07 DI06 DI05 DI04 DI03 DI02 DIOl ATN (MY LISTEN ADDRESS) O O l S5 S4 S3 S2 O -- (SEliDING ASCII-S=SYNCHRO) O l O l O O l l

EOI (SENDING ASCII-l= 118V AND TERMINATING) O O l l O O O l

ATN (UNLISTEN) O O l l l l l l

OR CR (CARRIAGE RETURN) O O O O l l O l

LF (LINE FEED) O O O O l O l O

EXAMPLE SENDING ANGLE 34215 DEGREES ~

DI08 DI07 DI06 DI05 DI04 DI03 DI02 DIOl

ATN (MLA ) O O l S5 S4 S3 S2 O

(SEND DATA) ~

MSB FIRS~~ ETC

3 (100) O O l l O O l l

4 (10) O O l l O l O O

2 ( l) O O l l O O l O

l (01) O O l l O O O l

5 (OCll) O O l l O l O l

CR O O O O l l O l

LF O O O O l O l O

ATN (UNLISTEN) O O l l l l l l

NOTE LSB POSITION IS O TO SEND DATA l TO SEND COMMANDS

3-7A Addendum 15 December 1981

TABLE 3-3

DBA-488 PARTS IJST

Ref Part Desig No Descri2tion

Cl-C6 C14 VK33 Capacitor 01 uf 20

C7 VK33 Capacitor 047 uf 10

C8 C12 C13 VK33 Capacitor 01 uf 20

C9 ClO VK23 Capacitor 27 pf 10

Cll 39D Capacitor 8000 uf l5V

CRAl VH-148 Rectifier bridge

CRl lN4l48 Diode

Jl 205869-1 Connector

Rl-R3R7shyR9 RCR07 Resistor 22K 14W 5

R4 RCR07 Resistor llOK 14W 5

R5R6 RCR07 Resistor 5lK 14W 5

SI 76PB08 Switch Dip

Tl LP16-700 Transformer

Ul-U4 MC 3448AP Bus Transceiver

U5 MC68488P lnterface Controller

U6 MC6802P Microprocessor

U7 U8 70L97N Tri-State Buffer

U9 lM6604lJG Read Only Memory

UlO Ull MC682lP Peripheral lnterface Adapter

U12 7404 lnverter Driver

VRl UA7805 Voltage Regulator

Yl SCM-18(4MHz) Crystal

C22933 Printed Circuit Board

C22934 Printed Circuit Board Assy

Specify C22934 for SR-400 or SR-460

Revised 983 3-8

Manufacturer

Sprague

Varo

Amp

Grayhill

Signal

Motorola

Motorola

Motorola

National

lntersil

Motorola

Texas Instrument

Fairchild

Sentry

DDC

DDC

bull bull

~

I I I -[ I

51~~ - -0lt -o~ oj 1 II l --- I~ JI~ VCY ~ PUOD OD [J M

UIO lU ll I I

[u3 UIZq IR3

us USI l I ~ C7 C6

RS el ~ ~apoD~~ D TPI O I ~ g elgJD C9

R8

R7 ClO

I lt

U6 I l ISshyCamp

~ D bull

R5 --c=r- O Tt

ltO 2R CRII I

8 4

= C I F= 7 3

1 l CJ (13 ~~ ~

Figure 3-3 DBA-488 Location of Parts

3-9

• DDC-1pdf
• Framsida
• DDC-A3
• Baksida

Command Code

p

1

2

9

S

R

I

F

T

D

TABLE 3-2

COMMAND CODE FUNCTIONS -Functlon

Preset SR-400 output to 26V L-L

Set output to 11 SV L- L

Set output to 26V L- L

Set output to 90V L- L

Select synchro outIAlt

Select resolver output

Inhibit converter traclting

Enable converter tracking of data input

Test lamps

Set display to read data

I I

3-6

--

ATN=~

CONTROL WORDS OR DATA

EOI=l ANDOR CARRIAGE

RN

ATN=l

Controller set s ATN (Attention) line to true

Controller transmits device listen address on the data lines For the SR-400 (SR-460) the LSB is set either to true to indicate that controI words will be sent or to false to indicate that a data word will be sent

Controller returns ATN line to false

Controller (or another device activated by the controller) transmits ACCII encoded controI words or data on the data lines

Controller or other device signals end of transmission by setting EOI (End or Identify) line to true during the last word or command or by transmitting a Carriage Return after the last word command

Controller sets ATN line to true

Controller transmits a UNL (unIisten) command on the data lines

Controller returns ATN line to false

Figure 3-2 Listen Command Sequence Flow Chart

3-7 Revised 15 December 1981

SR-400DBA-4aa PROGRAMMING

ADDRESS SWITCH SETTING S8 S7 S6 S5 S4 S2 SI

DONT LISTEN WILL LISTEN CARE S ADDRESS REGARDLESS

OF POSITION

TO SEND COMMANDS EXAMPLE S = SYNCHRO R = RESOLVE~ (SYNCHRO 118V) l = 118V 2 = 26V 9 = 90V LINE TO LINB

P = PRESET (SYNCHRO 26V LINE TO LINE)

ASSERTED CONTROL LINES DATA BUS INFORMATION

DIOa DI07 DI06 DI05 DI04 DI03 DI02 DIOl ATN (MY LISTEN ADDRESS) O O l S5 S4 S3 S2 O -- (SEliDING ASCII-S=SYNCHRO) O l O l O O l l

EOI (SENDING ASCII-l= 118V AND TERMINATING) O O l l O O O l

ATN (UNLISTEN) O O l l l l l l

OR CR (CARRIAGE RETURN) O O O O l l O l

LF (LINE FEED) O O O O l O l O

EXAMPLE SENDING ANGLE 34215 DEGREES ~

DI08 DI07 DI06 DI05 DI04 DI03 DI02 DIOl

ATN (MLA ) O O l S5 S4 S3 S2 O

(SEND DATA) ~

MSB FIRS~~ ETC

3 (100) O O l l O O l l

4 (10) O O l l O l O O

2 ( l) O O l l O O l O

l (01) O O l l O O O l

5 (OCll) O O l l O l O l

CR O O O O l l O l

LF O O O O l O l O

ATN (UNLISTEN) O O l l l l l l

NOTE LSB POSITION IS O TO SEND DATA l TO SEND COMMANDS

3-7A Addendum 15 December 1981

TABLE 3-3

DBA-488 PARTS IJST

Ref Part Desig No Descri2tion

Cl-C6 C14 VK33 Capacitor 01 uf 20

C7 VK33 Capacitor 047 uf 10

C8 C12 C13 VK33 Capacitor 01 uf 20

C9 ClO VK23 Capacitor 27 pf 10

Cll 39D Capacitor 8000 uf l5V

CRAl VH-148 Rectifier bridge

CRl lN4l48 Diode

Jl 205869-1 Connector

Rl-R3R7shyR9 RCR07 Resistor 22K 14W 5

R4 RCR07 Resistor llOK 14W 5

R5R6 RCR07 Resistor 5lK 14W 5

SI 76PB08 Switch Dip

Tl LP16-700 Transformer

Ul-U4 MC 3448AP Bus Transceiver

U5 MC68488P lnterface Controller

U6 MC6802P Microprocessor

U7 U8 70L97N Tri-State Buffer

U9 lM6604lJG Read Only Memory

UlO Ull MC682lP Peripheral lnterface Adapter

U12 7404 lnverter Driver

VRl UA7805 Voltage Regulator

Yl SCM-18(4MHz) Crystal

C22933 Printed Circuit Board

C22934 Printed Circuit Board Assy

Specify C22934 for SR-400 or SR-460

Revised 983 3-8

Manufacturer

Sprague

Varo

Amp

Grayhill

Signal

Motorola

Motorola

Motorola

National

lntersil

Motorola

Texas Instrument

Fairchild

Sentry

DDC

DDC

bull bull

~

I I I -[ I

51~~ - -0lt -o~ oj 1 II l --- I~ JI~ VCY ~ PUOD OD [J M

UIO lU ll I I

[u3 UIZq IR3

us USI l I ~ C7 C6

RS el ~ ~apoD~~ D TPI O I ~ g elgJD C9

R8

R7 ClO

I lt

U6 I l ISshyCamp

~ D bull

R5 --c=r- O Tt

ltO 2R CRII I

8 4

= C I F= 7 3

1 l CJ (13 ~~ ~

Figure 3-3 DBA-488 Location of Parts

3-9

• DDC-1pdf
• Framsida
• DDC-A3
• Baksida

--

ATN=~

CONTROL WORDS OR DATA

EOI=l ANDOR CARRIAGE

RN

ATN=l

Controller set s ATN (Attention) line to true

Controller transmits device listen address on the data lines For the SR-400 (SR-460) the LSB is set either to true to indicate that controI words will be sent or to false to indicate that a data word will be sent

Controller returns ATN line to false

Controller (or another device activated by the controller) transmits ACCII encoded controI words or data on the data lines

Controller or other device signals end of transmission by setting EOI (End or Identify) line to true during the last word or command or by transmitting a Carriage Return after the last word command

Controller sets ATN line to true

Controller transmits a UNL (unIisten) command on the data lines

Controller returns ATN line to false

Figure 3-2 Listen Command Sequence Flow Chart

3-7 Revised 15 December 1981

SR-400DBA-4aa PROGRAMMING

ADDRESS SWITCH SETTING S8 S7 S6 S5 S4 S2 SI

DONT LISTEN WILL LISTEN CARE S ADDRESS REGARDLESS

OF POSITION

TO SEND COMMANDS EXAMPLE S = SYNCHRO R = RESOLVE~ (SYNCHRO 118V) l = 118V 2 = 26V 9 = 90V LINE TO LINB

P = PRESET (SYNCHRO 26V LINE TO LINE)

ASSERTED CONTROL LINES DATA BUS INFORMATION

DIOa DI07 DI06 DI05 DI04 DI03 DI02 DIOl ATN (MY LISTEN ADDRESS) O O l S5 S4 S3 S2 O -- (SEliDING ASCII-S=SYNCHRO) O l O l O O l l

EOI (SENDING ASCII-l= 118V AND TERMINATING) O O l l O O O l

ATN (UNLISTEN) O O l l l l l l

OR CR (CARRIAGE RETURN) O O O O l l O l

LF (LINE FEED) O O O O l O l O

EXAMPLE SENDING ANGLE 34215 DEGREES ~

DI08 DI07 DI06 DI05 DI04 DI03 DI02 DIOl

ATN (MLA ) O O l S5 S4 S3 S2 O

(SEND DATA) ~

MSB FIRS~~ ETC

3 (100) O O l l O O l l

4 (10) O O l l O l O O

2 ( l) O O l l O O l O

l (01) O O l l O O O l

5 (OCll) O O l l O l O l

CR O O O O l l O l

LF O O O O l O l O

ATN (UNLISTEN) O O l l l l l l

NOTE LSB POSITION IS O TO SEND DATA l TO SEND COMMANDS

3-7A Addendum 15 December 1981

TABLE 3-3

DBA-488 PARTS IJST

Ref Part Desig No Descri2tion

Cl-C6 C14 VK33 Capacitor 01 uf 20

C7 VK33 Capacitor 047 uf 10

C8 C12 C13 VK33 Capacitor 01 uf 20

C9 ClO VK23 Capacitor 27 pf 10

Cll 39D Capacitor 8000 uf l5V

CRAl VH-148 Rectifier bridge

CRl lN4l48 Diode

Jl 205869-1 Connector

Rl-R3R7shyR9 RCR07 Resistor 22K 14W 5

R4 RCR07 Resistor llOK 14W 5

R5R6 RCR07 Resistor 5lK 14W 5

SI 76PB08 Switch Dip

Tl LP16-700 Transformer

Ul-U4 MC 3448AP Bus Transceiver

U5 MC68488P lnterface Controller

U6 MC6802P Microprocessor

U7 U8 70L97N Tri-State Buffer

U9 lM6604lJG Read Only Memory

UlO Ull MC682lP Peripheral lnterface Adapter

U12 7404 lnverter Driver

VRl UA7805 Voltage Regulator

Yl SCM-18(4MHz) Crystal

C22933 Printed Circuit Board

C22934 Printed Circuit Board Assy

Specify C22934 for SR-400 or SR-460

Revised 983 3-8

Manufacturer

Sprague

Varo

Amp

Grayhill

Signal

Motorola

Motorola

Motorola

National

lntersil

Motorola

Texas Instrument

Fairchild

Sentry

DDC

DDC

bull bull

~

I I I -[ I

51~~ - -0lt -o~ oj 1 II l --- I~ JI~ VCY ~ PUOD OD [J M

UIO lU ll I I

[u3 UIZq IR3

us USI l I ~ C7 C6

RS el ~ ~apoD~~ D TPI O I ~ g elgJD C9

R8

R7 ClO

I lt

U6 I l ISshyCamp

~ D bull

R5 --c=r- O Tt

ltO 2R CRII I

8 4

= C I F= 7 3

1 l CJ (13 ~~ ~

Figure 3-3 DBA-488 Location of Parts

3-9

• DDC-1pdf
• Framsida
• DDC-A3
• Baksida

SR-400DBA-4aa PROGRAMMING

ADDRESS SWITCH SETTING S8 S7 S6 S5 S4 S2 SI

DONT LISTEN WILL LISTEN CARE S ADDRESS REGARDLESS

OF POSITION

TO SEND COMMANDS EXAMPLE S = SYNCHRO R = RESOLVE~ (SYNCHRO 118V) l = 118V 2 = 26V 9 = 90V LINE TO LINB

P = PRESET (SYNCHRO 26V LINE TO LINE)

ASSERTED CONTROL LINES DATA BUS INFORMATION

DIOa DI07 DI06 DI05 DI04 DI03 DI02 DIOl ATN (MY LISTEN ADDRESS) O O l S5 S4 S3 S2 O -- (SEliDING ASCII-S=SYNCHRO) O l O l O O l l

EOI (SENDING ASCII-l= 118V AND TERMINATING) O O l l O O O l

ATN (UNLISTEN) O O l l l l l l

OR CR (CARRIAGE RETURN) O O O O l l O l

LF (LINE FEED) O O O O l O l O

EXAMPLE SENDING ANGLE 34215 DEGREES ~

DI08 DI07 DI06 DI05 DI04 DI03 DI02 DIOl

ATN (MLA ) O O l S5 S4 S3 S2 O

(SEND DATA) ~

MSB FIRS~~ ETC

3 (100) O O l l O O l l

4 (10) O O l l O l O O

2 ( l) O O l l O O l O

l (01) O O l l O O O l

5 (OCll) O O l l O l O l

CR O O O O l l O l

LF O O O O l O l O

ATN (UNLISTEN) O O l l l l l l

NOTE LSB POSITION IS O TO SEND DATA l TO SEND COMMANDS

3-7A Addendum 15 December 1981

TABLE 3-3

DBA-488 PARTS IJST

Ref Part Desig No Descri2tion

Cl-C6 C14 VK33 Capacitor 01 uf 20

C7 VK33 Capacitor 047 uf 10

C8 C12 C13 VK33 Capacitor 01 uf 20

C9 ClO VK23 Capacitor 27 pf 10

Cll 39D Capacitor 8000 uf l5V

CRAl VH-148 Rectifier bridge

CRl lN4l48 Diode

Jl 205869-1 Connector

Rl-R3R7shyR9 RCR07 Resistor 22K 14W 5

R4 RCR07 Resistor llOK 14W 5

R5R6 RCR07 Resistor 5lK 14W 5

SI 76PB08 Switch Dip

Tl LP16-700 Transformer

Ul-U4 MC 3448AP Bus Transceiver

U5 MC68488P lnterface Controller

U6 MC6802P Microprocessor

U7 U8 70L97N Tri-State Buffer

U9 lM6604lJG Read Only Memory

UlO Ull MC682lP Peripheral lnterface Adapter

U12 7404 lnverter Driver

VRl UA7805 Voltage Regulator

Yl SCM-18(4MHz) Crystal

C22933 Printed Circuit Board

C22934 Printed Circuit Board Assy

Specify C22934 for SR-400 or SR-460

Revised 983 3-8

Manufacturer

Sprague

Varo

Amp

Grayhill

Signal

Motorola

Motorola

Motorola

National

lntersil

Motorola

Texas Instrument

Fairchild

Sentry

DDC

DDC

bull bull

~

I I I -[ I

51~~ - -0lt -o~ oj 1 II l --- I~ JI~ VCY ~ PUOD OD [J M

UIO lU ll I I

[u3 UIZq IR3

us USI l I ~ C7 C6

RS el ~ ~apoD~~ D TPI O I ~ g elgJD C9

R8

R7 ClO

I lt

U6 I l ISshyCamp

~ D bull

R5 --c=r- O Tt

ltO 2R CRII I

8 4

= C I F= 7 3

1 l CJ (13 ~~ ~

Figure 3-3 DBA-488 Location of Parts

3-9

• DDC-1pdf
• Framsida
• DDC-A3
• Baksida

TABLE 3-3

DBA-488 PARTS IJST

Ref Part Desig No Descri2tion

Cl-C6 C14 VK33 Capacitor 01 uf 20

C7 VK33 Capacitor 047 uf 10

C8 C12 C13 VK33 Capacitor 01 uf 20

C9 ClO VK23 Capacitor 27 pf 10

Cll 39D Capacitor 8000 uf l5V

CRAl VH-148 Rectifier bridge

CRl lN4l48 Diode

Jl 205869-1 Connector

Rl-R3R7shyR9 RCR07 Resistor 22K 14W 5

R4 RCR07 Resistor llOK 14W 5

R5R6 RCR07 Resistor 5lK 14W 5

SI 76PB08 Switch Dip

Tl LP16-700 Transformer

Ul-U4 MC 3448AP Bus Transceiver

U5 MC68488P lnterface Controller

U6 MC6802P Microprocessor

U7 U8 70L97N Tri-State Buffer

U9 lM6604lJG Read Only Memory

UlO Ull MC682lP Peripheral lnterface Adapter

U12 7404 lnverter Driver

VRl UA7805 Voltage Regulator

Yl SCM-18(4MHz) Crystal

C22933 Printed Circuit Board

C22934 Printed Circuit Board Assy

Specify C22934 for SR-400 or SR-460

Revised 983 3-8

Manufacturer

Sprague

Varo

Amp

Grayhill

Signal

Motorola

Motorola

Motorola

National

lntersil

Motorola

Texas Instrument

Fairchild

Sentry

DDC

DDC

bull bull

~

I I I -[ I

51~~ - -0lt -o~ oj 1 II l --- I~ JI~ VCY ~ PUOD OD [J M

UIO lU ll I I

[u3 UIZq IR3

us USI l I ~ C7 C6

RS el ~ ~apoD~~ D TPI O I ~ g elgJD C9

R8

R7 ClO

I lt

U6 I l ISshyCamp

~ D bull

R5 --c=r- O Tt

ltO 2R CRII I

8 4

= C I F= 7 3

1 l CJ (13 ~~ ~

Figure 3-3 DBA-488 Location of Parts

3-9

• DDC-1pdf
• Framsida
• DDC-A3
• Baksida

bull bull

~

I I I -[ I

51~~ - -0lt -o~ oj 1 II l --- I~ JI~ VCY ~ PUOD OD [J M

UIO lU ll I I

[u3 UIZq IR3

us USI l I ~ C7 C6

RS el ~ ~apoD~~ D TPI O I ~ g elgJD C9

R8

R7 ClO

I lt

U6 I l ISshyCamp

~ D bull

R5 --c=r- O Tt

ltO 2R CRII I

8 4

= C I F= 7 3

1 l CJ (13 ~~ ~

Figure 3-3 DBA-488 Location of Parts

3-9

• DDC-1pdf
• Framsida
• DDC-A3
• Baksida

• DDC-1pdf
• Framsida
• DDC-A3
• Baksida