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Dynamically Dynamically Reconfigurable Reconfigurable Architectures: Architectures: An OverviewAn Overview
Juanjo NogueraJuanjo Noguera
Dept. Computer Architecture (DAC-Dept. Computer Architecture (DAC-UPC)UPC)
[email protected]@ac.upc.es
2
IntroductionIntroduction Reconfigurable ComputingReconfigurable Computing
• Reconfigurable devices and systemsReconfigurable devices and systems• Reconfigurable Systems ClassificationReconfigurable Systems Classification• Reconfiguration MethodsReconfiguration Methods
Reconfigurable Instruction Set Reconfigurable Instruction Set ProcessorsProcessors• ASIP-based approachASIP-based approach• Coprocessor-based approachCoprocessor-based approach
ConclusionsConclusions
OutlineOutline
3
Reconfigurable Computing (RC) is an Reconfigurable Computing (RC) is an emerging paradigm for digital emerging paradigm for digital systems designsystems design
Technology improvements have made Technology improvements have made possible new programmable logic possible new programmable logic devices (FPGAs, CPLDs)devices (FPGAs, CPLDs)
Objective of the talkObjective of the talk: Give an : Give an overview of RC concepts and overview of RC concepts and introduce the Reconfigurable introduce the Reconfigurable Instruction Set Processors. Instruction Set Processors.
IntroductionIntroduction
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Introduction (II)Introduction (II)
RC objectives:RC objectives: Specialization, performance, Specialization, performance, flexibilityflexibility
Basic idea: “Programmable Hardware”Basic idea: “Programmable Hardware”
SpecializationSpecialization
PerformancePerformance Power Power
consumptionconsumption
FlexibilityFlexibility ProgrammingProgramming
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Introduction (III)Introduction (III)
RC comparison versus other RC comparison versus other alternativesalternatives
Application SpecificSystems
General Purpose Systems
Cost
Performance
ReconfigurableComputing
Performance
Flexibility, Power
GPP
ASIC
DSP RC
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IntroductionIntroduction Reconfigurable ComputingReconfigurable Computing
• Reconfigurable devices and systemsReconfigurable devices and systems• Reconfigurable Systems ClassificationReconfigurable Systems Classification• Reconfiguration MethodsReconfiguration Methods
Reconfigurable Instruction Set Reconfigurable Instruction Set ProcessorsProcessors• ASIP-based approachASIP-based approach• Coprocessor-based approachCoprocessor-based approach
ConclusionsConclusions
OutlineOutline
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General device architectureGeneral device architecture
Reconfigurable DevicesReconfigurable DevicesR
econ
fig
ura
ble
Com
pu
tin
g
Logic Bloc
InterconnectionStructure
I/O Bloc
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Routing strategiesRouting strategies
Reconfigurable Devices Reconfigurable Devices (II)(II)
Recon
fig
ura
ble
Com
pu
tin
g
A B
C
A B
C
Continuous Routing Structured Routing
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SRAM based devices with infinite SRAM based devices with infinite number of reconfigurationsnumber of reconfigurations
Reconfigurable Devices Reconfigurable Devices (III)(III)
Recon
fig
ura
ble
Com
pu
tin
g
Configuration Bitstream110011101 ...
• App 1 -> Bitstream 1• App 2 -> Bitstream 2
• App n -> Bitstream n
Reconfigurable Device
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Rapid System (ASIC) PrototypingRapid System (ASIC) Prototyping
Reconfigurable Systems Reconfigurable Systems (I)(I)
Recon
fig
ura
ble
Com
pu
tin
g
PLD PLDPLDCPU PLD
PLD
PLD PLD
PLD PLD
PLD
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Reconfigurable Systems Reconfigurable Systems ClassificationClassification
Reconfigurable Systems Reconfigurable Systems (II)(II)
Recon
fig
ura
ble
Com
pu
tin
g
I/O PLD RAM
PLD
CPURAM
PLD
PLD RAM
(c)
(d)
(b)
(a)
HostComputer
SYSTEM BUS
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Reconfiguration Methods Reconfiguration Methods (I)(I)
Recon
fig
ura
ble
Com
pu
tin
g Compile Time Reconfiguration (CTR)Compile Time Reconfiguration (CTR)• Device configuration is fixed during Device configuration is fixed during
application run time executionapplication run time execution
Run Time Reconfiguration (RTR)Run Time Reconfiguration (RTR)• Device configuration changes during Device configuration changes during
application run time executionapplication run time execution
RTR strategiesRTR strategies• Global RTRGlobal RTR• Partial RTRPartial RTR
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Global Run Time Reconfiguration Global Run Time Reconfiguration (Single context)(Single context)
Reconfiguration Methods Reconfiguration Methods (II)(II)
Recon
fig
ura
ble
Com
pu
tin
g
#1
#2
#3
#4
Application
#1
Reconfiguration Contexts
Dynamically Reconfigurable Device
Reconfiguration
Execution
#2
Reconfiguration
ExecutionReconfiguration
#4
Execution
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Partial Run Time Reconfiguration Partial Run Time Reconfiguration (Multiple context)(Multiple context)
Reconfiguration Methods Reconfiguration Methods (III)(III)
Recon
fig
ura
ble
Com
pu
tin
g
#1
#2
#3
#4
Aplicació
Reconfiguration Contexts
Dynamically Reconfigurable Device
#4
#1
#3
Reconfiguration
#4
#1
#2
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Run-Time Reconfiguration Run-Time Reconfiguration ChallengesChallenges• Temporal PartitioningTemporal Partitioning• Context Scheduling (static)Context Scheduling (static)
Reconfiguration Latency OverheadReconfiguration Latency Overhead• Configuration Pre-fetchingConfiguration Pre-fetching• Configuration CachingConfiguration Caching• Configuration CompressionConfiguration Compression
Reconfiguration Methods Reconfiguration Methods (IV)(IV)
Recon
fig
ura
ble
Com
pu
tin
g
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IntroductionIntroduction Reconfigurable ComputingReconfigurable Computing
• Reconfigurable devices and systemsReconfigurable devices and systems• Reconfigurable Systems ClassificationReconfigurable Systems Classification• Reconfiguration MethodsReconfiguration Methods
Reconfigurable Instruction Set Reconfigurable Instruction Set ProcessorsProcessors• ASIP-based approachASIP-based approach• Coprocessor-based approachCoprocessor-based approach
ConclusionsConclusions
OutlineOutline
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By including reconfigurability we By including reconfigurability we can increase flexibility with high can increase flexibility with high specializationspecialization
Introduction Introduction R
econ
fig
ura
ble
In
str
ucti
on
Set
Pro
cessors
Processor PLD
Reconfigurable Processor
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Coprocessor based approachCoprocessor based approach
ASIP based approachASIP based approach
Introduction (II)Introduction (II)R
econ
fig
ura
ble
In
str
ucti
on
Set
Pro
cessors
· · ·
Task 1 Task K
· · ·
Task K+1
Task N
Software Hardware
Task 1 Task 2 Task N
Software
Hardware
· · ·
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Typical example: CPU + PCI boardTypical example: CPU + PCI board• Altera ARC-PCIAltera ARC-PCI• Compaq PametteCompaq Pamette
System on Chip (SoC)System on Chip (SoC)• Altera´s Excalibur deviceAltera´s Excalibur device• Chameleon Systems, Inc.Chameleon Systems, Inc.
Coprocessor based approach Coprocessor based approach (I)(I)
Recon
fig
ura
ble
In
str
ucti
on
Set
Pro
cessors
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Altera ARC-PCIAltera ARC-PCI
Coprocessor based approach Coprocessor based approach (II)(II)
Recon
fig
ura
ble
In
str
ucti
on
Set
Pro
cessors
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Compaq PametteCompaq Pamette
Coprocessor based approach Coprocessor based approach (III)(III)
Recon
fig
ura
ble
In
str
ucti
on
Set
Pro
cessors
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Altera´s Excalibur deviceAltera´s Excalibur device• Embedded Processor: ARM, MIPS or Embedded Processor: ARM, MIPS or
NIOS NIOS
Coprocessor based approach Coprocessor based approach (IV)(IV)
Recon
fig
ura
ble
In
str
ucti
on
Set
Pro
cessors
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Chameleon Systems, Inc.Chameleon Systems, Inc.
Coprocessor based approach Coprocessor based approach (V)(V)
Recon
fig
ura
ble
In
str
ucti
on
Set
Pro
cessors
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Reconfigurable unit within CPUReconfigurable unit within CPU
ASIP based approach (I)ASIP based approach (I)R
econ
fig
ura
ble
In
str
ucti
on
Set
Pro
cessors
Fetch
Decode
Issue
IntegerUnit
FPUnit
BranchUnit
LD/STUnit
ReconfigurableUnit
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Challenge: CAD toolsChallenge: CAD tools
ASIP based approach (II)ASIP based approach (II)R
econ
fig
ura
ble
In
str
ucti
on
Set
Pro
cessors
C Code
Compiler
AssemblyCode
InstructionDescription
(Configuration bits)
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ASIP based approach (III)ASIP based approach (III)R
econ
fig
ura
ble
In
str
ucti
on
Set
Pro
cessors
C Parsing
Optimizations
Inst. Identification
Inst. Selection
Config. Scheduling
Code Generation
C Code
Assembly Code
HardwareGeneration
Configuration bits
HardwareEstimator
Compiler Structure
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Example: Philips CinCISe Example: Philips CinCISe ArchitectureArchitecture
ASIP based approach (II)ASIP based approach (II)R
econ
fig
ura
ble
In
str
ucti
on
Set
Pro
cessors
En
cod
ed
In
str
ucti
on
Word
RegisterFile A
LU
RFU
MU
X
5
5
5
4
32
32
32
32
32
32
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Application example: DES & A5 Application example: DES & A5 encryptation algorithmsencryptation algorithms
ASIP based approach (III)ASIP based approach (III)R
econ
fig
ura
ble
In
str
ucti
on
Set
Pro
cessors
27 26 25 23 22 30
7 6 5 4 3 2
27 26 25 22
XOR
srl $13, $2, 20andi $25, $13, 1srl $14, $2, 21andi $24, $14, 6or $15, $25, $24srl $13, $2, 22andi $14, $13, 56or $25, $15, $14sll $24, $25, 2
srl $24, $5, 18srl $25, $5, 17xor $8, $24, $25srl $9, $5, 16xor $10, $8, $9srl $11, $5, 13xor $12, $10, $11andi $13, $12, 1
29
Reconfigurable Computing is an Reconfigurable Computing is an emerging and interesting computing emerging and interesting computing paradigmparadigm
RC devices and architectures are RC devices and architectures are becoming a realitybecoming a reality
There is a big challenge is High-level There is a big challenge is High-level synthesis (CAD) toolssynthesis (CAD) tools
ConclusionsConclusions
30
What is the future ??What is the future ??
Conclusions (II)Conclusions (II)
Flexibility,Power
Performance
GPP
ASIC
DSP RC
RC
??
RC