Dynamic Power Management for Harvested Energy-based

Embedded Systems

Dynamic Power Management for Harvested Energy-based

Embedded Systems

Tohru ISHIHARAishihara@i.kyoto-u.ac.jp

Department of Communications & Computer Engineering Graduate School of Informatics

Kyoto University, Japan

Project OverviewProject Overview

Grant: Japan Cabinet funding program for next generation (younger than 45 years old) world-leading researchers

Period: Feb. 2011 – March 2014 Goal: Developing Self-Powered Computer Systems

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Power Supply

Embedded Computer Systems

Thermal energy

Solar cells

Kinetic energy

Solar cellsKinetic Energy

Power Supply

Surveillance camera

Smart phone

Wireless router

Cellular phone

0.1-100mW/cm2

2mW/cm3

Solar Cells

Project TeamProject Team

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- Control engineering- Energy harvesting- Fuel cells- Modeling

System Software(Tohru ISHIHARA

Onodera Lab.

-VLSI design-Low-Power &

Dependable Circuits

Collaborationwith Prof. Chang of SNU

- Control theory- Energy harvesting

SystemHardware（KyungsooLEE)

- RTOS- Embedded

system

Collaboration with Prof. Takada of Nagoya Univ.

Interdisciplinary Research Project

- Leader- RTOS- Compiler- Processor

Project Activity OverviewProject Activity Overview Efficiency Generating efficiency Harvesting device efficiency

Consuming efficiency Consumer device efficiency

Transferring efficiency DC-DC converter efficiency Charger efficiency

• Harvested energy is not constant• Power is not available on-demand• High peak power is not available

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Low-Power Multi-Core Processor Design

Power Management Techniques for Memory Subsystems

1st part of this talk

2nd part of this talk

MotivationMotivationLow Power / Low Energy Growth of portable electronics market

Peak Performance Growth of real-time applications

Scalability and adaptability Energy saving without losing the peak performance

Real-time DVFS on a multi-core processor

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DVFS Pros and ConsDVFS Pros and ConsPros Quadratic reduction of energy consumptionCons Low performance at low operating voltage Large overhead of DC-DC converter

T. Burd and R. Brodersen, “Design Issues for Dynamic Voltage Scaling”, ISLPED 2000.

||221 DDDD

MAXTRAN VV

ICt

||)1( 22

21 DDDDTRAN VVCE

C=100μF、IMAX=1AVDD1=1.0、VDD2=0.68tTRAN=64μs, ETRAN =4.6μJ

Typically 0.9

This prevents real-time control of DVFS processors

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Program RAMPE2Middle VDD

PE3Low VDD

PE1High VDD

Data RAM

memory

Dedic

ated B

us

•PEs have the same ISA•Differ in their clock speeds and energy consumptions

•A single PE is activated at a time

Internal register values are transferred through a dedicated bus before switching PEs

Cache

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Our ApproachOur Approach

No multi-port RAM is needed

No data migration is needed when a PE-core switches

Multi-Performance Processor (MPP)

MPP Pros and ConsMPP Pros and ConsPros Low transition overhead Two orders of magnitude less than that of DVFS

Higher performance at low operating voltage Each PE core is optimized for the target supply voltage

Cons Large area overhead Limited number of clock speeds

Need multiple voltage sources

H-PE

Memo

ry

M-PE

DC-DC

DC-DC

Experimental ResultsExperimental Results

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34mW@200MHz

18mW@133MHzDC-DC& VCO

DVFS ProcessorVDD

F26μs164nJ

Overheads

H-PE35mW@200MHz

M-PE14mW@133MHz

Shared local-memory

1μs ,13nJ

MPP (ours)

DVFS

Overheads

Base DVFSMPP

Nor

mal

ized

Ene

rgy

Average execution time for each task

T. Burd and R. Brodersen, “Design Issues for Dynamic Voltage Scaling”, ISLPED 2000.

[ms]

Project Activity OverviewProject Activity Overview

Efficiency Generating efficiency Harvesting device efficiency

Consuming efficiency Consumer device efficiency

Transferring efficiency DC-DC converter efficiency Charger efficiency

• Harvested energy is not constant• Power is not available on-demand• High peak power is not available

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This talk part 2

Low-Power Multi-Core Processor Design

Power Management Techniques for Memory Subsystems

This talk part 1

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Energy Harvesting DevicesEnergy Harvesting Devices10 thermoelectric modules generates microwatts

800mW per shoe at a pace of two steps per second

10m/s wind speed generates 100W electrical power with 1m rotor diameter

1m/s water speed generates 1W with 0.1m rotor diameter

Power Transferring Loss in Portable System Power Transferring Loss in Portable System

8%10%

16%

26%

25%

15%

CPU Memory Frame BufferLCD LCD Backlight DC-DC converter

H. Shim, Y. Cho and N. Chang, "Power Saving in Hand-held Multimedia Systems Using MPEG-21 Digital Item Adaptation," in ESTIMedia, 2004

Up to 15% of power is dissipated in DC-DC converters

Power breakdown in portable audio player

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Power Transferring Loss in Data CenterPower Transferring Loss in Data Center

Power Supply System

208/120ＶAC input

DC/DC

DC/DC

DC/DC

CPU,

Memory

etc.

12Vdc

5.0V

3.3V

DC/DCAC/DC

PSU

DC/ACAC/DC

UPS PDU

VRs

Source: DC Power for Improved Data Center Efficiency, LBNL

Power transferring loss when a computational load is 100W

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Powe

r con

sump

tion [

W]

Power loss depends on Boost-up or drop-down Voltage difference Output power

TPS63030 datasheet. http://www.ti.com/lit/ds/symlink/tps63030.pdf.

Power Loss in Voltage ConversionPower Loss in Voltage Conversion

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inputPEfficiencyLossPower

)100(

DC-DCinput output

MotivationsMotivations

Many DC-DC converters are used in a system Different components use different voltages Large power loss in the DC-DC converters Voltage difference between source and load is large

Energysource

DC-DC

Supplyvoltage A

group

DC-DC

Supplyvoltage B

group

DC-DC

Supplyvoltage C

group

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e.g.) CPU1.0V

e.g.) modem3.3V

e.g.) camera5.0V

Set the voltage here

Reconfigurable ArrayReconfigurable Array

An example for a configurable array 3 configurations with 4 photovoltaic

(PV) cells or super-capacitor cells Each cell has 0.5V, 80mA output

(4,1): 0.5V, 320mA output

(2,2): 1V, 160mA output (1,4): 2V, 80mA output

Reduce the difference between the input and output voltages in a DC-DC converter

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M. Uno, “Series-parallel reconfiguration technique for supercapacitor energy storage systems,” in Proc. of TENCON, 2009.Y. Kim, et al. “Balanced Reconfiguration of Storage Banks in a Hybrid Electrical Energy Storage System,” in Proc. of ICCAD, pp.624-631, November 2011.

Proposed System ArchitectureProposed System Architecture

System block diagram

Power OR’ing by Linear Technology’s ideal diode

Good harvest mode Hybrid mode Bad harvest mode

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K. Lee, T. Ishihara, “A Dynamic Reconfiguration Technique for PV and Capacitor Arrays to Improve the Efficiency in Energy Harvesting Embedded Systems,” in Proc. of SmartGreens, pp. 175-182, April, 2012

Good Harvest ModeGood Harvest Mode

Enough sunlight to operate the loads

Control the configurationto minimize the total loss

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Hybrid ModeHybrid Mode

Not enough sunlight to operate the loads

Control the configurationto minimize the total loss

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Bad Harvest ModeBad Harvest Mode

The power loss in the Conv_cap is more than the amount of generated power from the PV array

Control the configurationto minimize the total loss

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One Case Result for the Array ConfigurationOne Case Result for the Array Configuration

Power loss in converters for different configurations

The lowest power loss

configuration

• CPU, modem, and camera consume 100mA, 30mA, and 1mA respectively

• Sunlight intensity and state of charge in super-cap are 100% and 20% respectively

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SchedulingScheduling I/O aware task scheduling Minimize the overlap among CPU tasks and I/O tasks Make the chance of power reduction larger

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K. Lee, T. Ishihara, “I/O Aware Task Scheduling for Energy Harvesting Embedded Systems with PV and Capacitor Arrays,” in Proc. of IEEE Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia 2012), pp. 48-55, October, 2012

Experimental ResultsExperimental Results

0

20

40

60

80

100

120

loss_convloss_charloss_ploss_modloss_camproc.mod.cam.

80 20 80 20 80 20 100 60 20

Sunlight intensity

State of Charge of super-capacitor

Conventional

Proposal

72% reduction in conversion loss25% reduction in total power

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Nor

mal

ized

Ene

rgy

ConclusionConclusion

Multi-performance processor Small core-switching overhead (2 order of magnitude smaller) More energy efficient in low voltage operation

Energy harvesting system Dynamic PV and capacitor array configuration Simultaneous reconfiguration and task scheduling Power loss in DC-DC converters can be reduced by 72%

Future work Targeting larger system such as smart house, data center, etc.

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