Dynamic Compilation Everywhere - Henri-Pierre Charles...2015/11/26 · architecture Specializedinstructions Fastdevelopmentcycle Cons StaticCompilation Canverify,assert Asmanytimeasneeded

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Dynamic CompilationEverywhere

Henri-Pierre Charles

CEA DACLE department / Grenoble

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Introduction : Course Organization

Dynamic Code GenerationState of the art (SOA)

ArchitectureCompiler

Applications impactMetricsIR for code generationFast code generationHow to debug

EvaluationQCM at the end(whithout documents)“Short term memory”Questions topics aregiven : search for

Assumption ; youunderstand my brokenfroglishknow C languageknow compiler structureknow a script language

Dynamic Compilation Everywhere | DACLE Division | | 2



Intro Why Dynamic Compilation

ProDynamic applicationMemory hierarchy versusdata setUnknown runningarchitectureSpecialized instructionsFast development cycle

ConsStatic CompilationCan verify, assertAs many time as needed

Dynamic Code Generation ! = Dynamic Optimization (or programming)




SOA Arch : ISA

Instruction Set ArchitectureLowest programming Level model : assembly languageAllow to use processor full capacity

Special instructions (multimedia, vectors)Strange memory access

Binary representationRegister access

What is the “instruction execution algorithm” ?Is the assembly language still used ?

https://en.wikipedia.org/wiki/Instruction_set


https://en.wikipedia.org/wiki/Instruction_set



Quizz Question 2USADA8 : not a “simple instruction”Extract from an ARM databook

file:///home/hpc/Desktop/UseFullDocs/ProcessorISA/ARM/ARM/A9docs/DDI0406B_arm_architecture_reference_manual.pdf




Problem example : video compression

Illustration Video Compress




Problem example : video compression

1 # define PIXEL_SAD_C ( name , lx , ly ) \2 int name( uint8_t *pix1 , int i_stride_pix1 , \3 uint8_t *pix2 , int i_stride_pix2 ) \4 { \5 int i_sum = 0; \6 int x, y; \7 for( y = 0; y < ly; y++ ) \8 { \9 for( x = 0; x < lx; x++ ) \10 { \11 i_sum += abs( pix1[x] - pix2[x] ); \12 } \13 pix1 += i_stride_pix1 ; \14 pix2 += i_stride_pix2 ; \15 } \16 return i_sum ; \17 }

(Extract from x264 video compressor from www.videolan.org project,(lx , ly) ∈ {(4, 4), (4, 8), (8, 4), (8, 8), (8, 16), (16, 8), (16, 16)}


www.videolan.org



SOA Arch : Language Classification / Addresses

Definition0 address : stack machines ; all operators are implicit (bytecode java)(Java bytecode, postscript)Register machines :

1 address : A add (other operand implicits)2 address : A += B (x86)3 address : A = B + C (itanium)4 address : A = B * C + D (power)

CompromiseCode compacity, expressiveness“Simplicity” / efficiencyCode generation speed


http://en.wikipedia.org/wiki/Java_bytecode



SOA ARCH : ARM big.LITTLE

big

LITTLE

ARM : “more than 30 billionprocessors sold with more than16M sold every day ARM”(Nov 2013) http://www.arm.com/products/processors/index.php

4 big processors + 4 littleSame ISA, . . .(even for vectoroperation)Low latencie switch

big.LITTLE notion


http://www.arm.com/products/processors/index.php



http://www.arm.com/products/processors/technologies/biglittleprocessing.php



SOA Architecture : RaspberryBuilding block for geek Web site

RaspberryCharacteristics :

ARM1176JZF-S (ARMv6)700MHzRAM : 256 Mo2 video out ; audio in/outSDCARD mem ; 1 PortUSB 2.0 ;300 mAFull OS : linux, BSD, ...20 $

Illustration


http://www.raspberrypi.org/



SOA Architecture : Texas Msp430

Building block for embedded system Arch Overview

Texas MicrocontrollerCharacteristics :

8 to 24 MHz512 to 1024 bytes of ramBare metal1.75$ to 2.45$Cross compiler

Illustration


http://www.ti.com/lsds/ti/microcontrollers_16-bit_32-bit/msp/overview.page



SOA Architecture : GenepyGenepy Bloc diagram

Genepy characteristicsLTE modem processor

Very low power (G Insn / mw)Hard to program (Kb of RAM), specialized operators

Locally heterogeneous (MIPS + DSP Mephisto) / Globally homogeneous




Architecture Nexus4

Face(red) Toshiba THGBM5G6A2JBA1R 8GB Flash(orange) SlimPort ANX7808 SlimPort Transmitter (HDMI outputconverter)(yellow) Invensense MPU-6050 Six-Axis (Gyro + Accelerometer)(green) Qualcomm WTR1605L Seven-Band 4G LTE chip(blue) Avago ACPM-7251 Quad-Band GSM/EDGE and Dual-BandUMTS Powe Amplifier(violet) SS2908001(black) Avago 3012 Ultra Low-Noise GNSS Front-End Module

BackSamsung K3PE0E00A 2GB RAM. We suspect the Snapdragon S4 Pro1.5 GHz CPU lies underneath.Qualcomm MDM9215M 4G GSM/CDMA modemQualcomm PM8921 Power ManagementBroadcom 20793S NFC ControllerAvago A5702, A5704, A5505Qualcomm WCD9310 audio codecQualcomm PM8821 Power Management

http://www.ifixit.com/Teardown/Nexus+4+Teardown/11781


http://www.ifixit.com/Teardown/Nexus+4+Teardown/11781



Rappels Nexus4Compil

Application SDK :Java programming languageDalvik virtual machineAndroid Market / Google controled

Native compilationModem stack

Native codeCross compilerClosed source

System stack mostly opensourceCyanogenmod build

Virtual machine CyanogenmodBuilding from source


http://wiki.cyanogenmod.org/wiki/Building_Kernel_from_source

http://www.cyanogenmod.org/

http://wiki.cyanogenmod.org/wiki/Building_from_source



SOA C compil chain

DescriptionC language (K&R), C90up to C11Normalizedgcc, clang, icc, tcc, ...

Compilation chainPreprocessing (# stuff)Compilation

Lexical / SyntaxicIR formPhases / passesInstructions selection

AssemblyLoad

https://en.wikipedia.org/wiki/C_(programming_language)


https://en.wikipedia.org/wiki/C_(programming_language)



Rappels Static Compilation chain

Static compilation (on C language) :1 Preprocessor (all # stuff : rewriting) cc -E

2 Compilation (from C to textual assembly) cc -S

3 Assembly (from textual asm to binary asm) cc -c

4 Executable (binary + dynamic library)

OptionalProfiling : Compile (use -pg) produce File ; Run File ; Use gprof

cc -da dump all intermediate representation

(Use gcc -v to see all the steps)Don’t stop at static time (Operating system + processor) : Load inmemory, dynamic linking ; Branch resolution ; Cache warmup




SOA Java

DescriptionJava Language (Sunmicrosystems / Oracle),95NormalizedStack machineEnormous API (+10000classes) “Compile once,run anywhere”Oracle, IBM, Google(+/-)

Compilation chainjavac (.java to .classbytecode)interpretation“Hotspot” compiler

trigger most usedmethodserver or client profile

class to executable

https://en.wikipedia.org/wiki/Java_(programming_language)


https://en.wikipedia.org/wiki/Java_(programming_language)



SW-SOA Dalvik

DescriptionJava languageAndroid APINormalized ...Google toolboxSecurityStoreDalvi is a register basedmachine

Compilation chainjava to dalvikDalvik VM optimized forsmall memory machinesdalvik jitted

https://source.android.com/devices/tech/dalvik/





SOA LLVM

DescriptionLow Level VirtualMachinehttp://llvm.org

Many compilation project(compiler toolbox)C ; C++ ; Objective-COther frontend viadragonegg

Compilation chainNative compilation(clang)LLVM bytecodeinterpretation (lli)Ahead of timecompilation ()JIT


http://llvm.org



SOA JavaScript

DescriptionScript languageTrace based compilationTons of tools (server sideand client side)Used as back-endlanguageNormalized, but withvariants

Compilation chainSource interpretationJIT part of scripts

https://en.wikipedia.org/wiki/JavaScripthttps://en.wikipedia.org/wiki/Comparison_of_server-side_JavaScript_solutionshttps://en.wikipedia.org/wiki/Node.jshttp://bellard.org/jslinux/


https://en.wikipedia.org/wiki/JavaScript

https://en.wikipedia.org/wiki/Comparison_of_server-side_JavaScript_solutions

https://en.wikipedia.org/wiki/Comparison_of_server-side_JavaScript_solutions

https://en.wikipedia.org/wiki/Node.js

http://bellard.org/jslinux/



SW-SOA JavaScriptVM

VM CategoryWeb Browser

V8 Chrome browserSpider monkey Firefox

Server sideEmbedded

“Smallest javascript”Tiny-JS / STM32C++


https://en.wikipedia.org/wiki/V8_(JavaScript_engine)

https://en.wikipedia.org/wiki/SpiderMonkey_(JavaScript_engine)

https://github.com/cesanta/v7/

https://github.com/snoozbuster/tiny-js

https://github.com/snoozbuster/tiny-js



SW-SOA Other

Other LanguagesPython, PHP, LUA,FORTH, . . .Fast developmentHuge library

Compilation chainNoneScript compressionJITNative Call Interaction




Arch Memory Cache Hierarchy

Memory type Perm. ? Access time Who care ?Processor Register no ns CompilerCache L1 no ns/ms CompilerCache L2 no ns/us CompilerCache L3 no us/ms Compiler /ApplicationRAM yes/no 10 ms ApplicationFlash / SSD yes .1 s SystemHard drive yes 1-10 s SystemTape Backup yes mn/hr User

Price / Access Time / Who care about




Arch Instruction Execution

ArgumentationWhile true

Fetch instructionIncrement PCDecode instructionFetch / Get DataExecute operationStore result

Vocabulary

RegisterUALPCRISC/CISC

https://en.wikipedia.org/wiki/Instruction_cycle


https://en.wikipedia.org/wiki/Instruction_cycle



SW-SOA OOO

Out of Order principle“Intelligent Reordering”Add a dispatch queueCF Slide ARMbig.LITTLE

IllustrationEasy to compileSame ISA, evolution atmicro architectural level(TICK/TOCK Intel)Difficult to compile veryefficient code

https://en.wikipedia.org/wiki/Out-of-order_execution


https://en.wikipedia.org/wiki/Out-of-order_execution



SW-SOA MicroController

DescriptionSingle chip with

Compute nodeRAM / ROMI/ODAC ConverterChip radio (IoT)

ProgrammingBare metalCross compilationInteractive (Script)

https://en.wikipedia.org/wiki/Microcontroller


https://en.wikipedia.org/wiki/Microcontroller



MPSoC : Multiprocessor System on Chip

One single chip which containsIP blocks (Intellectual property).

FFT / Turbo code / ../..ProcessorsMemory

Why ?IP : Save energySame chip : Save energy, ease integrationMemory on chip : Save energyMultiple processors : parallelism to ... save energy

http://en.wikipedia.org/wiki/System_on_a_chip


http://en.wikipedia.org/wiki/System_on_a_chip



Vocabulaire Lois

Moore http://en.wikipedia.org/wiki/Moore’s_law

Amdahl http://en.wikipedia.org/wiki/Amdahl’s_law

Memory bound http://en.wikipedia.org/wiki/IO_bound

CPU bound http://en.wikipedia.org/wiki/CPU_bound


http://en.wikipedia.org/wiki/Moore's_law

http://en.wikipedia.org/wiki/Amdahl's_law

http://en.wikipedia.org/wiki/IO_bound

http://en.wikipedia.org/wiki/CPU_bound



Vocabulaire Speedup

NotionSpeedup S = 100 ∗ Tseq

ToptCan be between

1 and N processor1 and vectorizednon optimized versus optimized version

Mesure Quality what are the execution conditions : data set, computerworkload, reproducibly, ...

Computer science has to use “human science” tools & methodology




Metrics How to Measure Performance ?

What scale ?Application level (TPS,Frame/s, .../)Run to completionMethod levelInstruction level

ToolsWall clockgettimeofday

Performance counters

Full application or functioncall ?

Cold start / warmupStatistic / multiple callsHow many calls




Vocabulaire Peak / Sustained

NotionsPeak performance : maximal theoretical performance, assuming no

bubbleSustain performance : real acheived performance, on a real

benchmark

CostWhat is the percentage you’re ready to lose ? 90% 95%?How many are you ready to pay (time, money) to minimise this loss ?

http://www.top500.org





Vocabulaire : Cycle par seconds / Flops

UnitsMips Million operation per secondFlops Floating point operation per second


Flops/Watt Floating point operation per watt per secondhttp://www.green500.org

IPC : Instructions per Cycle

How to mesureAnalytique (wall clock)Instrumentation

“Portable” (gettimeofday())Hardware (hardware performance counter)



http://www.green500.org



Vocabulaire Amdahl

ArgumentationThe speedup of a programusing multiple processors inparallel computing is limitedby the sequential fraction ofthe program. For example, if95% of the program can beparallelized, the theoreticalmaximum speedup usingparallel computing would be20x as shown in the diagram,no matter how manyprocessors are used.

Illustration




Amdahl2ArgumentationAssume that a task has two independent parts, A and B. B takes roughly25% of the time of the whole computation. By working very hard, onemay be able to make this part 5 times faster, but this only reduces thetime for the whole computation by a little. In contrast, one may need toperform less work to make part A be twice as fast. This will make thecomputation much faster than by optimizing part B, even though B’sspeed-up is greater by ratio, (5x versus 2x)

Illustration




Intermediate representation (IR)

Represent a programEach compiler hasa/many IRsInstruction ListProgramming model(0/1/2/3 address)Easy to manipulate (SSA)List of instructions

What for ?(re) Generate codeBinary code at staticcompil timeBinary code at run-time




IR LLVM

LLVM Intermediaterepresentation

SSA form“Easy” to readUsed for OpenCLMany Possible Scenarii

ExamplesCompilte to native clangfile.c -o file

Compile to bytecodeclang -emit-llvm -Sfile.c -o file.bc

Interpret : lli file.bc

Compile ahead of time :llc test.bc

Optimize bytecode :opttest.bc




IR Java ByteCode

Java BytecodeStack based machineByte InstructionsFast interpretorBytecode Verifier/prover

Examplesjavac File.java“Bytecompile” java programjar tf a.jar File.classLinkjava File.class or a.jarLaunch VM

-server|-zero|-javm|avianchoose VM-XX:CompileThreshold=N1500=client, 10000=server

javah .h for JNI callhttps://en.wikipedia.org/wiki/Java_bytecodehttps://en.wikipedia.org/wiki/Java_bytecode_instruction_listingsDynamic Compilation Everywhere | DACLE Division | | 37

https://en.wikipedia.org/wiki/Java_bytecode

https://en.wikipedia.org/wiki/Java_bytecode_instruction_listings

https://en.wikipedia.org/wiki/Java_bytecode_instruction_listings



IR Java ByteCode

Java VM interpretorRead an instruction (abyte)Choose a case (switch)Use statistics (methodcount)Method call :if call count > thresoldthen Jit compile

if method nativethen call nativeelse call interpretor

HotSpot JITChoose thresold (clientversus server)JIT compile a methodIterative compilationContext switch betweennative and virtualenvironment !




IR ART

Android RuntimeAndroid Virtual Machine(Not JVM)Register basedDalvik was JITed, ART isahead of time (installtime)

Compiler optionseverything - compilesalmost everythingspeed - maximizesruntime performance,(default option)balanced -performance/compilationinvestment.space - prioritizing storagespace.interpret-onlyverify-none - should beused only for trustedsystem code.

https://en.wikipedia.org/wiki/Android_Runtimehttps://source.android.com/devices/tech/dalvik/


https://en.wikipedia.org/wiki/Android_Runtime


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Dynamic Compilation Everywhere - Henri-Pierre Charles...2015/11/26 · architecture Specializedinstructions Fastdevelopmentcycle Cons StaticCompilation Canverify,assert Asmanytimeasneeded