DV29 service manual issue 1.pdf

ServiceManual

DV29 DVD Player

Issue 1.0

ARCAMARCAMBringing music & movies to lifeBringing music & movies to life

Circuit Description

Power Supply L959AY

! CCT diagram ! Component layout diagram ! Parts list

Main Board L971AY


Display Board L972AY


Transformers

! L924TX ! L925TX ! L931TX

Mechanical Assembly

! Mechanical and packing part list

DV29

Contents List

Overview

The DV29 is effectively a no compromise version both electronically and mechanically of the DV79.

The player is based around acclaimed Zoran Vaddis V

chipset coupled to high specification Wolfson D to A converters for all six audio output channels, also featured in this design is a HDMI transmitter with digital Video and a Audio output capable of Digital Surround.

The DV29 and the DV79 use the same main board and power supply stage but with many of the components either upgrade or replaced with different topologies, many of the critical audio/video components with 0.1% tolerance within the DV29 and we also have an extra toroid power supply for the Audio stages.

Both the HDMI chip and Video encoder are of a higher quality than those found inside the DV79.

Power supply board.

Non-switching

Mains power arrives at IEC inlet socket SKT1 and is filtered by EMC choke LI and Y caps C3 and C4, mains switch SW2a/b switches both Negative and Live phases before the power reaches the mains select switch at location SW1 the switch allows the primary windings of the transformer TX1 to be wired in either Parallel or Series configuration.

The Bridge rectifying Diode package at location D1 forms the basis of the conventional power stage and supplies a VN35V6 (-35.6v) to the Switch mode stage, transistor TR1 is biased by 2v7 Zener diode DZ1

and allows for the series Zener diodes DZ2, DZ3, DZ3

to supply the VN13V5 and VN19V rails.

We will also see a simple A.C present circuit this is used for delayed output relay operation and fast relay closure under interrupted supply conditions thus preventing op-amp offsets from reaching the Audio output sockets.

Switch mode

The switch mode supply is formed around the Driver/Control chip IC1 UC3843 (used in regulating mode). The chip is referenced the 36.5V supply line and the Digital ground DGND, the supply for the chip is formed by the 12v Zener at location DZ6 and can be seen on Pin 7 as VCC. The power supply allows for the switch-mode to be tied the to Audio sampling frequency for any given compatible format see Fig 1.

Fig 1 PSU clock control and IC305 line status

Fs Frequency select

PSUFS1 Pin 11 IC305a

PSUFS0 Pin 12 IC305a

PSUCLK Output Pin 5 of IC305a

44.1 kHz 0 0 44.1 kHz 48 kHz 0 0 48 kHz 88.2 kHz 0 1 44.1kHz 96 kHz 0 1 48 kHz 176.4 kHz 1 0 44.1 kHz 192 kHz 1 0 48 kHz Others 1 1 OFF

The PSU sync signal is driven into the power supply via Resistor R9 if no Sync is present the unit is set to free run at xxxx due to the RT/RC network attached to Pin 4.

IC1 is running in regulated mode and monitors the voltage

output on the +5V and +3V3 D.C lines, the two voltages are summed by TR8 and Driven into the VFB and Comp inputs of IC1, the Voltage is then regulated by changing the time base of the PWM output at pin 6 (longer the time base the lower the voltage), the PWM switching frequency is driven into the switch-mode transformer by the high speed Nmos device at position M1, R5 is used to sense the Current across the gate of the Nmosfet and in the event of a short circuit will safely shut the power supply down. We derive the 12v Mech supply from the output of M1 using the Ultra-fast Diode at location D8 to rectify the PWM line.

The D.C outputs from the switch mode have extensive switch mode noise removing filters these are seen as 100n caps down to ground and Wire wound inductors in series with the supply rail.

Power supply main board

All the power supply rails are supplied to the main board via the 32 way FFC conector at location CON1001.

The Digital supplies from the switch mode stage of the power supply arrive as 3V3D, +5VD and +12VD we also see the Display board power supplies arrive as 19V, -9V and 13.5V

all of the supplies have a second stage of implemented on the board to remove all traces of ultra-sonic noise.

The 3V3D rail is the main 3V3 rail used to power the digital circuitry; +5VD is used for all 5v Digital/Video supplies the +12VD is used for Scart switching and to power the HDMI circuit (not DV78).

The 1V8 rail is derived from the 3V3 rail and is regulated by the adjustable regulator at location REG1003.

FMJ Dv29 Circuit description.

The DV29 uses a separate isolated Toroid transformer and Rectification stages based around Bridge rectifiers DBR1000

and DBR1001 and bulk smoothing caps C1048 and C1049 to supply the Analogue stages the smoothed D.C output from this stage is fed L1013 (+) and L1015 (-).

Regulator REG1001 is fed from the +15V3 rail and forms the Audio DAC supply.

The Display board requires several supply voltages these are simply passed through the main board, being filtered on the way to prevent transmission of noise through to the surrounding electronics. The display takes the +5V, -19V, -13V5 and -9V the 13V5 and 9V form a floating 4.5V supply biased relative to the 19V grid voltage.

Display Board

The main component of the Display board is IC1 this is a Vacuum Florescent Display driver with keyboard san and a serial data in/out interface.

The Chip receives display drive serial data from the Vaddis V chip on the main board via Con1 on pins 12, 13 and 14 these will be seen a DIN, STS and CLK this data is used to drive the VFD a DOUT line interfaces with the VADDIS V and supplies Keyboard Scan information. The keyboard scan is a 6 x 4 matrix with the Key Source appearing at S3, S4, S5, S6 and the Keyscan data returns appearing a K2, K3 and K4.

Please see: above for power supply information.

The Infra red pick-up at location RXI receives RC5 data and send the data to the Vaddis V on the main board via transistors TR2 and TR3, LED 2 is used to mix the rear panel RC5, this is covered in-depth within the Coms and Video output section of this guide.

Main Board electronics

Zoran Vaddis V.

The main processor/control chip on the main board is the Zoran Vaddis V at location IC202, this is the latest incarnation of the very popular Vaddis range of processors and allows for a much lower component count when compared to our earlier players as many of the playback functions have moved onto the Vaddis V silicon.

Below you will see the major functions of the Vaddis V

o 20 Bit digital video output for external Video DACs and HDMI output stage.

o Decoded Analogue Video output (internal DAC) used on the DV78 only.

o Digital Audio output 3 data lines 6 channels for internal L + R DACs and L + R + C + LS + RS for DV79 and DV29 also used for HDMI for the DV79 and DV29.

o SPDIF output.

o Internal display interface.

o Internal ATAPI interface.

o Internal IR interface.

o Serial in/out for RS232 DV79/DV29

A more detailed explanation of the Vaddis V and peripheral components follows.

Vaddis Power

The Vaddis V is powered by two separate supplies the Vaddis requires a 1.8v supply for the core, this is regulated from the 3.3v rail by REG1003, the 3.3v rail is used to supply power to the I/P O/P ports of the chip.

ATAPI interface

CON203 is an ATAPI interface on a 40 way IDE connector. This is decoupled from the Drive via an array of decoupling resistors as required by the ATAPI spec.

Display Board interface

The display board interface is on the 16 way FFC flexi foil connector at location CON202. Power for the display also travels on the connector. There are 4 wires to interface with the VFD driver chip these are seen as.

o XFPDIN - Data to the display board o FPDOUT - Data from the display board o XFPCLK - Clock

o XFPSEL - Chip select

The above control lines are level shifted to 5v logic from 3.3v levels by IC200 (74HCT125) these are the levels required by the VFD drive chip.

The IR output from the Display board arrives as IRRCV this is an open collector signal, which can be wire-Ord with the re-panel remote input.

Digital Audio

The Digital audio leaves the chip 3 sets of data lines labelled as.

o ADAT0 - Left and Right channel data o ADAT1 - Left and Right surround o ADAT2 - Centre and Sub

Along with the ADAT line we will also see the ABCLK and ALRCK as required for IS2 data conversion.

The Vaddis V also supplies a direct SPDIF output for interfacing with ancillary processing equipment.

Digital Video

The Digital Video output from the Vaddis V consists of the following signals:

o VIDPO to 19 - 20 Bit wide digital video data o CLK_27M - 27 Mhz Video clock o VSYNC - Vertical sync o HSYNC - Horizontal Sync

The 20 bit wide bus VIDP0 to 19 provides video data as follows.

Interlaced video mode: VIDP0 to 7 provide multiplexed 8 bit Y, Cb and Cr data with VIDPO being the Isb.

Progressive scan video mode: VIDP0 to 9 provide 10 bit multiplexed Cb, Cr data with VIDP0 being the Isb. VIDP10 to 19 provide 10 bit Y data with VIDP10 being the Isb.

Flash/ SDRAM

IC203 is a 64Mbit (32 bit x 2Meg) SDRAM. It runs at

135MHz

IC205 is a 16Mbit (16 bit x 1Meg) intel type flash IC for program storage (Player software).

The flash interfaces to the Vaddis V using the SDRAM bus it may appear that the bus connects to the flash in a random manner, however this is simply because the Vaddis bus is multiplexed that way. The Flash will be accessed at power up and the contents are copied to the SDRAM the program will then be run from the SDRAM. Series resistors are employed to isolate the flash bus from the main SDRAM bus.

EEPROM

IC204 is a 8kBit (1K x 8) Serial EEPROM. This is used for storage of non-volatile storage of player settings, region settings and bookmark data.

Clocks

CLK27MV is the 27Mhz clock for video. It is used to generate the 135Mhz clock for the Vaddis microprocessor and DSP. The MCLKV is the audio master clock for the Vaddis.

We run the Vaddis in PLL bypass mode and generate or own master clock (see main clock section of manual) for higher accuracy and improved performance across Audio and Video.

RESET

IC201 is a reset generator chip that monitors the +3.3V rail and ensures a reset signal PWR_ON_RESET* is generated on power up, or if the mains power dips below an operational level. This signal is used to reset the Vaddis V and Flash micro only. The Vaddis V line labelled as RESET* resets the remaining circuitry of the player apart from the HDMI chip, this has its own reset line labelled as HDMI_RESET this is necessary if we require to reset the HDMI chip only (for example when the HDMI sink is connected and then disconnected).

Serial Port

The VADDIS V can interface with the external world via the RS232 connector at location CON900 and the RS232 Transceiver at location IC900, the serial data lines are shown as SERIAL RX and SERIAL TX these lines allow for direct control over the unit via RS232.

Fig 3. GPIO control signals from the Vaddis V

Single Name I/P-O/P Function PSUFSO-1 Output Control PSU Clock

divider ENABLE_AV Output SCART control High

in normal operation and low in standby

16/9 Output Scart 16/9 anamorphic control line

9190INT* Input Interrupt signal from SII9190 HDMI transmitter

GAIN_SCALING Output High for HDCD gain scaling

ML_8740_0-2 Output SPI load signal for Audio DACs 0,1 and 2 (see note 1)

MC Output SPI clock signal for DAC control

MD Output SPI data signal for DAC control

FSELE0-1 Output Frequency select generator

MUTE* Output Active low audio mute signal

DDC_SDA,DDC,SCL I/O 12C bus for DDC channel on HDMI interface

PROG_INT* Output High for Progscan mode, Low for interlaced mode. Controls Sil9130 data mux

HDMI_RESET* Output Reset signal for HDMI transmitter

RESET* Output System reset

Clocks and SPDIF stage.

IC300 is a SM8707E clock generator IC. This IC is sensitive to noise on its power supply, which causes clock jitter for this reason we have a independent Low dropout low noise +3v3 power supply for the chip based around the regulator at location REG300.

X300 is a 27Mhz crystal that IC300 uses to generate

all the video and audio clocks required by the system the crystal sits on the XTI and XTO pins of the chip, the 27Mhz output at Pin 4 (MO2) is used to drive the Vaddis chip directly bypassing the internal PLL.

The frequency of the audio master is dependent on the on the current audio sample rate (I.e the sample rate required by the format CD=44.1Khz and DVD=48khz etc) and this is set by the system micro via the FSLO and FSEL1 this selects either the 22.5792Mhz or 24.576Mhz clock from frequency from IC300 this may then be divided by 2 by the clock divide chip at location IC306 depending on the status of FSEL1. Therefore 4 clock frequencies may be obtained to support all required audio samples rates.

Nand gate IC303 is used to gate FSEL1 with

ENABLE_AV (which is low in standby mode) as such when in standby mode the audio clock is disabled.

Clock Buffer

IC301 us used to buffer the audio master clock. The circuit is arranged so that each device that requires the audio master clock has its own driver these are seen as.

o MCLK_DAC0 - Pin 18 o MCLK_DAC1 Pin 16 o MCLK_DAC2 Pin 14 o MCLK_VADDIS Pin 3 o MCLK_HDMI Pin 9

We also run the Mute Line from the Vaddis V IC301 this can be seen on Pin 12 and drives transistor TR401, the transistor pulls the relays RLY400, RLY500, RLY600 to ground and un-mutes the audio outputs.

IS2 Audio Data

IC302 and IC309 are buffers for the 12S signals these

ensure that the signals travelling to the DACs are point to point. IC302 deals with the ALRCK and ABCLK and IC309 the ADAT0,1,2 all signal are split into three separate lines for the three stereo DACS.

PSU Clock Divider

IC304 and IC305 form a clock divide by 1, 2 or 4 to ensure the PSU clock is always either 44.1kHz or 48Khz (See fig 1 within the power supply description section). This circuit will also switch the PSUCLK off when switching between sample rates (the PSU will free run when the PSUCLK is not present).

SPDIF Output

The SPDIF output consists of IC308 implemented as a inline buffer and parallel output buffer. Gate A buffers the signal so that the SPDIF line from the VADDIS sees fewer loads and form a feed to the Optical output transmitter, gates B,C and D drive the SPDIF in parallel so that we can drive a 75ohm load adequately. The resistors at the output of IC308 are arrange so that the output will be 500mV pk-pk

when the output is terminated with a 75 ohm load at the same time the output impedance of the circuit is 75ohms as required by the Sony Philips Digital Interface specification, the transformer at location TX301 electrically isolates the SPDIS output.

Left and Right channel D to A stages

The Wolfson WM8740 stereo DAC requires +5V(A) and a +3V3 supply along with the Digital Audio data lines already described in this guide.

The Left channel output only will be described in this section as all audio output stages are the identical (all six channels of a DV79) apart from the HDCD gain switching for L + R only.

IC400B and associated components for a 2nd order

Bessel filter with a differential input and a gain of 1 this follow by a output buffer IC401B, the gain of IC401B is control by the switching chip at location IC402, in normal use the Gain of IC401B is set to 1.1 but in HDCD

mode the IC402 switches a second 10k resistor in parele with R413 and the gain is set to 2.2 allowing for the higher audio output required by the HDCD standard.

C436 is a A.C coupling capacitor used to remove the few mV of offset that the DAC produces, D400 provides protection against from ESD.

The all output relays are under control of the Vaddis V chip but will also mute the outputs instantly under mains failure conditions. Switching drive is provided by TR401 (MUTE_BUF) and TR400 (AC_PRES) the relays are in mute mode if either the input to TR401 is Low or if the input to TR400 is high.

Please note: The Scart left/right audio is fed from the

outputs of the left/right audio stages.

Video Encoder

The video encoder at location IC703 is an Analogue devices ADV7310 video encoder, supporting interlaced and progressive scan video. Please note the 0.1% tolerance components around this stage. IC703 runs on a 2.5V supply provided by REG700 the voltage reference for the chip of 1.225V is provided by REF700

and should be seen on Pin 46. C730-731 and R736 form an external PLL filter.

The Data lines into the encoder arrive as VIDP0 19 from the outputs of the VADDIS V chip.

The external current setting resistors for the internal DACS are seen as R721-R722 and R738-R739 these set the correct output level for the DACS.

The encoder gives out 6 video signals, for composite, S-Video (Y and C) and shared YUV/RGB signals. The setting of the RGB or YUV mode is select with the Video settings page of the Setup menu.

The six analogue output signals are seen as.

o DAC_A = Composite o DAC_B = SVID Y o DAC_C = SVID C o DAC_D = Y or Green o DAC_E = U or Blue o DAC_F = V or Red

Please note: When the player is in Progressive scan mode the composite and S-Video signals will be switched off.

The Video outputs from IC703 are filtered by six identical filters. For instance if we look at the Composite stage we will see a very slow roll off filter comprising of C719, C721 with L701 and L703 the 3dB point of the filter stage is around 40Mhz, resistors R700 and R702 form a load for the current output DAC and as such set the relative output level.

The outputs are driven by the Video op-amp at location IC700A

this has a gain of 2.15 and is terminated by a 75ohm resistor, D701 forms protection against ESD.

These signals now travel to the COMMS and Video extension card on Con 901.

SCART Output

RGB and Composite video signals as well as left and right audio signals are all present on the SCART output socket. As the RGB and YUV signals share the same output port at the Vaddis V the player must be set to RGB SCART

operation to have a RGB output on the SCART. Please note: When in RGB SCART mode the RGB does not contain a Sync signal and the sync must be taken from the Composite out (4 wire RGB).

Also present at the Scart are a number of control flags for the monitor these include 2 GPIO control lines direct from the Vaddis.

o ENABLE_AV o 16/9

These are seen at the SCART output pins as.

o O/6/12 o RGB STAT

The 0/6/12 line (SCART pin 8) is used to inform the monitor of the screen format being sent by the player as set in the video set-up section of the software.

o Standby = 0V o 16:9 aspect ratio = 6V o 4:3 aspect ration = 12V

The RGB status line (SCART pin 16) will be seen as 0v = no RGB and >1v is RGB present.

HDMI output stage

Please note: Due to the plug and play nature of the HDMI/DVI interface, if presented with a reported no HDMI problem it is worth checking all set-up parameters of both the DVD player and the Plasma/Projector in use before performing component level diagnostics on this section.

HDMI is a system that transmits uncompressed digital video and digital audio over a high speed encrypted interface.

IC1102 is an SII9030 HDMI transmitter IC in essence

the chip takes the Digital Video and Audio information and sends the Data out in HDMI format.

REG1100 is used to generate a clean regulated 3V3

power supply to Pins 18 and 33 of the HDMI chip.

IC1100 IC1101 are 3 state octal/line drivers these form a multiplex that switches between the 2 groups of signals for the video data input stage of the SII9190 the multiplexer is control by the Signal from the Vaddis V labelled as PROG/INT this will sit at logic 1 for Progressive scan and logic 0 for interlaced.

In interlaced mode the 8 bit Y/Cb/Cr video data on VIDP7-0

are passed to input port pins D15 D8 of the SII9190.

In Progressive scan mode all 20 bits of the Video data bus are used and get mapped as follow.

VIDP 19 -12 provide 8 msbits of Y data to pins D15-8

VIDP 11 -10 provide 2Isbits of Y data to pins D2-3

VIDP 9 - 2 provide 8 msbits of Cb/Cr data to pins D23 16

VIDP 1 0 provide 2 Isbits of Cb/Cr data to pins D7 - 6

Along with the VIDP video data lines we must also see

VSYNC Vertical sync data HSYNC Horizontal sync CLK27M_VID 27Mhz video clock.

SPDIF Digital audio data (Full surround) MCLK_HDMI Used to strobe HDMI dig audio

At the output of the HDMI chip we will see the following signals at SKT100.

TMDS (Transistion Minimised Differential Signalling) this consists of a clock signal (TXC+/TXC-) and 3 data signals (TX0+/TX0-, TX1+/TX1- and TX2+/TX2-). All signals are differential and use current switching techniques therefore no signals will be observed unless the output is correctly terminated. In this application the clock signal will always be 27MHz and the data signals will be clock X10 so 270Mbit/s.

DDC Channel this is a 12C interface on DDC_SCL and DDC_SDA. These signals connect to the VADDIS V which is the I2C bus master, The DDC channel is used to read back information from the HDMI sync regarding its Video and Audio capabilities and is also used for HDCP encryption authentication.

+5V Power, the HDMI interface requires a 5V supply capable of delivering around 50mA, the supply is provided by REG 1101 which delivers the required current and will shut down in the event of a short circuit.

Hotplug. The HDMI `Hot plug signal HDPIN is a +5V to signal the presence of equipment being connected, this converted to 3v3 logic 1 as IC1100 is not +5V tolerant.

CEC. The CEC (Consumer Electronics Control) signal is a 1-wire bidirectional control signal. It connects to the Vaddis via an ESD protection circuit D1102 at the moment this line is not used at present and is an optional part of the HDMI specification.

Comms and Final video output stage

The signals from the main board travel up to the Comms board on connector CON902.

The Video signals simply travel via an A-C coupling net before exiting the player via the RCA-phono sockets at locations SKT902 and SKT903.

The RS232 interface is on 9 way D type CON900, with IC900 providing the level translation and static protection between the RS232 levels and the 3.3V CMOS levels required by the VADDIS V, CON900 also supplies a +5V Status level when ever the unit is not in standby this generated from a buffered version of the AV_ENABLE signal as used within the SCART output stage (0V in standby).

We have two remote input buss on this board, the first can be seen to arrive at SK901 on a 3.5mm mono jack signal received should be a 36Khz modulated RC5 signal, the RC5 data then travels to the front panel and is fed to IR led that is sited just behind the front panel IR Sensor, we use the sensor to demodulate the and opto-isolate the signal due to the fact that the signal is floating up from ground.

The 3.5mm socket at location SKT900 is used to receive un-modulated RC5 the 0V representing a space (equivalent to no-infra-red carrier), this input is effectively wire-Ord with the front panel IR receiver on IRRCV

these take the form of a 5V/0V RC5 signal, with 5V representing a mark (equivalent to a burst of 36Khz carrier on infrared) and 0V representing a mark (space), the signal is simply inverted and wire-ord to the display board Infra-red led via TR900.

ISSUE

DRAWING NO.

DRAWING TITLE

DATE

Filename:

ECO No. DESCRIPTION OF CHANGE

L959_1.1.sch

DV78 SERIES PSU

Contact Engineer: L959CT22-Apr-2004INITIALS

Printed: 1 1Sheet of

Notes:

Contact Tel: (01223) 203200Kevin Lamb

A & R Cambridge Ltd.Pembroke Avenue

Cambridge CB5 9PBWaterbeach

DGND

DGND

DGND

DGND

DGND

VN35V6

VN35V6 VN35V6VN35V6

DGND

115V

115V

6

4

2

1

5

3

7

TX1Small Toroidal MainsL924TX

D12KBP02

VN35V6

DGND

1

2

3

4

5

6

CON1

MOLEX44472

L

N

E

SKT1BULGINPX0580

C2

C1 C33N3250VCER

C43N3250VCER

1

34

2

L1250U

SW2ASDDFC30400

SW2BSDDFC30400

1

A

1

1

B

2

A

2 2

B

115V 230VSW118-000-0019

FHLDR220mm HLDR

FHLDR120mm HLDR

FS1 T315mA

S504

FS2T315mAS504

VN19V

EMC Shield

SH1

1234

CON5

AmpHD Pwr Con

VP5V

VP12V

DGND

123456789

1011121314151617181920212223242526272829303132

CON7

MOLEX52045

VN19V

VN13V5_F1VN9V_F2

DGNDAGND

VP12V

VP15V5

VP5V

VP3V3

VP3V3

VN15V5

VP5V

VP3V3

VP3V3

VP3V3

VP3V3

VP5V

SPARE3SPARE4

AC_PRES*

PSU_CLK

DGND

VP3V3

VP5V

SPARE1SPARE2

C46470UF25VYK

C39220UF16VYXF

C541000UF16VYXF

C551000UF16VYXF

C45470UF25VYK

C44470UF25VYK

D4

UF4003DO-41

C34

1N0 100VCERC36

1N0100VCER C25

100N100VMKS2

C20100N100VMKS2

C22100N100VMKS2

C21100N100VMKS2

C23100N100VMKS2

C26100N100VMKS2

C24100N100VMKS2

C19100N100VMKS2

C18100N100VMKS2

R3110R0W25MF

R18

10R 0W25MF

R22

470R 0W25MF DZ5

BZX79C5V1DO-35

TR6BD179TO-126

R24

33R 0W25MF

R5

4K7 0W25MF

C40220UF16VYXF

C17100N100VMKS2

DZ6BZX79C12VDO-35

R119K10W25MF

R76K80W25MF

R4

4K7 0W25MF

R2668R0W25MF

R272K70W25MF

R25100R0W25MF

R2822R0W25MF

R1510K0W25MF

C50

22N 100VMKS2

C16100N100VMKS2

C564N7100VCER

TR8

BC556BTO-92

M1IRF640NTO-220

C6100N100VMKS2

C7100N100VMKS2

COMP1

VFB2

ISEN 3

RT/CT4

G

N

D

5

OUT 6

V

C

C

7

VREF8

IC1UC3843ANDIP-8

TR7BC556BTO-92

DGND

TR3BC546BTO-92

R1310K0W25MF

VP5V

PSU_CLK

C35

1N0 100VCER

R19

10R 0W25MF

C33

1N0 100VCER

R23

33R 0W25MF

AGND

C41470UF25VYK

C9100N100VMKS2

C10100N100VMKS2

C12100N100VMKS2

R20470R0W25MF

D2

UF4003DO-41

C42470UF25VYK

C13100N100VMKS2D3

UF4003DO-41 C11100N

100VMKS2

VP15V5

VN15V5

VN13V5_F1

VN9V_F2

VP5V

VP3V3

VP12V

VN35V6

R34K70W25MF

TR2

BC546BTO-92

R66K80W25MF

C3122UF63VYK

VP5V

DGND

AC_PRES*

R9

1K0 0W25MF

TR4BC546BTO-92

C4722P100VN150

DGND

R81K00W25MF

C14100N100VMKS2

R10

1K0 0W25MFC15

100N100VMKS2

VN35V6

5V_NFB

3V3_NFB

3V3_NFB

5V_NFB

C5122N100VMKS2

L6

6U8 2.1A 8RHT2

L7

6U8 2.1A 8RHT2

L5

33U 1.17A 8RHT2

L3

33U 1.17A 8RHT2

L433U 1.17A 8RHT2

VN35V6

VN35V6

VN13V5_F1

C2922UF63VYK

MAINS SUPPLYFOR EXT. AUDIOSUPPLY TX

C4922N100VMKS2

R14

R29

82K 0W25MF

NF

NFB (To Controller E/A)

(NFB From PSU Outputs)

G

R

E

Y

4

D

K

G

R

E

Y

3

L

T

G

R

E

Y

2

B

L

U

E

1

CON2WAGO256

G

R

E

Y

2

G

R

E

Y

1

CON4WAGO256

G

R

E

E

N

1

CON3WAGO256

G

R

E

Y

W

H

I

T

E

B

L

A

C

K

B

L

U

E

R1647K0W25MF

C531000UF16VYXF

C8100N100VMKS2

QTY DESCRIPTIONPART No. NOTESITEM

ITEM1 1 Clip For SW Profile HeatsinkF006

ITEM3 2 Fuseholder Cover For 20mm FuseholderF022

ITEM2 1 Sil Pad For TO-220 HS InsulatorF082

ITEM4 1 Blank PCB DV78 PSUL959PB

C37100UF50VYXF

C38100UF50VYXF

C57470UF25VYXF

C3022UF63VYK

C43470UF25VYK

NF

NF

12345678

CON6

AMPCTNF

R32

C5

AGND

DGND

LK2

ITEM5 1 Earth Lead Assy 75MM8M101 SAFETY EARTH WIRE FROM IEC INLET SK1 TO METAL CHASSIS

L2

LK1

0R0 0W25 MF

D5

1N4148DO-35

1

FIX2

Dia 3.5mm

1

FIX4

Dia 3.5mm

1

FIX5

Dia 3.5mm

7

2

3

16T

16T

22T

14T

10T8

1 11

10

9

12

4

41T

41T

5

6

S

C

R

TX2Ferrite Switch ModeL925TX

DGND

FD1

FD2

TOOL1

TOOL2

TOOL3

TOOL4

C271000UF63VYK

C281000UF63VYK

C48

1N0100VCER

TR5BD179TO-126

R1210K0W25MF

D6

31DQ10 DO-201AD

D7

31DQ06 DO-201AD

D8

UF5406DO-201AD

R21470R0W25MF

C32470pF1kVDE

DZ4BZX79C5V6DO-35

1

FIX1

Dia 3.5mm

1

FIX3

Dia 3.5mm

1

FIX6

Dia 3.5mm

NF

NF

R1710R0W25MF

TR1BC547BTO-92

DZ1

BZX79C2V7DO-35

R122K0W25MF

R2

220R0W25MF

HS1BSW38-210.2C/W

NOTE TRANSFORMER TX1 IS MOUNTED ONTHE CHASSIS AND CONNECTED TO THE PSUPCB BY CON2,3,4. TX1 IS SHOWN ABOVE FOR CIRCUIT OPERATION

NF

R331K00W25MF

USED TO SECURE TRANSFORMER CABLES TO PCB NEAR CON1

NF

ITEM7 2 Rivet CopperHP007S RIVETS TO SECURE IEC INLET TO PCB

DZ2BZX79C10VDO-35

DZ3BZX79C3V3DO-35

NF

C52330P100VN750

R300R223WSPRX

1.0Production release02/07/03KAL03_E1951.1Make CON1 fitted (used in DV29)22/04/04PG04_E046

ITEM6 1 Cable Tie 100MM X 2.5MMF044

DV29 DVD player PSU board L959AY issue 1.1.1

Designator Part DescriptionC1 2J410 Capacitor SM 0805 X7R Ceramic 10% 50V 100NC2 2J410 Capacitor SM 0805 X7R Ceramic 10% 50V 100NC3 2J410 Capacitor SM 0805 X7R Ceramic 10% 50V 100NC4 2J410 Capacitor SM 0805 X7R Ceramic 10% 50V 100NC5 2MA610 Capacitor Surface Mount Electrolytic 10UF 50V 6.3 X 4.5MMC6 2MA610 Capacitor Surface Mount Electrolytic 10UF 50V 6.3 X 4.5MMC7 2MA610 Capacitor Surface Mount Electrolytic 10UF 50V 6.3 X 4.5MMC8 2L210 Capacitor SM 0805 NPO Ceramic 5% 100V 1N0C9 2L210 Capacitor SM 0805 NPO Ceramic 5% 100V 1N0C10 2L210 Capacitor SM 0805 NPO Ceramic 5% 100V 1N0C11 2L210 Capacitor SM 0805 NPO Ceramic 5% 100V 1N0CON1 8K8616 Con 1.0MM Horiz FFC 16WAY 52807 SeriesD1 3AS16W Diode Surface Mount Small Signal BAS16W SOT-23 PackageD2 3AS16W Diode Surface Mount Small Signal BAS16W SOT-23 PackageD3 3AS16W Diode Surface Mount Small Signal BAS16W SOT-23 PackageD4 3AS16W Diode Surface Mount Small Signal BAS16W SOT-23 PackageDISP1 B1014 Display DV88IC1 5H6312 IC VFD Driver PT6312LQ SM LQFP-44 packageLED1 3D007 LED 3.1mm Green SLR-37MG3TLED2 3D010 LED SM Red SML-010LTLED3 3D007 LED 3.1mm Green SLR-37MG3TLED5 3D006 LED 3mm Red/Green Tri-Colour L-93WEGWR1 1M133 Resistor 0805 Surface Mount 0.125W 1% 330RR2 1M133 Resistor 0805 Surface Mount 0.125W 1% 330RR3 1M133 Resistor 0805 Surface Mount 0.125W 1% 330RR4 1M122 Resistor 0805 Surface Mount 0.125W 1% 220RR5 1M118 Resistor 0805 Surface Mount 0.125W 1% 180RR6 1M139 Resistor 0805 Surface Mount 0.125W 1% 390RR8 1M310 Resistor 0805 Surface Mount 0.125W 1% 10KR9 1M310 Resistor 0805 Surface Mount 0.125W 1% 10KR10 1M247 Resistor 0805 Surface Mount 0.125W 1% 4K7R11 1M356 Resistor 0805 Surface Mount 0.125W 1% 56KR13 1M310 Resistor 0805 Surface Mount 0.125W 1% 10KR14 1M310 Resistor 0805 Surface Mount 0.125W 1% 10KR15 1M310 Resistor 0805 Surface Mount 0.125W 1% 10KRX1 B2109 IR Receiver Module Kodenshi KSM-902TM1NSW1 A1511 Switch Tact Low Profile No Gnd PinSW2 A1511 Switch Tact Low Profile No Gnd PinSW3 A1511 Switch Tact Low Profile No Gnd PinSW4 A1511 Switch Tact Low Profile No Gnd PinSW5 A1511 Switch Tact Low Profile No Gnd PinSW6 A1511 Switch Tact Low Profile No Gnd PinSW7 A1511 Switch Tact Low Profile No Gnd PinSW8 A1511 Switch Tact Low Profile No Gnd PinSW9 A1511 Switch Tact Low Profile No Gnd PinTR2 4D10KN Digital Transistor MMUN2211LT1 SOT23 PackageTR3 4A849B Transistor BC849B SOT23 PackageTR4 4A849B Transistor BC849B SOT23 PackageTR5 4D10KP Digital Transistor MMUN2111LT1 SOT23 Package

ISSUE

DRAWING NO.

DRAWING TITLE

DATE

Filename:


L971C1.Prj

DV29 MAIN BOARD TOP LEVEL

Contact Engineer: L971C124-Aug-2004INITIALS


Notes:

Contact Tel: (01223) 203270Peter Gaggs


Cambridge CB5 9QRWaterbeach

A2

MUTE*

ML_8740_0MCMD

ML_8740_2

FSEL0

ML_8740_1

ENABLE_AV16/9

GAIN_SCALING

SERIAL_RXSERIAL_TX

IRRCV

SPDIF

ADAT1ADAT2

ADAT0

ABCLKALRCLK

CLK27M_VADDISMCLK_VADDIS

RESET*

PSUFS0PSUFS1

CLK_27M_VIDVSYNC*HSYNC*

VIDP[0..19]

REM_BUS_PREM_BUS_N

9190INT*

FSEL1

PROG/INT*DDC_SDADDC_SCL

SDASCL

CEC

HDMI_RESET*

MUTE_RGB

L967C2L971C2.sch

FSEL0


MCLK_DAC0

MCLK_DAC1

MCLK_DAC2

ABCLKALRCLK

ABCLK_DAC0

ABCLK_DAC1

ABCLK_DAC2

ALRCLK_DAC0

ALRCLK_DAC1

ALRCLK_DAC2

PSUCLK

PSUFS0PSUFS1

MUTE*

MUTE_BUF*

FSEL1

MCLK_HDMI

ABCLK_HDMI

ADAT0ADAT1

ADAT_DAC0

ADAT_DAC1

ADAT2

ADAT_DAC2

SPDIF

ENABLE_AV

L967C3L971C3.Sch

ALRCLK_DAC0

ADAT_DAC0ABCLK_DAC0

MCLK_DAC0

MDMCML_8740_0

RESET*GAIN_SCALING

MUTE_BUF*

AC_PRES* SCART_LEFTSCART_RIGHT

L967C4L971C4.Sch

ALRCLK_DAC1

ADAT_DAC1ABCLK_DAC1

MCLK_DAC1

MDMCML_8740_1RESET*

CENTRE_OUTSUB_OUT

L967C5L971C5.Sch

ALRCLK_DAC2

ADAT_DAC2ABCLK_DAC2

MCLK_DAC2

MDMCML_8740_2RESET*

CENTRE_OUTSUB_OUT

L967C6L971C6.Sch

SCART_LEFTSCART_RIGHT

SCART_BLUESCART_GREENSCART_REDSCART_COMPOSITE

ENABLE_AV16/9

L967C8L971C8.Sch

PSUCLK

AC_PRES*

L967C10L971C10.Sch

HDMI_RESET*

9190_INT*

SCLSDA

VIDP[0..19]VSYNC*HSYNC*

CLK27M_VID

MCLK_HDMI

SPDIF

PROG/INT*

DDC_SCLDDC_SDA

ADAT0ADAT1ADAT2

ALRCLKABCLK_HDMI

CEC

HSYNCD*

L967C11L971C11.Sch

FSEL0FSEL1PSUFS0PSUFS1

ADAT0ADAT1ADAT2ABCLKALRCLKSPDIF

MUTE*


GAIN_SCALINGRESET*MDMCML_8740_0ML_8740_1ML_8740_2

PSUCLK

AC_PRES*

ADAT_DAC0ABCLK_DAC0ALRCLK_DAC0MCLK_DAC0

MUTE_BUF*

MDMC



ADAT0ADAT1ADAT2

ABCLK_HDMIALRCLK

MCLK_HDMI

RESET*

9190INT*PROG/INT*DDC_SDADDC_SCLSDASCL

VIDP[0..19]HSYNC*VSYNC*CLK_27M_VID

16/9ENABLE_AV

SCART_LEFTSCART_RIGHT

SCART_COMPOSITESCART_REDSCART_GREENSCART_BLUE

COMPOSITEYUVSVID_YSVID_C

MDMC

RESET*

RESET*

IRRCV

SERIAL_TXSERIAL_RX

REM_BUS_PREM_BUS_N

VADDIS VSHEET 2

CLOCKSSHEET 3

DAC L&RSHEET 4

DAC LS&RSSHEET 5

DAC C & SUB

SHEET 6

HDMISHEET 11

VIDEO ENCODER

SHEET 7

SCARTSHEET 8

COMMS, VIDEO OUTSHEET 9

POWERSHEET 10

CEC

PG 1.0

ENABLE_AV

VUYCOMPOSITE

SVID_YSVID_C

REM_BUS_PREM_BUS_N

IRRCVENABLE_AV

SERIAL_RXSERIAL_TX

MUTE_RGB

L967C9L971C9.Sch

VIDP[0..19]HSYNCD*VSYNC*CLK27M_VID

SDASCLRESET*

COMPOSITE

SCART_COMPOSITE

SVID_YSVID_C

Y

SCART_GREEN

U

SCART_BLUE

V

SCART_RED

L967C7L971C7.Sch

04_E121

HDMI_RESET*

09-08-04

ITEM100 1 Blank PCB DV29 Main BoardL971PB

Production release

MUTE_RGB

HSYNCD*

NOTES ON PCB VARIANTS

L971AY

DV29

Part number

Product

Audio output channels

AUX PSU fitted

Precision parts on component video output

Transformer on digital COAX output

6

YES

YES

YES

RS232 YES

DV79

6

NO

NO

NO

YES

DV75

2

NO

NO

NO

NO

When updating the design, modify this schematic first. The PCB is updated from this schematic.Also update the DV79 schematic and DV75 schematic, and get the DV79 and DV75 BOMs from their own schematics

L973AYL974AY

ISSUE

DRAWING NO.

DRAWING TITLE

DATE

Filename:


L971C2.sch

DV29 MAIN VADDIS V



Notes:




A1

ISSUE

DRAWING TITLE

DATE

Filename:


L971C2.sch

DV29 MAIN VADDIS V

Contact Engineer: 24-Aug-2004

INITIALS


Notes:


A & R Cambridge Ltd.Pembroke AvenueWaterbeach

RAMADD0RAMADD1RAMADD2RAMADD3RAMADD4RAMADD5RAMADD6RAMADD7RAMADD8RAMADD9RAMADD10

RAMBA0RAMBA1

RAMADD0RAMADD1RAMADD2RAMADD3RAMADD4RAMADD5RAMADD6RAMADD7RAMADD8RAMADD9RAMADD10

RAMBA1RAMBA0

DGND

+3V3D

+1V8D

DGND

+3V3D

VDDP_A

VDD_PLL

+3V3D

DGND

RAMDAT0RAMDAT1RAMDAT2RAMDAT3RAMDAT4RAMDAT5RAMDAT6RAMDAT7RAMDAT8RAMDAT9RAMDAT10RAMDAT11RAMDAT12RAMDAT13RAMDAT14RAMDAT15RAMDAT16RAMDAT17RAMDAT18RAMDAT19RAMDAT20RAMDAT21RAMDAT22RAMDAT23RAMDAT24RAMDAT25RAMDAT26RAMDAT27RAMDAT28RAMDAT29RAMDAT30RAMDAT31

RAMDAT31

RAMDAT0RAMDAT1RAMDAT2RAMDAT3RAMDAT4RAMDAT5RAMDAT6RAMDAT7RAMDAT8RAMDAT9RAMDAT10RAMDAT11RAMDAT12RAMDAT13RAMDAT14RAMDAT15RAMDAT16RAMDAT17RAMDAT18RAMDAT19RAMDAT20RAMDAT21RAMDAT22RAMDAT23RAMDAT24RAMDAT25RAMDAT26RAMDAT27RAMDAT28RAMDAT29RAMDAT30

RAMDQMRAMCS*RAMRAS*RAMCAS*RAMWE*RAMCKEPCLK

RAMDQM

RAMCS*RAMRAS*RAMCAS*RAMWE*

PCLKRAMCKE

DGND

NF

NF

RAMADD7

RAMADD5RAMADD6

RAMADD1RAMADD0

RAMADD8

RAMADD10

RAMADD9

RAMDAT27

RAMDAT20

RAMDAT5

RAMDAT21

RAMDAT26

RAMDAT9

RAMDAT6

RAMDAT24

RAMBA1RAMBA0

RAMADD11

RAMDAT8

RAMDAT7

RAMDAT22

RAMDAT25

RAMDAT23

RAMDAT18

RAMDAT31RAMDAT30

RAMDAT16RAMDAT17

RAMDAT29

RAMDAT28

RAMDAT19

RAMADD11

FRAMADD7

FRAMADD5FRAMADD6

FRAMADD1FRAMADD0

FRAMADD8

FRAMADD10

FRAMADD9

FRAMDAT27

FRAMDAT20

FRAMDAT5

FRAMDAT21

FRAMDAT26

FRAMDAT9

FRAMDAT6

FRAMDAT24

FRAMBA1FRAMBA0

FRAMADD11

FRAMDAT8

FRAMDAT7

FRAMDAT22

FRAMDAT25

FRAMDAT23

FRAMDAT18

FRAMDAT31FRAMDAT30

FRAMDAT16FRAMDAT17

FRAMDAT29

FRAMDAT28

FRAMDAT19

+3V3D

DGND

FRAMADD5FRAMADD6FRAMADD7FRAMADD8FRAMADD9FRAMADD11FRAMDAT8FRAMDAT9

FRAMDAT5FRAMDAT6FRAMDAT7FRAMBA0FRAMBA1FRAMADD10FRAMADD0FRAMADD1

RAMADD2 FRAMADD2

FRAMADD2

RAMDAT10 FRAMDAT10

FRAMDAT10

RAMDAT11 FRAMDAT11

FRAMDAT11RAMDAT4

RAMDAT3

RAMDAT12 NF (Intel 64Mb)

PWR_ON_RESET*

FLASHA19FLASHA19

FRAMDAT3

FRAMDAT3

FLASHA21

FLASHA21

Use these resistors to configure for Intel/AMD 8Mbit, 16Mbit, 32Mbit or 64Mbit devicesIntel 32Mbit is used for DV79

RAMADD4 FRAMADD4

FRAMADD4+3V3D

PNVMCE*

PNVMCE*

RAMADD3 FRAMADD3

FRAMADD3

FRAMDAT31FRAMDAT29FRAMDAT27FRAMDAT25FRAMDAT23FRAMDAT21FRAMDAT19FRAMDAT17

FRAMDAT30FRAMDAT28FRAMDAT26FRAMDAT24FRAMDAT22FRAMDAT20FRAMDAT18FRAMDAT16

SDRAM

FLASH

ZORAN VADDIS V

+3V3D

DGND+1V8D

DGND VADDIS DECOUPLING

+3V3D

DGND

SDRAM DECOUPLING

+3V3D

DGND

FLASH DECOUPLING

ATDD0ATDD1ATDD2ATDD3ATDD4ATDD5ATDD6ATDD7ATDD8ATDD9ATDD10ATDD11ATDD12ATDD13ATDD14ATDD15ATDMARQATDIOW*ATDIOR*ATIORDYATDMACK*ATINTRQATDA0ATDA1ATDA2ATCS0*ATCS1*

Audio master clock (input)Can be configured as an output for testing

AMCLK_OUT

AMCLK_OUT

PWR_ON_RESET*

DGND

+3V3D

To enable Vaddis PLL for testing:Make PLLCFGA lowIsolate AMCLK from GCLKALink GCLKA to GCLKPConnect AMCLK_OUT to AMCLKAMCLK is now an output and the Vaddis PLL is enabled

Fit Link to boot from DEBUG UART

MUTE*MUTE*

ML_8740_0MCMD

ML_8740_2

FSEL0

ML_8740_1ML_8740_1ML_8740_0MCMD

ML_8740_2

FSEL0

ENABLE_AV16/9

GAIN_SCALING

ENABLE_AV16/9

GAIN_SCALING

BOOT SELECT

+3V3D

Not Fitted

+3V3D

DGND

EJTAG DEBUG

EEPROM MEMORYSERIAL_RXSERIAL_TX

SDASCL

EJTRSTEJTDIEJTDOEJTMSEJTCK

SERIAL PORT IRRCV

IRRCV

SPDIF

ADAT1ADAT2

ADAT0

ABCLK

ALRCLKALRCLK

ABCLK

ADAT0

ADAT2ADAT1

SPDIF

DIGITAL AUDIO

CLOCKS

PSUFS0PSUFS1

ATRESET*

XATRESET*

ATE can use test pad to put in debug boot mode

DGND

DGND

DGND

DGND

DGND

address

dataaddress data

+3V3D

DGND

Decoupling caps on bottom of board

+1V8D

DGND

Decoupling caps on bottom of board

L200 120R@100MHz

L201 120R@100MHz

+3V3D

+1V8D

C248

10UF50VYK

C208100N16V0603

DGND

C250

10UF50VYK

C210100N16V0603

63RP214C 100R1 8RP214A 100R

2 7RP214B 100R

A0 1A1 2A2 3SDA5

SCL6WP7

IC204A

24LC08BT/SNSO-8

DGND

DGND

+3V3D

123456789

10111213141516

CON201

HARWINM20-972

1

8

RP215A4K762mW1206

2

7

RP215B4K762mW1206

6

3

RP215C4K762mW1206

5

4

RP215D4K762mW1206

NF NF

TR200MMUN2211LT1SOT-23

12

CON200

HARWINM20-973

NF

CLK27M_VADDIS

MCLK_VADDIS

NF

C223

100N16V0603

C240

100N16V0603

C239

100N16V0603

C238

100N16V0603

C237

100N16V0603

C236

100N16V0603

C235

100N16V0603

C234

100N16V0603

C233

100N16V0603

C232

100N16V0603

C231

100N16V0603

C229

100N16V0603

C227

100N16V0603

C225

100N16V0603

C221

100N16V0603

C222

100N16V0603

C224

100N16V0603

C226

100N16V0603

C228

100N16V0603

C230

100N16V0603

V

D

D

1

DQ0 2

V

D

D

Q

3

DQ1 4DQ2 5

V

S

S

Q

6

DQ3 7DQ4 8

V

D

D

Q

9

DQ5 10DQ6 11

V

S

S

Q

1

2

DQ7 13

V

D

D

1

5

DQM016

WE17CAS18RAS19CS20

BA022BA123

A10/AP24

A025A126A227

DQM228

V

D

D

2

9

DQ16 31

V

S

S

Q

3

2

DQ17 33DQ18 34

V

D

D

Q

3

5

DQ19 36DQ20 37

V

S

S

Q

3

8

DQ21 39DQ22 40

V

D

D

Q

4

1

DQ23 42

V

D

D

4

3

V

S

S

4

4

DQ24 45

V

S

S

Q

4

6

DQ25 47DQ26 48

V

D

D

Q

4

9

DQ27 50DQ28 51

V

S

S

Q

5

2

DQ29 53DQ30 54

V

D

D

Q

5

5

DQ31 56

V

S

S

5

8

DQM359

A360A461A562A663A764A865A966

CKE67CLK68

DQM171

V

S

S

7

2

DQ8 74

V

D

D

Q

7

5

DQ9 76DQ10 77

V

S

S

Q

7

8

DQ11 79DQ12 80

V

D

D

Q

8

1

DQ13 82DQ14 83

V

S

S

Q

8

4

DQ15 85

V

S

S

8

6

A11 (NC)21

IC203

IC MEM SDRAM 512KX32BITX4 7NS

C217100N16V0603

R2251K00W0630603

C212100N16V0603

C213100N16V0603

C214100N16V0603

C215100N16V0603

C220100N16V0603

1 8RP200A 56R2 7RP200B 56R

63RP200C 56R54RP200D 56R

1 8RP201A 56R2 7RP201B 56R

63RP201C 56R54RP201D 56R

1 8RP202A 56R2 7RP202B 56R

63RP202C 56R54RP202D 56R

1 8RP203A 56R2 7RP203B 56R

63RP203C 56R54RP203D 56R

1 8RP204A 56R2 7RP204B 56R

63RP204C 56R54RP204D 56R

1 8RP205A 56R2 7RP205B 56R

63RP205C 56R54RP205D 56R

1 8RP206A 56R2 7RP206B 56R

63RP206C 56R54RP206D 56R

1 8RP207A 56R2 7RP207B 56R

63RP207C 56R54RP207D 56R

1 8RP208A 56R2 7RP208B 56R

63RP208C 56R54RP208D 56R

GND 7

VCC 14

IC200E74HCT125DSO-14

C219

100N16V0603

+5VD

DGND

GND 4

VCC 8

IC204B24LC08BT/SNSO-8

C218

100N16V0603

+3V3D

DGND

V

C

C

RST

G

N

D

IC201

LM809M3-2.63SOT-23

C207

100N16V0603

+3V3D

DGND

RESET*

PWR_ON_RESET*

RESET

CLK27M_VADDIS

MCLK_VADDIS

54RP209D 33R63RP209C 33R

2 7RP209B 33R1 8RP209A 33R

54RP210D 33R63RP210C 33R

2 7RP210B 33R1 8RP210A 33R1 8RP211A 33R2 7RP211B 33R

63RP211C 33R54RP211D 33R

1 8RP212A 33R2 7RP212B 33R

63RP212C 33R54RP212D 33R

DGND

+5VD

ATRESET*

+5VD

DGND

Design note: Some Vaddis GPIO initialise as o/p high, some as o/p low.MUTE must use one that initialises as o/p low. Currently on pin T2

PSUFS0PSUFS1

FPDOUT

FRONT PANEL

2 3

1

IC200A 74HCT125DSO-14

5 6

4

IC200B 74HCT125DSO-14

9 8

1

0

IC200C 74HCT125DSO-14

DGND

DGND

DGND

DGND

FPDINFPCLKFPSEL

12 11

1

3

IC200D74HCT125DSO-14

DGND

C200

47P100V0805

C205

47P100V0805

R206

56R0W125 0805

R207

56R0W125 0805

R208

56R0W125 0805

R209

56R0W125 0805

R210

56R0W1250805R222

0R00W1250805

R223

0R00W1250805

R219

0R00W1250805

R224

0R00W1250805

R250

5K60W1250805

R226

1K00W1250805

R227

1K00W1250805

R228

1K00W1250805

R2344K70W1250805

R2324K70W1250805

R2334K70W1250805

R2374K70W1250805

R20410K0W1250805

R251

33R0W1250805

R2354K70W1250805

R2364K70W1250805

R231

1K00W1250805

R230

1K00W1250805

R229

1K00W1250805

R2200R00W1250805

R2210R00W1250805

FSEL1

DGND

DGND

PNVMR/B*

R252

56R0W125 0805

PNVMR/B* NF(AMD)

R253

56R0W125 0805

RAMDAT4 NF(AMD 16Mb)

HS202

3319B+T410-0120.9C/W

P242

R218

100R0W125 0805

R254

100R0W125 0805

R255

100R0W125 0805

C253

100UF10VYXF

C252

100UF10VYXF

C254

100UF10VYXF

NF

R249 33R 0805R248 33R 0805R247 33R 0805R246 33R 0805R245 33R 0805R244 33R 0805R240 82R 0805R243 22R 0805R239 82R 0805R242 22R 0805R241 22R 0805R238 82R 0805

+3V3D

P243P244P245P246P247P248P249P250P251P252P253P254P255P256P257P258P259P260P261P262P263P264P265P266P267P268

P269P270

PR220PR221PR222PR223PR224PR225PR226PR227PR228PR229PR230PR231PR232PR233PR234PR235PR236PR237PR238PR239PR240PR241PR242PR243PR244PR245PR246PR247PR248PR249PR250PR251

PR200PR201

PR202PR203

PR204PR205PR206PR207

PR208PR209PR210PR211PR212PR213PR214PR215PR216PR217PR218

PR219

PF224PF225PF226PF227PF239PF240PF241PF242




PF228PF229PF230PF231PF232PF233

PF234PF235

PF236PF237

PF238

P271

P273

PF243

PR252

P275

P274

P277

P276

P279P278

P282P201

P284P285

P286

NOTE: JTAG port is for software debug only. Boundary scan is not supported

P287

P288P289

P290

P291P292P293

P294

P295

P296

PJ203

PJ205PJ200

PR253

P200

P204

P203

P202

C245

1N050V0603

C241

1N050V0603

C243

1N050V0603

C246

1N050V0603

C247

1N050V0603

C242

1N050V0603

C244

1N050V0603

+3V3D

CLK_27M_VIDVSYNC*HSYNC*

VIDP[0..19]VIDP[0..19]

VIDP0VIDP1VIDP2VIDP3VIDP4VIDP5VIDP6VIDP7VIDP8VIDP9VIDP10VIDP11VIDP12VIDP13VIDP14VIDP15VIDP16VIDP17VIDP18VIDP19

12345678910111213141516171819202122232425262728293031323334353637383940

CON203

DubilierC3

XATRESET*

DGND

ATDD7ATDD8ATDD6ATDD9ATDD5ATDD10ATDD4ATDD11ATDD3ATDD12ATDD2ATDD13ATDD1ATDD14ATDD0ATDD15

ATDMARQ

ATDIOW*

ATDIOR*

ATIORDY

ATDMACK*

ATINTRQ

ATDA1

ATDA0ATDA2ATCS0*ATCS1*

DRIVE

12345678910111213141516

CON202

MOLEX52806 DGND

FPDOUTXFPCLKXFPSELXFPDIN

IRRCVREM_BUS_P

FPDOUT

XFPDIN

XFPCLK

XFPSEL

IRRCV

FRONT PANEL

REM_BUS_P

REM_BUS_NREM_BUS_N

+5V_DISPLAY

-19V_OUT-13V5_OUT-9V_OUT

9190INT*9190INT*FSEL1

PROG/INT* PROG/INT*

DDC_SDA DDC_SDA

DDC_SCL DDC_SCL

SDASCL

CEC CEC

P239

RESET*

PV200PV201PV202PV203PV204PV205PV206PV207PV208PV209PV210PV211PV212PV213PV214PV215PV216PV217PV218PV219

PV220PV221PV222

PV223PV224PV225PV226PV227PV228PV229PV230PV231PV232PV233PV234PV235PV239PV240PV241PV242PV243PV244PV245

PV238PV237PV236

NVMDA0N3NVMDA1P4

NVMDA2P3NVMDA3R3NVMDA4R4NVMDA5P1NVMDA6P2NVMDA7N4NVMR/BN1NVMCEL4

NVMREM1NVMWPN2NVMWEM2NVMALEL1NVMCLEL2

PCLKU12RAMCKEV11RAMWEY14RAMCASW13RAMRASY13RAMCSY12RAMDQMW14RAMBA1Y11RAMBA0W11

RAMADD0Y9RAMADD1W8RAMADD2Y8RAMADD3Y7RAMADD4W7RAMADD5V8RAMADD6U8RAMADD7V9RAMADD8U9RAMADD9V10

RAMDAT0W18RAMDAT1Y18RAMDAT2W17RAMDAT3Y17RAMDAT4W16RAMDAT5Y16RAMDAT6W15RAMDAT7Y15RAMDAT8V14RAMDAT9U14RAMDAT10V15RAMDAT11V16RAMDAT12V17RAMDAT13U17RAMDAT14V18RAMDAT15U18RAMDAT16W6RAMDAT17Y6RAMDAT18W5RAMDAT19Y5RAMDAT20W4RAMDAT21Y4RAMDAT22Y3RAMDAT23Y2RAMDAT24W2

RAMDAT25W3RAMDAT26V4RAMDAT27U4RAMDAT28V5RAMDAT29V6RAMDAT30U6RAMDAT31V7

RAMADD10W9RAMADD11U10

ATDD0D2ATDD1C2ATDD2A1ATDD3B2ATDD4D3ATDD5C3ATDD6D4ATDD7C4ATDD8A4ATDD9B4ATDD10A3ATDD11B3ATDD12A2ATDD13E4ATDD14E3ATDD15F4ATDMARQB1ATIOWC1ATIORD1ATIORDYF3ATDMACKE2ATINTRQE1ATDA0G3ATDA1F1

ATDA2F2ATCS0G1ATCS1G2

DAC_A_B/U E17DAC_B_R/V F17DAC_C_G/Y F18

DAC_D_CVBS G17

RSET D16VREF D17

COSYNC K17

VIDP_2 L19VIDP_3 L20VIDP_4 L18VIDP_5 M19VIDP_6 M20VIDP_7 M18

VSYNC R17HSYNC T20

VCLK T19VCLKx2 K18

AMCLK E19ALRCLKI E20

ABCLKI F20ALRCLKO F19

ABCLKO G19AIN0 C17AIN1 C16

AOUT0 J17AOUT1 J19AOUT2 H20AOUT3 H19AOUT4 G20

SPDIF J20

XOC14GCLKPA14GCLKAB15RESETB14

PLLCFGA J3PLLCFGP J2

FPCDOUT G4FPCDIN H4FPCCLK H3FPCSTB H1

IRRCV H2

MODRI W19MODDCD U20MODDSR V20MODCTS V19MODDTR U19MODRTS Y20MODRD Y19MODTD W20

DUPRD T3DUPTD U3

BOOTSEL0 C10BOOTSEL1 D10

SPIDATO C13SPICLK D13

I2CDAT B17I2CCLK A17

SERADC0 C15SERADC1 B16

EJTRST K3EJTDI K4

EJTDO K2EJTMS K1EJTCK J1

GPAIO0 B12

V

D

D

P

E

5

V

D

D

P

F

5

V

D

D

P

H

5

V

D

D

P

K

1

6

V

D

D

P

K

5

V

D

D

P

N

5

V

D

D

P

R

5

V

D

D

P

E

7

V

D

D

P

T

7

V

D

D

P

U

7

V

D

D

P

T

9

V

D

D

P

E

1

0

V

D

D

P

T

1

1

V

D

D

P

U

1

1

V

D

D

P

E

1

2

V

D

D

P

U

1

3

V

D

D

P

E

1

5

V

D

D

P

M

1

6

V

D

D

P

R

1

6

V

D

D

P

U

1

6

V

D

D

P

T

1

5

V

D

D

C

E

1

3

V

D

D

C

L

1

7

V

D

D

C

V

1

2

V

D

D

C

W

1

0

V

D

D

C

L

5

V

D

D

_

D

A

C

A

1

8

V

D

D

A

A

1

3

V

D

D

A

D

C

A

1

6

V

D

D

P

-

A

D

1

2

G

N

D

P

T

5

G

N

D

P

T

6

G

N

D

P

T

8

G

N

D

P

T

1

0

G

N

D

P

T

1

2

G

N

D

P

T

1

3

G

N

D

P

V

1

3

G

N

D

P

T

1

4

G

N

D

P

U

1

5

G

N

D

P

T

1

6

G

N

D

P

J

9

G

N

D

P

K

9

G

N

D

P

L

9

G

N

D

P

M

9

G

N

D

P

L

1

0

G

N

D

P

K

1

1

G

N

D

P

K

1

2

G

N

D

P

-

A

2

H

1

6

G

N

D

P

J

1

1

G

N

D

P

J

1

2

G

N

D

P

J

1

0

G

N

D

P

K

1

0

G

N

D

C

E

1

4

G

N

D

C

L

1

6

G

N

D

C

W

1

2

G

N

D

C

Y

1

0

G

N

D

C

M

5

G

N

D

A

A

1

2

G

N

D

A

D

C

A

1

5

G

N

D

D

A

C

-

P

C

1

9

G

N

D

D

A

C

-

S

B

B

1

9

G

N

D

D

A

C

-

D

B

2

0

V

D

D

P

-

A

2

G

1

6

DAC_E_Y G18DAC_F_C H17

VIDP_1 K20VIDP_0 K19

VIDP_8 M17VIDP_9 N20

VIDP_10 N19VIDP_11 N18VIDP_12 N17VIDP_13 P20VIDP_14 P19VIDP_15 P18

VIDP_19 R18VIDP_18 R19VIDP_16 P17VIDP_17 R20

NVMR/B1M3NVMCE1L3

NVMCDM4

PNVMCEY1PNVMR/BW1

SERADC2 D15

PWM C9

BOOTSEL2 D11

HD0B7HD1A7HD2B8HD3A8HD4B9HD5A9HD6B10HD7A10HA0B5HA1A5HA2B6HA3A6HWRC6HRDD6HCSD7HIRQC7HACKC5

HACK1D5HCS1D8HIRQ1C8

PLLSEL D9

SPIDATI B13

TESTMODE D14

GPCIO6 J4GPCIO7 B18GPCIO8 C18GPCIO9 V1

GPCIO10 V2GPCIO11 U2GPCIO12 U1GPCIO13 T1GPCIO14 T2GPCIO15 R1GPCIO16 R2GPCIO17 B11GPCIO18 C11GPCIO19 C12GPCIO20 V3

V

D

D

P

-

A

U

5

V

D

D

C

E

9

V

D

D

_

D

A

C

A

1

9

V

D

D

_

D

A

C

A

2

0

G

N

D

C

E

8

G

N

D

D

A

C

-

D

C

2

0

G

N

D

D

A

C

-

D

D

2

0

G

N

D

A

A

1

1

G

N

D

P

L

1

1

G

N

D

P

L

1

2

G

N

D

P

M

1

0

G

N

D

P

M

1

1

G

N

D

P

M

1

2

IC202

ZR36750BGA-316

C201

100N16V0603

C202

100N16V0603

C204

100N16V0603

C206

100N16V0603

C209

100N16V0603

C211

100N16V0603

C216

100N16V0603

C249

100N16V0603

C251

100N16V0603

DGND

+3V3D

C203

100N16V0603

C264

100N16V0603

Near ATAPI conn

+3V3D

DGND

+3V3D

DGNDOn bottom of board

+3V3D

DGND

SDRAM decoupling on bottom of board

R200 33R

RAMADD11

1 8RP216A 100R2 7RP216B 100R

63RP216C 100R54RP216D 100R

1 8RP217A 100R2 7RP217B 100R

63RP217C 100R54RP217D 100R

1 8RP218A 100R2 7RP218B 100R

63RP218C 100R54RP218D 100R

1 8RP219A 100R2 7RP219B 100R

63RP219C 100R54RP219D 100R

1 8RP220A 100R2 7RP220B 100R

63RP220C 100R54RP220D 100R

1 8RP213A 56R

2 7RP213B 56R

63RP213C 56R

54RP213D 56R

R201 100RR205 100R

HDMI_RESET* HDMI_RESET*

R202 22R 0603

C255

1N050V0603

C263

1N050V0603

C256

1N050V0603

C257

1N050V0603

C258

1N050V0603

C259

1N050V0603

C260

1N050V0603

C261

1N050V0603

C262

1N050V0603

A025A124

A223A322A421A520A619A718

A88A97A106A115A124A133A142A151

A1648

G

N

D

4

6

V

C

C

3

7

DQ0 29DQ1 31DQ2 33DQ3 35DQ4 38DQ5 40DQ6 42DQ7 44

DQ8 30DQ9 32

DQ10 34DQ11 36DQ12 39DQ13 41DQ14 43DQ15 45

VPP13OE28CE26

V

C

C

Q

4

7

WE11RP12

G

N

D

2

7

WP14

A1717A1816A1915A2010A219

IC205

TE28F160L967SWTSOP-48

NF(32Mb+)

MUTE_RGB MUTE_RGB

NOTE: Pin B9 is set HIGH to indicate that this version of hardware features the HSYNC delay circuit (see sheet 11)

R2034K70805

R2114K70805

DGND

+3V3DCONFIGURATION LINKS

P205

DV75

DV79/DV29

6CH*

PG 1.004_E121 09-08-04 Production release

ISSUE

DRAWING NO.

DRAWING TITLE

DATE

Filename:


L971C3.Sch

DV29 MAIN CLOCKS & SPDIF



Notes:




A2

DGND

DGND DGND

FSEL0

CLOCK GENERATOR

CLK27M_VADDIS

DGND

DGND

AUDIO CLOCK BUFFER

MCLK_VADDIS

MCLK_DAC0

MCLK_DAC1

MCLK_DAC2

ABCLK

ALRCLK

I2S BUFFER

DGND

1 8RP300A

100R 1206

2 7RP300B

100R 1206

ABCLK_DAC0

ABCLK_DAC1

ABCLK_DAC2

DGND

63 RP300C

100R 1206

ALRCLK_DAC0

ALRCLK_DAC1

ALRCLK_DAC2

PSUFS0PSUFS1

DGND

PSUCLK

I04I13

Y 5

Y 6

E7

I22I31I415I514I613I712

S011S110S29

IC305A

74HC151DSO-16

+3V3D

+3V3D

+3V3D

+3V3D

VCC 16

GND 8

IC305B

74HC151DSO-16

+3V3D

PSU CLOCK DIVIDER

PSUCLK SHOULD BE 44.1kHz OR 48kHz

Fs PSUFS1 PSUFS0 PSUCLK44.1kHz 0 0 44.1kHz48kHz 0 0 48kHz88.2kHz 0 1 44.1kHz96kHz 0 1 48kHz176.4kHz 1 0 44.1kHz192kHz 1 0 48kHzothers 1 1 OFF

DGND

PSUFS0PSUFS1

27MHz

Audio master clock frequency for different sample rates

Fs Master clock frequency FSEL1..044.1kHz 11.2896MHz (256 x Fs) 0048kHz 12.288MHz (256 x Fs) 0188.2kHz 22.5792MHz (256 x Fs) 1096kHz 24.576MHz (256 x Fs) 11176.4kHz 22.5792MHz (128 x Fs) 10192kHz 24.576MHz (128 x Fs) 11

DGND

MUTE* MUTE_BUF*

Spare clock buffer used to buffer mute control

C303

100UF10VYXF

C305

100UF10VYXF

C309

100N16V0603

C310

100N16V0603

C306

100N16V0603

C308

100N16V0603

P308

P309

P310

P314

P315

P316

P305

P306

P307

P311

P312P313

P318P319P320

P321

P323

P325

P326

P327

P329

P334

P335

P350

P351P352

P353

P354

P362P363

P355

Base resistor for TR401 here to reduce noise on MUTE_BUF*

X300

27MHzHC49

ITEM300 1 Pad Damping 7.5x6x3MM RubberE828AP Fit on one side of X300 (see assembly drawing)

C311

100N16V0603

CLK11D12

S

D

1

0

R

D

1

3

Q 9

Q 8

IC306B

74LVC74ADS0-14R301

100R 0603

R306

100R0603

+3V3D

FSEL1

9 8

1

0

IC307C74LVC125ADSO-14

R308

100R 0603

12 11

1

3

IC307D74LVC125ADSO-14

CLOCK DIVIDER

MCLK_HDMI

P301

OE1

A02Y0 18

A14Y1 16

A26Y2 14

A38Y3 12

IC301A

74LVC244APWTSSOP-20

OE19

A017Y0 3

A115Y1 5

A213Y2 7

A311Y3 9

IC301B

74LVC244APWTSSOP-20

R305

1K8 0603

P300

1 8RP301A

100R 1206

2 7RP301B

100R 1206

63 RP301C

100R 1206

ABCLK_HDMIP317P303

OE1

A02Y0 18

A14Y1 16

A26Y2 14

A38Y3 12

IC302A

74LVC244APWTSSOP-20

OE19

A017Y0 3

A115Y1 5

A213Y2 7

A311Y3 9

IC302B

74LVC244APWTSSOP-20

CLK3D2

S

D

4

R

D

1

Q 5

Q 6

IC304A

74LVC74ADS0-14

CLK11D12

S

D

1

0

R

D

1

3

Q 9

Q 8

IC304B

74LVC74ADS0-14

OE1

A02Y0 18

A14Y1 16

A26Y2 14

A38Y3 12

IC309A

74LVC244APWTSSOP-20

ADAT0ADAT1

DGND

1 8RP302A

100R 1206

63 RP302C

100R 1206

ADAT_DAC0

ADAT_DAC1

OE19

A017Y0 3

A115Y1 5

A213Y2 7

A311Y3 9

IC309B

74LVC244APWTSSOP-20

ADAT2

DGND

ADAT_DAC2R312

100R 0603

GND 10

VCC 20IC301C

74LVC244APWTSSOP-20

GND 10

VCC 20IC302C

74LVC244APWTSSOP-20

GND 10

VCC 20IC309C

74LVC244APWTSSOP-20

C318

100N16V0603

VCC 14

GND 7

IC304C

74LVC74ADS0-14

GND 7

VCC 14IC307E

74LVC125ADSO-14

C317

100N16V0603

R300

75R 0603

5 6

4

IC307B74LVC125ADSO-14

2 3

1

IC307A74LVC125ADSO-14

DGND

C312

100N16V0603

C313

100N16V0603

CLK3D2

S

D

4

R

D

1

Q 5

Q 6

IC306A

74LVC74ADS0-14

DGND

5 6

4

IC308B

74LVC125ADSO-14

9 8

1

0

IC308C

74LVC125ADSO-14

12 11

1

3

IC308D

74LVC125ADSO-14

2 3

1

IC308A

74LVC125ADSO-14

SPDIF COAX OUTPUT

GND 7

VCC 14IC308E

74LVC125ADSO-14

SPDIF

DGND DGND

DGND

DGND

DGND

1

3 4

2

L301

1000R @ 100MHz

DLW31S

DGNDEMC_GND

DGND

+5VDOPTICAL OUT

SPDIF_OUT

SPDIF_GND

DGND

+3V3D

D300BAT54SSOT-23

C304

100UF10VYXF

C307

100UF10VYXF

P328 P330

P322

P331

P332 P333 P337

P336

P324

V

C

C

2

G

N

D

3

I/P1

TX300JFJ1001-010010

R314

100R 0603

R311

100R 0603

R315

750R 0603

R316

750R 0603

R317

750R 0603

C320

100N16V0603

S

C

R

N

SKT300KUNMINGGOLD

1

24

IC303ASN74AHC1G00DBVRDBV-5

ENABLE_AV Ensures audio clock can be trurned off in standby mode

GND 3

VCC 5

IC303BSN74AHC1G00DBVR

DBV-5

C319

100N16V0603

XTI7

XTO8

FSEL14

V

S

S

2

6

V

S

S

3

1

1

V

S

S

1

2

V

D

D

2

5

V

D

D

3

1

2

V

D

D

1

1

MO1 3MO2 4

AO1 9AO2 10

SO1 13SO2 15

NC16

IC300SM8707EVSOP-16

C314

100N50V0805

C343

100N 50V0805

C316

100N50V0805

C322

100P100V0805

VCC 14

GND 7

IC306C

74LVC74ADS0-14

C324

100N16V0603

R323

100R 0603P341

P340

P342

P343

P345

P344

P347P346

P348

P356

P349P357

P358

P359

P360

P361P364

P366

P371

P365P368

P372

P374

P376

SPDIF_OP

DGND

P302

C325

100N16V0603

C326

100N16V0603

C327

100N16V0603

C328

100N16V0603

C329

100N16V0603

C330

100N16V0603

C331

100N16V0603

C332

100N16V0603

C333

100N16V0603

C334

100N16V0603

C335

100N16V0603

C336

100N16V0603

C337

100N16V0603

C338

100N16V0603

C339

100N16V0603

C340

100N16V0603

+3V3D

DGND

C341

100N16V0603

R318

120R0W1250805

R319

1K00W1250805

C323

10N50V0603

C300

27P100V0805

C301

27P100V0805

R313

56R0W125 0805

NFR320

0R00W1250805 NF

C321

47P100V0805NF

+3V3

REG300LM1086CS-3.3

TO-263

C342

100N16V0603

C302

100N16V0603

+3V3PLL+5VD

84

51 TX301

PCB Mount SMT7A29398

DGND

C315

100N 50V0805

P304

NF

R302

75R 0603

R303

75R 0603

R304

75R 0603

R307

75R 0603

R310

75R 0603

R321

75R 0603

R309

47R 0603

R322

47R 0603

DV29

DV79, DV75


ISSUE

DRAWING NO.

DRAWING TITLE

DATE

Filename:


L971C4.Sch

DV29 MAIN DAC L & R AUDIO



Notes:




A2

L400

120R@100MHz

+3V3A

C402

10UF35VSGET

C414

100N50V0805

+5VA

C400

10UF35VSGET

C406

100N50V0805

C407

100N50V0805

C408

100N50V0805

DGND

DGND

DGNDR416

10K0W1250805

+3V3_DAC0

+3V3_DAC0

C403

10UF35VSGET

C415

100N50V0805

C404

10UF35VSGET

C416

100N50V0805

DGND

ALRCLK_DAC0ADAT_DAC0ABCLK_DAC0

MCLK_DAC0


MCLK_DAC0

MDMCML_8740_0

MDMCML_8740_0

DGND

+3V3_DAC0

RESET* RESET*

R400

3K30W1250805

C4262N2100VFKP2

R4023K30W1250805

C430680P100VFKP2

R408

680R0W1250805

R401

3K30W1250805

C4272N2100VFKP2

R409

680R0W1250805

R403

3K30W1250805

C431

680P100VFKP2

6

57

IC400B

OPA2134UASO-8

DGND

DGND

2nd order Bessel filter, Av=1

C401

10UF35VSGET

C409

100N50V0805

C405

10UF35VSGET

C417

100N50V0805

+12VA

DGND

-12VA

DGND

R404

3K30W1250805

C4282N2100VFKP2

R4063K30W1250805

C432680P100VFKP2

R410

680R0W1250805

R405

3K30W1250805

C4292N2100VFKP2

R411

680R0W1250805

R407

3K30W1250805

C433

680P100VFKP2

2

31

8

4

IC400A

OPA2134UASO-8

DGND

DGND


DAC

FILTER

6

57

IC401B

OPA2134UASO-8

R413

10K0W1250805

R412

10K0W1250805

C410100N50V0805

C411100N50V0805

R4221M00W1250805

C43433P100V0805

C436

100UF16VNONP

R424

47R0W1250805

R425

47R0W1250805

+12VA

DGND

-12VA

DGND

DGND

67

8

IC402BDG413DYSO-16

1011

9

IC402CDG413DYSO-16

1415

1

6

IC402DDG413DYSO-16

OUTPUT BUFFERGain of -2.2 for HDCD, otherwise -1.1Cheapo version could have bipolar op-amp, but without feedback round coupling cap

GAIN_SCALING GAIN_SCALING

R41510K0W1250805

DGND

1=HDCD gain, 0=normal

2

31

8

4

IC401A

OPA2134UASO-8

R418

10K0W1250805

R417

10K0W1250805 R423

1M00W1250805

C43533P100V0805

C437

100UF16VNONP

R426

47R0W1250805

R427

47R0W1250805DGND

2 3

1

IC402ADG413DYSO-16

C421100N50V0805

C423100N50V0805

C422100N50V0805

V-4

GND5

V+13

VL12

IC402E

DG413DYSO-16

+12VA

+5VA

-12VA

DGND

DGND

+12VA

-12VA

C4401N0100V0805

+12VA

-12VA

C4441N0100V0805

EMC_GND

RLY400A

NECEB2-5NU

DGND

DGND

DGND

RLY400B

NECEB2-5NU

DGND

RLY400CNECEB2-5NU

+5VD

D404

BAS16SOT-323

RLY500CNECEB2-5NU

RLY600CNECEB2-5NU

TR401

FMMT497SOT-23

DGND

MUTE_BUF*

AC_PRES* AC_PRES*

MUTE_BUF*

MUTING

R420

11K0W1250805

R421

11K0W1250805

Useful for drop-out test

D400

BAT54SSOT-23

D403

BAT54SSOT-23

R428

0R0 0W1250805

R429

0R00805

R430

0R0 0W1250805

R431

0R00805

R434

1K00W1250805

R435

1K00W1250805

SCART_LEFT

SCART_RIGHT

D401BAT54SSOT-23

R436

100R0W1250805

C441

1N0100V0805

DGND EMC_GND12

CON400

HARWINM20-973

DGND

C442

1N0100V0805

C443

1N0100V0805

TR400

BC849BSOT-23

DGND

R41447K0W1250805

R41947K0W1250805

NF

NF

P408

P409

P414

P415

P416

P417

P421

P423

P422

P424 P427

P428

P429P430

P434

P431

P435

P436

P437

P438 ML/I2S28

D

V

D

D

8

D

G

N

D

7

LRCKIN1

BCKIN3DIN2

DIFFHW6

SCLK5

RSTB22

VOUTL+ 17

MODE8X4

VOUTR+ 12

MODE24

A

G

N

D

L

1

9

ZERO 21

VOUTL- 16

VMIDL 18

VOUTR- 13

A

V

D

D

R

9

A

G

N

D

R

1

0

VMIDR 11

MC/DM127

CSBIOW23

MUTEB25

MD/DM026

A

V

D

D

L

2

0

A

G

N

D

1

4

A

V

D

D

1

5

IC403

XWM8740EDSSSOP-28

Audio outputs are inverted so as to be compatible with DV88. This is compenstaed for in software by setting a register in the DAC to invert the signal

Base resistor on sheet 3

Base resistor on PSU

Fit on top of RLY400

C412

100N100VMKS2

C413

100N100VMKS2

C424

47P100V0805

C425

47P100V0805

LEFT

RIGHT

S

C

R

N

SKT400KUNMING GOLD

DGND DGND

LEFT_OUT

RIGHT_OUT

C439

100P100V0805

C438

100P100V0805

C419

100P100V0805

C418

100P100V0805

P400P401

P402

OUT_GND1OUT_GND2

ITEM400 1 Pad Damping 7.5x6x3MM RubberE828AP


ISSUE

DRAWING NO.

DRAWING TITLE

DATE

Filename:


L971C5.Sch

DV29 MAIN DAC LS & RS AUDIO



Notes:




A2

L500

120R@100MHz

+3V3A

C502

10UF35VSGET

C514

100N50V0805

+5VA

C500

10UF35VSGET

C506

100N50V0805

C507

100N50V0805

C508

100N50V0805

DGND

DGND

DGND

+3V3_DAC1

C503

10UF35VSGET

C515

100N50V0805

C504

10UF35VSGET

C516

100N50V0805

DGND


MCLK_DAC1


MCLK_DAC1

MDMCML_8740_1

MDMCML_8740_1

DGND

+3V3_DAC1

RESET* RESET*

R500

3K30W1250805

C5222N2100VFKP2

R5023K30W1250805

C526680P100VFKP2

R508

680R0W1250805

R501

3K30W1250805

C5232N2100VFKP2

R509

680R0W1250805

R503

3K30W1250805

C527

680P100VFKP2

6

57

IC500B

OPA2134UASO-8

DGND

DGND


C501

10UF35VSGET

C509

100N50V0805

C505

10UF35VSGET

C517

100N50V0805

+12VA

DGND

-12VA

DGND

R504

3K30W1250805

C5242N2100VFKP2

R5063K30W1250805

C528680P100VFKP2

R510

680R0W1250805

R505

3K30W1250805

C5252N2100VFKP2

R511

680R0W1250805

R507

3K30W1250805

C529

680P100VFKP2

2

31

8

4

IC500A

OPA2134UASO-8

DGND

DGND


DAC

FILTER

6

57

IC501B

OPA2134UASO-8

R512

10K0W1250805

C510100N50V0805

C511100N50V0805

R5181M00W1250805

C53033P100V0805

C532

100UF16VNONP

R520

47R0W1250805

R521

47R0W1250805

+12VA

DGND

-12VA

DGND

DGND

OUTPUT BUFFERGain of -1.1Cheapo version could have bipolar op-amp, but without feedback round coupling cap

2

31

8

4

IC501A

OPA2134UASO-8

R514

10K0W1250805

R5191M00W1250805

C53133P100V0805

C533

100UF16VNONP

R522

47R0W1250805

R523

47R0W1250805DGND

+12VA

-12VA

C534470P100V0805

C5361N0100V0805

EMC_GND

+12VA

-12VA

C535470P100V0805

C5371N0100V0805

RLY500B

NECEB2-5NU

DGND

DGND

DGND

RLY500A

NECEB2-5NU

DGND

R516

11K0W1250805

R517

11K0W1250805

R524

0R00805

R525

0R00805

R526

0R0 0W1250805

R527

0R00805

D500BAT54SSOT-23

D501BAT54SSOT-23

R51347K0W1250805

R51547K0W1250805

P507

P508

P519

P520

P513 P514P515

P518

P521

P525 P526P527

P530

P531 ML/I2S28

D

V

D

D

8

D

G

N

D

7

LRCKIN1

BCKIN3DIN2

DIFFHW6

SCLK5

RSTB22

VOUTL+ 17

MODE8X4

VOUTR+ 12

MODE24

A

G

N

D

L

1

9

ZERO 21

VOUTL- 16

VMIDL 18

VOUTR- 13

A

V

D

D

R

9

A

G

N

D

R

1

0

VMIDR 11

MC/DM127

CSBIOW23

MUTEB25

MD/DM026

A

V

D

D

L

2

0

A

G

N

D

1

4

A

V

D

D

1

5

IC502

XWM8740EDS

SSOP-28



C512

100N100VMKS2

C513

100N100VMKS2

C520

47P100V0805

C521

47P100V0805

LEFT SURR

RIGHT SURR

DGND DGND

CENTRE_OUT

SUB_OUT

From sheet 6

CENTRE

SUB

LS_OUT

C518470P100V0805

C519470P 100V0805

S

C

R

N

SKT500KUNMING GOLD

RS_OUT

OUT_GND3OUT_GND4

CENTRE_OUT

SUB_OUT


ALL PARTS ON THIS SHEET ARE NOT FITTED FOR DV75


ISSUE

DRAWING NO.

DRAWING TITLE

DATE

Filename:


L971C6.Sch

DV29 MAIN DAC CENTRE & SUB



Notes:




A2

L600

120R@100MHz

+3V3A

C602

10UF35VSGET

C614

100N50V0805

+5VA

C600

10UF35VSGET

C606

100N50V0805

C607

100N50V0805

C608

100N50V0805

DGND

DGND

DGND

+3V3_DAC2

C603

10UF35VSGET

C615

100N50V0805

C604

10UF35VSGET

C616

100N50V0805

DGND


MCLK_DAC2


MCLK_DAC2

MDMCML_8740_2

MDMCML_8740_2

DGND

+3V3_DAC2

RESET* RESET*

R600

3K30W1250805

C6222N2100VFKP2

R6023K30W1250805

C626680P100VFKP2

R608

680R0W1250805

R601

3K30W1250805

C6232N2100VFKP2

R609

680R0W1250805

R603

3K30W1250805

C627

680P100VFKP2

6

57

IC600B

OPA2134UASO-8

DGND

DGND


C601

10UF35VSGET

C609

100N50V0805

C605

10UF35VSGET

C617

100N50V0805

+12VA

DGND

-12VA

DGND

R604

3K30W1250805

C6242N2100VFKP2

R6063K30W1250805

C628680P100VFKP2

R610

680R0W1250805

R605

3K30W1250805

C6252N2100VFKP2

R611

680R0W1250805

R607

3K30W1250805

C629

680P100VFKP2

2

31

8

4

IC600A

OPA2134UASO-8

DGND

DGND


DAC

FILTER

6

57

IC601B

OPA2134UASO-8

R612

10K0W1250805

C610100N50V0805

C611100N50V0805

R6181M00W1250805

C63033P100V0805

C632

100UF16VNONP

R620

47R0W1250805

R621

47R0W1250805

+12VA

DGND

-12VA

DGND

DGND

OUTPUT BUFFERGain of -1.1Cheapo version could have bipolar op-amp, but without feedback round coupling cap

2

31

8

4

IC601A

OPA2134UASO-8

R614

10K0W1250805

R6191M00W1250805

C63133P100V0805

C633

100UF16VNONP

R622

47R0W1250805

R623

47R0W1250805DGND

+12VA

-12VA

+12VA

-12VA

RLY600B

NECEB2-5NU

DGND

DGND

DGND

RLY600A

NECEB2-5NU

DGND

R616

11K0W1250805

R617

11K0W1250805

D600

BAT54SSOT-23

D601

BAT54SSOT-23

R624

0R0 0W1250805

R626

0R0 0W1250805

R61347K0W1250805

R61547K0W1250805

P619

P620

P607

P608

P613 P614P615

P618

P625 P626P627

P630

P631


ML/I2S28

D

V

D

D

8

D

G

N

D

7

LRCKIN1

BCKIN3DIN2

DIFFHW6

SCLK5

RSTB22

VOUTL+ 17

MODE8X4

VOUTR+ 12

MODE24

A

G

N

D

L

1

9

ZERO 21

VOUTL- 16

VMIDL 18

VOUTR- 13

A

V

D

D

R

9

A

G

N

D

R

1

0

VMIDR 11

MC/DM127

CSBIOW23

MUTEB25

MD/DM026

A

V

D

D

L

2

0

A

G

N

D

1

4

A

V

D

D

1

5

IC602

XWM8740EDS

SSOP-28


C612

100N100VMKS2

C613

100N100VMKS2

C620

47P100V0805

C621

47P100V0805

CENTRE_OUT

SUB_OUT

Connector on sheet 5

Connector on sheet 5


ALL PARTS ON THIS SHEET ARE NOT FITTED FOR DV75


ISSUE

DRAWING NO.

DRAWING TITLE

DATE

Filename:


L971C8.Sch

DV29 MAIN SCART OUTPUT



Notes:




A2

1

3

5

7

9

11

13

15

17

19

21

2

4

6

8

10

12

14

16

18

20

SKT800

CHARMCW

SCART OUTPUT

SCART_LEFT

SCART_RIGHT

C80047P100V0805

C80147P100V0805 R800

0R00W1250805

DGND

SCART_LEFT

SCART_RIGHT

DGND EMC_GND

C811

1N0 100V 0805

C812

1N0 100V 0805

AUDIO

SCART_BLUE

SCART_GREEN

SCART_RED

SCART_COMPOSITE

VIDEO

SCART_AGND

SCART_BLUE

SCART_GREEN

SCART_RED

SCART_COMPOSITE

C80247P100V0805

C80347P100V0805

C80447P100V0805

C80547P100V0805

DGND

ENABLE_AV

16/9

SCART control signals

ENABLE_AV: 0 in when standby mode, 1 when on (3V3 levels)(RGB_STAT is supposed to be >1V when driving 75R)16/9: 0 when 4:3 output, 1 when 16:9 output (3V3 levels)0/6/12: 0V in standby, 6V when output is 16:9, 12V when output is 4:3

CONTROL

TR801

MMUN2211LT1SOT-23

DGND

TR803

BC849BSOT-23

R8074K70W1250805

R8066K80W1250805

TR802

MMUN2211LT1SOT-23

DGND

R80810K0W1250805

0/6/12

DGND

D800

BAT54SSOT-23

DGND

TR804

BC849BSOT-23

+5V_VID

DGND

D801

BAT54SSOT-23

DGND

+5V_VID

RGB_STAT

DGND

R809

330R0W1250805

R810

330R0W1250805

R8111K00W1250805

RGB_STAT

0/6/12

R801

1K00W1250805

+5V_VID

P811

P810

TR800

MMUN2111LT1SOT-23

+12VD

+12VD

P812

P816

P815

P814

P817 P818

P819

R803

100R0W1250805

R812

82R0W1250805

C806

100N50V0805

C807

100N50V0805

C813

10N50V0603


ISSUE

DRAWING NO.

DRAWING TITLE

DATE

Filename:


L971C10.Sch

DV29 MAIN Power



Notes:




A2

P1000 P1002

C1010

100UF25VYK

+5VD

DGND

P1003

DGND

+3V3D

A

D

J

REG1003LM1086CS-ADJTO-263

C1002

100N50V0805

D1000

S1DDO-214AC (SMA)

R1000

120R0W1250805

R1006

56R0W1250805

C1012

100UF25VYK

P1004+1V8D

DGND

POWER IN

VADDIS +1.8V REGULATOR

C1003

100N50V0805

A

D

J

REG1000LM317T TO-220

D1001

S1DDO-214AC (SMA)

D1002

S1DDO-214AC (SMA)

R1001

390R0W1250805

R1004

3K30W1250805

C1014

100UF25VYK

+12VA

AUDIO SUPPLY REGULATORS

DGND

C1005

100N50V0805

C1017

100UF25VYK

A

D

J

REG1002LM337TTO-220

D1006

S1DDO-214AC (SMA)

D1005

S1DDO-214AC (SMA)

R1003

390R0W1250805

R1005

3K30W1250805

-12VA

C1004

100N50V0805

A

D

J

REG1001LM317T TO-220

D1003

S1DDO-214AC (SMA)

D1004

S1DDO-214AC (SMA)

C1015

100UF25VYK

+5VA

DGND

AUDIO DAC SUPPLY

+15V5

-15V5

+15V5

C1000

100N50V0805

C1001

100N50V0805

C1011

100UF25VYK

L1004

120R@100MHz

C1006

100N50V0805L1007

120R@100MHz

DGND

-9V

DISPLAY BOARD SUPPLIES

P1012 L1005

120R@100MHz

C1007

100N50V0805L1008

120R@100MHz

DGND

-13V5To display board

L1006

120R@100MHz

C1008

100N50V0805L1009

120R@100MHz

DGND

-19V

C1009

100N50V0805

L1010

120R@100MHz

Place these near power input

DGND

+3V3AFor DACs

R1007

1K00W1250805

R1002

330R0W1250805

C1022

1N050V0603

DGND

C1024

1N050V0603

DGND

C1026

1N050V0603

DGND

1

FIX1004

Dia 3.5mm

C1028

1N050V0603

DGND

1

FIX1006

Dia 3.5mm

C1023

1N050V0603

DGND

1

FIX1002

Dia 3.5mm

C1025

1N050V0603

DGND

1

FIX1003

Dia 3.5mm

C1027

1N050V0603

DGND

1

FIX1005

Dia 3.5mm

Documents

DV29 service manual issue 1.pdf