Dual Edge Triggered Sense-Amplifier Flip-Flop for Low

Power System

ByManukumar G C (13MT6SP003)Sudeep Sagar E (13MT6SP007)

Introduction

Optimization Technique

Classification

Low Power Design

Overview

Comparison

Contents

Electronic Design Automation (EDA) tools were used in order to implement complex and low power systems.

The use of low power has been extended from portable devices to high performance computing applications .

As flip-flops are critical timing elements they have large impact on circuit speed and power consumption.

Introduction

The use of dual edge triggered flip flop has gained more attention, as it maintains constant throughput at only half the clock frequency.

In the modern era rapid increases in clock frequency contribute directly to power consumption of microprocessor.

Reducing the power consumption of a design translate directly into increased battery life of portable devices.

Clock gating can be used as a method of shutting down portions of SOC or microprocessor when the functional blocks are not in use.

Dynamic Voltage Scaling (DVS) can be used to reduce the power consumption by reducing the operating voltage of the entire design.

DVS has limited use of applications because of its scalability issues.

Optimization Technique

The best approach to reduce power is to use dual edge triggered storage elements in place of single edge triggered storage elements.

Dual edge clocking can achieve the same throughput at half the clock frequency and half the clock related power consumption as compared to SETFF.

This technology can be scaled according to our applications and can be used in conjunction with the benefits of clock gating.

Power consumption in synchronous VLSI can be divided into three major factors:

Power consumption in the clock network 

Power consumption in clock buffer 

Power consumption in the flip-flops

 

Classification

The power consumption in digital CMOS circuit is given by

α denotes the transition activity factor which is defined as the average number of power consuming transitions that is made at one node in one clock cycle.

Low Power Design

Vdd.CL is the node capacitance. It can be classified as gate, diffusion and interconnect capacitance.

The interconnect capacitance is the function of placement and routing.

Energy provided by the supply source is

R is the resistance path between the Vdd and the output node.

Energy can be rewritten as

During low to high transitions no energy is supplied by the source. Hence, the average power consumed is given by

As energy is independent of clock frequency, reducing the frequency will not change the energy required to perform given operation.

The battery life is determined by energy consumption where as the heat dissipation is related to power consumption.

In SETFF, the output of flip-flop will follow the input D at the rising edge of the clock.

In DETFF, the transition is observed on both rising and falling edge of the clock.

The output can only change at clock edges, and if the input changes at other times the output will be unaffected.

Dual Edge-Triggered Static Pulsed Flip-Flop

Static output controlled discharge Flip-Flop

Proposed Dual Edge Triggered Flip-flop

Overview of existing Flip-Flop

Dual Edge-Triggered Static Pulsed Flip-Flop

Static Pulse generation The four inverters are used to generate the inverted and delayed clock signals. The two nMOS transistors create a narrow sampling window at both rising and falling edges of the clock.

Static Latch

RbSb

The two nMOS transistors N3 and N4 are turned on by the pulse in a very short time.

During this time input data can be captured by the static latch so the nodes Sb and Rb will be charged or discharged according to input data.

The two pMOS transistors P1 and P2 will supply Vdd to Rb and Sb respectively.

The N5 and N6 transistors are connected to GND if P1 and P2 are on.

Hence P1,P2,N1 and N2 will avoid floating of nodes Rb and Sb.

Static output controlled discharge Flip-Flop

Dual Pulse Generation

It involves an explicit pulse generator and a latch that captures the pulse signal.

Latch of SCDFFIt involves two stages

1) The input D is used to drive the precharge transistors so the node X follows D during sampling period.

2) Qb controlled nMOS discharge path, which prevents unnecessary discharge at node X as long as the input D

remains high.

X

Proposed Dual Edge Triggered Flip-flop

DDb

Comparison

Sudeep Balan, Sanil K Daniel, ”Dual-edge triggered sense amplifier flip-flop for low power systems”, IEEE Transaction on VLSI Systems, 2012.

W. M. Chung, T. Lo, and M. Sachdev, “A comparative analysis of low-power low-voltage dual-edge triggered flip-flops”, IEEE Transaction on VLSI Systems, 2011.

 Jan M. Rabaey, Anantha P. Chandrakasan, Boriveje Nikolic. Digital Integrated Circuits: A Design Perspective, 2002 Edition, Prentice Hall.

Weste, Neil H. E., and Harris David. CMOS VLSI Design: A Circuits and Systems Perspective, 2005 Ed., Addison-Wesley.

References

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