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Page 1 of 47
DSPC-8682
Octal-TMS320C6678 DSP PCI-E FLCard
H/W Manual
Author:
Status: Version 1.0
Document ID:
Location:
Page 2 of 47
Content
1. GENERAL ............................................................................................................. 6
1.1 GENERAL INTRODUCTION .............................................................................................................................................. 6 1.2 PRODUCT SPECIFICATIONS ............................................................................................................................................. 6 1.3 DSPC-8682 BLOCK DIAGRAMS ..................................................................................................................................... 9 1.4 DSPC-8682 PCI-E CARD PLACEMENT .......................................................................................................................... 10
2. HARDWARE SPECIFICATION ............................................................................... 11
2.1 POWER FEED ............................................................................................................................................................ 11 2.2 POWER DISTRIBUTION ............................................................................................................................................... 11 2.3 POWER BUDGET ....................................................................................................................................................... 14 2.4 POWER SEQUENCE .................................................................................................................................................... 15 2.5 PLATFORM CLOCK ...................................................................................................................................................... 17 2.6 RESET BLOCK DIAGRAM .............................................................................................................................................. 22 2.7 RESET SEQUENCE....................................................................................................................................................... 23 2.8 DSP (TI TMS320C6678) BLOCK DIAGRAM ................................................................................................................. 24 2.9 MEMORY (DDR3) .................................................................................................................................................... 24 2.10 SRIO INTERFACE ....................................................................................................................................................... 24 2.11 PCI-E INTERFACE ....................................................................................................................................................... 25 2.12 ETHERNET MAC ....................................................................................................................................................... 26 2.13 HYPERLINK INTERFACE ................................................................................................................................................ 27 2.14 FGPA XC3S200AN .................................................................................................................................................. 28 2.15 LEDS ...................................................................................................................................................................... 30
3. IO CONNECTOR .................................................................................................. 32
3.1 CONNECTOR OVERVIEW.............................................................................................................................................. 32 3.2 THE PEX8748, BCM5482S AND CPS1616 BOUNDARY SCAN CONNECTOR ........................................................................ 33 3.3 TMS320C6678 BOUNDARY SCAN CONNECTOR ............................................................................................................ 34 3.4 60 PINS DSP EMULATOR CONNECTOR ........................................................................................................................... 34 3.5 RJ45 LAN CONNECTOR .............................................................................................................................................. 37 3.6 XILINX XC3S200AN JTAG INTERFACE ........................................................................................................................ 38 3.7 DC 12V ATX POWER CONNECTOR ............................................................................................................................... 39 3.8 FAN CONNECTOR ...................................................................................................................................................... 40 3.9 FAN CONNECTOR ...................................................................................................................................................... 41
4. JUMPER AND SWITCH SETTING .......................................................................... 42
5. MECHANICAL DRAWING .................................................................................... 46
Page 3 of 47
Figure
FIGURE 1: DSPC-8682 SYSTEM BLOCK DIAGRAM .............................................................................. 9
FIGURE 2: DSPC-8682 PCI-E CARD PLACEMENT ............................................................................... 10
FIGURE 3: POWER DISTRIBUTION BLOCK DIAGRAM FOR DSP0, DSP1, DSP6 AND DSP7 .................... 11
FIGURE 4: POWER DISTRIBUTION BLOCK DIAGRAM FOR DSP2, DSP3, DSP4 AND DSP5 .................... 12
FIGURE 5: POWER DISTRIBUTION BLOCK DIAGRAM ....................................................................... 13
FIGURE 6: DSPC-8682 OVERALL POWER SEQUENCE ........................................................................ 15
FIGURE 7: POWER DISTRIBUTION ON DSPC-8682 PCI-E CARD ......................................................... 16
FIGURE8: DSPC-8682 CARRIER CLOCK FEEDING DIAGRAM .............................................................. 21
FIGURE9: DSPC-8682 RESET BLOCK DIAGRAM ................................................................................ 22
FIGURE10: THE DSP RESET SEQUENCE ON DSPC-8682 ..................................................................... 23
FIGURE11: TI TMS320C6678 BLOCK DIAGRAM ................................................................................ 24
FIGURE12: SERIAL RAPIDIO RING ................................................................................................... 25
FIGURE13: PCIE INTERCONNECTION ............................................................................................... 26
FIGURE14: LAN INTERCONNECTION ............................................................................................... 27
FIGURE15: HYPERLINK CONNECTION ............................................................................................. 28
FIGURE16: FPGA CONNECTION ...................................................................................................... 29
FIGURE17: TOP SIDE LED LOCATION ............................................................................................... 30
FIGURE18: CONNECTOR OVERVIEW ............................................................................................... 32
FIGURE19:CN1, BOUNDARY SCAN FOR PEX748, BCM5482S AND CPS1616....................................... 33
FIGURE20: CN2, THE BOUNDARY SCAN FOR THE DSP FARM............................................................ 34
FIGURE21: CN3, TI 60-PIN EMULATION CONNECTOR ...................................................................... 35
FIGURE22: CONNECTION THE XDS560V2 STM EMULATOR .............................................................. 35
FIGURE23: 60-PIN HEADER ORIENTATION....................................................................................... 35
FIGURE24: THE CONNECTION WITH TI XDS560V2 STM EMULATOR ................................................. 36
FIGURE25: CN5, RJ45 LAN PORT ..................................................................................................... 37
FIGURE26: CN5, THE FPGA JTAG FOR FIRMWARE UPDATE .............................................................. 38
FIGURE27: CN6, 12V CONNECTOR .................................................................................................. 39
FIGURE28: CN7, FAN CONNECTOR .................................................................................................. 40
FIGURE29: CN8, FAN CONNECTOR .................................................................................................. 41
FIGURE30: THE SW1 ON DSPC-8682 PCIE CARD .............................................................................. 42
Page 4 of 47
FIGURE31: THE SW1 SCHEMATIC .................................................................................................... 42
FIGURE32: THE SW2 SCHEMATIC .................................................................................................... 44
FIGURE33: DSPC-8682 TOP SIDE ..................................................................................................... 46
FIGURE34: DSPC-8682 FRONT SIDE ................................................................................................ 46
FIGURE 35: DSPC-8682 BOTTOM SIDE ............................................................................................ 47
Page 5 of 47
Table
TABLE 1: DSPC-8682 POWER BUDGET ............................................................................................ 14
TABLE 2: SYSTEM POWER SEQUENCE PARAMETER ......................................................................... 16
TABLE 3: CLOCK DOMAINS ............................................................................................................. 20
TABLE 4: PCI-E PORT MAPPING ON PEX8748 .................................................................................. 26
TABLE5: PCI-E SWITCH LED ............................................................................................................. 30
TABLE6: FPGA LED ......................................................................................................................... 31
TABLE7: CN1 PIN ASSIGNMENT ...................................................................................................... 33
TABLE 8: CN2 PIN ASSIGNMENT ..................................................................................................... 34
TABLE 9: CN3 DSP EMULATOR PIN ASSIGNMENTS .......................................................................... 36
TABLE10: CN4 PIN ASSIGNMENT .................................................................................................... 37
TABLE11: CN5 PIN ASSIGNMENT .................................................................................................... 38
TABLE12: CN6 PIN ASSIGNMENT .................................................................................................... 39
TABLE13: CN7 PIN ASSIGNMENT .................................................................................................... 40
TABLE14: CN8 PIN ASSIGNMENT .................................................................................................... 41
TABLE15: THE SW1 SETTING TABLE ................................................................................................ 43
TABLE16: THE SW2 SETTING TABLE ................................................................................................ 45
Page 6 of 47
1. General
1.1 General Introduction
This document is the H/W user manual of DSPC-8682, the PCI-E x8 Full-Length add-on card with
octal-TMS320C6678 DSPs. DSPC-8682 is composed of eight TI TMS320C6678 DSPs, one PCI-E GEN3
switch PEX8748, one SRIO GEN2 switch CPS1616 and two RJ45 LAN ports.
1.2 Product Specifications
Below information describes the components designed on DSPC8682E PCI-E card.
DSP
� TI TMS320C6678 Multi-core Fixed and Floating-Point Digital Signal Processor.
DSP Memory
� 1024MB or 2048MB memory size on each DSP composed of 64-bit data width with four 2G
or 4G bits DDR3-1333 x16 memory chips. Refer below list for detail.
Revision PCB SN PCB Rev Memory
X 19C2868200 A101-1 Samsung 2G bits
X 19C2868201-01 A102-1 Micron 4G bits
Rev.05 19C2868201-01 A102-1 Samsung 4G bits
Refer to blow picture to see the PCB SN
Octal-TMS320C6678 DSP PCI-E FL Card contains very delicate integrated circuit chips.
In order to protect Octal-TMS320C6678 DSP PCI-E FL Card from static electricity, you should
follow some precautions whenever you work on your computer.
1. Turn off your computer and unplug power supply.
2. Use a grounded wrist strap before handling computer components. If you do not have one,
touch both of your hands to a safely grounded object or to a metal object, such as the power
supply case.
3. Plug in ATX power connector (CN6) first before turn on your computer. Some voltage’s
power source of octal card comes from 6-pin ATX power connector.
Page 7 of 47
FPGA
� XILINX XC3S200AN
Handle the DSPs’ interrupt events, booting configurations, power sequences, reset sequences
and PHY LED control, programming clock generator of CDCE62005 and the LVDS clock buffers.
PCI-express Switch
� PEX8748 (48 lanes / PCI-E GEN3)
Upstream port: PCI-E x8 GEN3 to HOST, Downstream port: PCI-E GEN2x2 4-port to eight DSPs.
Ethernet PHY
� BCM5482S
Support 10/100/1000 Mb/s with 1000BASE-T interface.
I/O Expansion
� Standard PCI-E x8 golden finger
I/O connector
� CN1: The PEX8748, BCM5482S and CPS1616 boundary scan connector.
� CN2: The DSP Boundary Scan connector.
� CN3: TI 60 pins DSP emulator connector.
� CN4: RJ45 connectors for LANs.
� CN5: FPGA JTAG connector.
� CN6: DC 12V ATX power connector.
� CN7: FAN connector for the heat sink.
� CN8: FAN connector for the heat sink.
� COM1: 3 pins UART connector.
Page 8 of 47
� PMBUS1: UCD9244 PMBUS connector.
� 560V2_PWR1: XDS560v2 power connector.
Indicator
� Four LEDs, FPGA LED1 to FPGA LED4, are used for the FPGA XC3S200AN debugging.
� LED D1 indicates the error event of CPS1616.
� LED D3 indicates the error event of PEX8748.
� LED D4 indicates the interrupt event of PEX8748.
� LED SYSPG_D1 indicates that all power rails are stable.
EEPROM
� Eight pieces of 1M bits I2C EEPROM are attached to eight DSPs respectively. The EEPROM is
contained of the DSP boot code and the initializations for the first boot while the card
power-on and then branch to PCI-E interface for the second boot by the HOST computer.
� One piece of 128kbit SPI EEPROM is attached to PCI-E switch (PEX8748) for specific port
configurations.
� One piece of 64kbit I2C EEPROM is attached to SRIO switch (CPS1616) for port’s routing
table configurations.
Power Requirement
� 12V and 3.3V from PCI-E golden finger.
� 12V from ATX power connector.
OS Verification
� Booting image (TBD).
� Application Program (TBD).
Environments
� Operating temperatures: -5°C to 45°C (TBD)
� Storage temperatures: -20°C to 70°C
� Relative humidity: 5% to 95% (Non-condensing)
Certification
� CE/ FCC Class A
� Compliant with RoHS
Page 9 of 47
1.3 DSPC-8682 Block Diagrams
The internal connections on DSPC-8682 PCI-E card are described and shown as below figures. The
whole system interface block diagram for the DSPC-8682 board is shown as Figure 1 Each
TMS320C6678 DSP contains several interfaces such as DDR, HyperLink, Serial RapidIO, PCI-E, and
SGMII for Ethernet connection.
PCIEx2
PCIEx2
PCIEx2
PCIEx2
PCIEx2
PCIEx8
PCIEx2
PCIEx2
PCIEx2
DSP5 Block DSP4 Block
DSP3 BlockDSP2 BlockDSP1 Block
DSP7 Block DSP6 Block
SRIOx1
Hyperlink
Hyperlink
Hyperlink
SRIOx1
Hyperlink
TMS320C6678
TMS320C6678
TMS320C6678TMS320C6678
TMS320C6678
TMS320C6678
TMS320C6678SGMII
SRIOx1
SGMII
SRIOx1SRIOx1
SGMII SGMII
SRIOx1
Switch21x21mm
CPS-1616IDT
SRIOx1
SGMII*1
SRIO (Gen2)12Ports/48Lanes
PEX8748PLX
27x27mm3.5W / 5.6W
TMS320C6678
DSP0 Block
PCIEx8 (Gen3)
SGMII
SRIOx1
SGMII
SRIOx1
SRIOx2
SRIOx2
SRIOx2
SRIOx2
SRIOx2
SRIOx2
SRIOx2
SRIOx2
PCIEx8 (Gen3)
BCM5482S
Broadcom
RJ45W/ Xfmr
RJ45W/ Xfmr
SGMII&MDIO&MDC(5482S input)
SGMII&MDIO&MDC(5482S input)
4Gbx16bDDR3
24x24mm
TISGMII[1]x1
DDR3-13334Gb*4
15W
DSP0~7
SRIO[1]x1
SGMII[0]x1
SRIO[0]x1
PCIE[0:1]x2 SRIO[2:3] x2 Hyperlink
I2C
EEPROM128k-byte
DSP Block
TMS320C6678
Figure 1: DSPC-8682 System Block Diagram
Page 10 of 47
1.4 DSPC-8682 PCI-E card Placement
Below figure shows main components on DSPC-8682. It’s only for reference if user needs to learn
specific DSP or want to find a key chip on the card during developing.
Figure 2: DSPC-8682 PCI-E card Placement
Page 11 of 47
2. Hardware Specification
2.1 Power Feed
The power source of DSPC-8682 is provided by two power rails, 12V and 3.3V from host, via PCI-E x8
golden finger and 12V from ATX power connector.
2.2 Power Distribution
The major power on DSPC-8682 is illustrated as below Figure3, Figure4 and Figure5. User could refer
to DSPC-8682 schematics for more details regarding the power supplies on DSPC-8682.
VCC1P5
DVDD1P8
VCC1P0
DSP7VID
1.8V/0.416A
1.5V/1.3A
0.75V
Adjustable Core(0.9V – 1.1V) 10A VCC0P75
1.0V/8A
DSP6
VID
VCC0P75
VID
Adjustable Core(0.9V – 1.1V) 10A
DSP1
1.5V/1.3A
1.8V/0.416A
1.0V/8A
Adjustable Core(0.9V – 1.1V) 10A
0.75V
DVDD1P8
VCC1P0
VCC1P5
UCD74110
DDR3
#1UCD9244
SmartReflexPMbus
V4
V2
V3
V1
4
4
DSP6_VartibleCore_1.0V
DSP1_VartibleCore_1.0V
DSP0_VartibleCore_1.0V
4
4
DSP7_VartibleCore_1.0V
PWMPWM
DSP0
TMS320C6678
PWMPWM
PMbus_CLK
PMbus_Alert
PMbus_Cntrl
GPIO_power_goodPMbus_DATA
0.75V
VCC1P0
1.5V/1.3A
1.8V/0.416A
1.0V/8AAdjustable Core(0.9V – 1.1V) 10A
DVDD1P8
VCC1P5
VCC0P75
1.0V/8A
1.8V/0.416A
1.5V/1.3A
0.75V
15A Max 15A Max
15A Max15A Max
TMS320C6678 TMS320C6678
TMS320C6678
UCD74110
UCD74110 UCD74110
VCC1P5
DVDD1P8
VCC1P0
VCC0P75
VID
DDR3 DDR3
DDR3
Figure 3: Power Distribution Block Diagram for DSP0, DSP1, DSP6 and DSP7
Page 12 of 47
UCD74110
UCD74110
UCD74110
15A Max 15A Max
15A Max
TMS320C6678
TMS320C6678
TMS320C6678
TMS320C6678
VID
DSP2
0.75V
1.5V/1.3A
1.8V/0.416A
15A Max
Adjustable Core(0.9V – 1.1V) 10A
VID
DSP5
1.0V/8A
VID DSP3
Adjustable Core(0.9V – 1.1V) 10A
Adjustable Core(0.9V – 1.1V) 10A
1.0V/8A
1.8V/0.416A
1.5V/1.3A
0.75V
DDR4
PMbus
SmartReflex
UCD9244 #2
V3
V2
V4
4
4
V1
DSP4_VartibleCore_1.0VDSP2_VartibleCore_1.0V
DSP5_VartibleCore_1.0V
4
4
DSP3_VartibleCore_1.0V
PWM PWM
DSP4
PMbus_Cntrl
PMbus_Alert
PMbus_CLK
PWM PWM
GPIO_power_good
1.8V/0.416A
1.5V/1.3A
0.75V
PMbus_DATA
Adjustable Core(0.9V – 1.1V) 10A1.0V/8A
1.8V/0.416A
1.0V/8A
0.75V
1.5V/1.3A
UCD74110VID
DDR4 DDR4
DDR4
DVDD1P8
VCC1P0
DVDD1P8
VCC1P0
VCC0P75 VCC0P75
VCC1P5
VCC1P0
VCC0P75
VCC1P5
DVDD1P8
VCC1P0
VCC1P5
VCC0P75
VCC1P5
DVDD1P8
Figure 4: Power Distribution Block Diagram for DSP2, DSP3, DSP4 and DSP5
Page 13 of 47
Max. Delivery Current : 45AVT239 1.0V@20A
EN_VCC1P0_1
0.75V@1AVCC0P75RT9173DMax. Delivery Current : 3A
Max. Delivery Current : 45AVT239
ENEN_VCC1P0_21.0V@20A
3VSB@From PCIE
PG
PG
PG
PG
PG
PG
PG_VCC2P5
PG_VCC1P8_FPGA
PG_VCC1P0_1
PG_VCC1P0_2
PG_VCC0P09
PG_VCC1P2
VCC0P9
VCC1P0_2
VCC1P0_1
VCC1P8_FPGA
VCC2P5
VCC1P2
VCC1P5
VCC0P75
VCC55V@1A
EN_VCC5 EN PGMax. Delivery Current : 3AMP28253EL
PG_VCC5
VCC3MOSFET PG
PG_VCC3VCC12 EN
PG_VCC1P2SBPG
VCC1P2SB
Max. Delivery Current : 1AEN
APL5912KAC [email protected]
PGPG_DVDD1P8EN_DVDD1P8
MP28253EL 1.8V@2ADVDD1P8
ENMax. Delivery Current : 3A
APL5912KAC
3VSB
3VSB
Max. Delivery Current : 34AEN_VCC0P9
0.9V@15AVT237EN
MP28253ELENEN_VCC1V2
MP28253EL 2.5V@1A
Max. Delivery Current : 3A
ENEN_VCC2P5Max. Delivery Current : 3A
Max. Delivery Current : 45AVT239
1.8V@1AEN
Max. Delivery Current : 1A
1.5V@22AEN
0.75V@1ART9173DMax. Delivery Current : 3A
EN_VCC1P5
EN
Figure 5: Power Distribution Block Diagram
Page 14 of 47
2.3 Power Budget
The estimated operational power budget of DSPC-8682 is about 152.06W. This value is estimated
based on the assumption of the power dissipations and utilizations of the key components. For
detailed number, it is summarized in the following table (Table1.DSPC-8682 Power Budget).
� VCC12 load= 12.3 A.
� VCC3.3 load=1.351 A
� Total power consumption (for EE Design) ~ 152.06W.
� Total power consumption (for Thermal Design) ~ 106.639W.
� Power budget table please refer to below.
Table 1: DSPC-8682 Power Budget
Page 15 of 47
2.4 Power Sequence
DSPC-8682 consists of many devices on it, including DSP, PCIe switch, SRIO switch, PHY & FPGA etc.
Hence, the power sequence is designed to meet all devices’ power-on requirements. And the timing
parameters are shown in below table (Table 2.System Power Sequence Parameter) while the power
sequence is shown in below figure.( Figure 6.DSPC-8682 overall power sequence).
t
Page 16 of 47
Sym Parameter Timing Note
T0 VCC1P0_EN is ramped up after UCD9244_EN. 5ms
Page 17 of 47
2.5 Platform Clock
The DSPC-8682 clocks are generated by the clock synthesizers, crystals and oscillators. Introductions
for each clock are described as below.
CDCE62005: It’s a Low-Jitter clock generator with 25.0MHz crystal. It’s programmed to provide
166.66MHZ, 250MHZ and 100MHz with LVDS level for the DSP reference clocks.
ICS853S12I: It’s a PCI-E GEN3 clock buffer and provides nine reference clocks to the PCI-E switch and
support PCI-E clock for DSP.
IDT_83PN156DKI: It’s a programmable LVPECL oscillator generator with 25.0MHz crystal. It offer
156.25MHz by LVPECL level and transfer to CML level for SRIO switch by divider resistor.
CDCLVD110A: It’s a 1:10 LVDS clock buffer. There are four clock buffers which fan out 166.66MHZ,
250MHZ and 100MHz to each DSP for the reference clocks of core, DDR3, HyperLink and SRIO/SGMII
interfaces.
Page 18 of 47
The platform clock distribution scheme is illustrated as the below Figure (Figure8.DSPC-8682 Carrier
Clock Feeding Diagram).
Signal Frequency Source Device
DSP0_DDR_CLKP
DSP0_DDR_CLKN 166.67MHz
TI_CDCLVD110ARHBR
U19 DSP0
DSP1_DDR_CLKP
DSP1_DDR_CLKN 166.67MHz
TI_CDCLVD110ARHBR
U19 DSP1
DSP2_DDR_CLKP
DSP2_DDR_CLKN 166.67MHz
TI_CDCLVD110ARHBR
U19 DSP2
DSP3_DDR_CLKP
DSP3_DDR_CLKN 166.67MHz
TI_CDCLVD110ARHBR
U19 DSP3
DSP4_DDR_CLKP
DSP4_DDR_CLKN 166.67MHz
TI_CDCLVD110ARHBR
U19 DSP4
DSP5_DDR_CLKP
DSP5_DDR_CLKN 166.67MHz
TI_CDCLVD110ARHBR
U19 DSP5
DSP6_DDR_CLKP
DSP6_DDR_CLKN 166.67MHz
TI_CDCLVD110ARHBR
U19 DSP6
DSP7_DDR_CLKP
DSP7_DDR_CLKN 166.67MHz
TI_CDCLVD110ARHBR
U19 DSP7
DSP0_CORE_CLKP
DSP0_CORE_CLKN 100.00MHz
TI_CDCLVD110ARHBR
U23 DSP0
DSP1_CORE_CLKP
DSP1_CORE_CLKN 100.00MHz
TI_CDCLVD110ARHBR
U23 DSP1
DSP2_CORE_CLKP
DSP2_CORE_CLKN 100.00MHz
TI_CDCLVD110ARHBR
U23 DSP2
DSP3_CORE_CLKP
DSP3_CORE_CLKN 100.00MHz
TI_CDCLVD110ARHBR
U23 DSP3
DSP4_CORE_CLKP
DSP4_CORE_CLKN 100.00MHz
TI_CDCLVD110ARHBR
U23 DSP4
DSP5_CORE_CLKP
DSP5_CORE_CLKN 100.00MHz
TI_CDCLVD110ARHBR
U23 DSP5
DSP6_CORE_CLKP
DSP6_CORE_CLKN 100.00MHz
TI_CDCLVD110ARHBR
U23 DSP6
DSP7_CORE_CLKP
DSP7_CORE_CLKN 100.00MHz
TI_CDCLVD110ARHBR
U23 DSP7
DSP0_SRIOSGMII_CLKP
DSP0_SRIOSGMII_CLKN 250.00MHz
TI_CDCLVD110ARHBR
U28 DSP0
DSP1_SRIOSGMII_CLKP
DSP1_SRIOSGMII_CLKN 250.00MHz
TI_CDCLVD110ARHBR
U28 DSP1
DSP2_SRIOSGMII_CLKP
DSP2_SRIOSGMII_CLKN 250.00MHz
TI_CDCLVD110ARHBR
U28 DSP2
Page 19 of 47
Signal Frequency Source Device
DSP3_SRIOSGMII_CLKP
DSP3_SRIOSGMII_CLKN 250.00MHz
TI_CDCLVD110ARHBR
U28 DSP3
DSP4_SRIOSGMII_CLKP
DSP4_SRIOSGMII_CLKN 250.00MHz
TI_CDCLVD110ARHBR
U28 DSP4
DSP5_SRIOSGMII_CLKP
DSP5_SRIOSGMII_CLKN 250.00MHz
TI_CDCLVD110ARHBR
U28 DSP5
DSP6_SRIOSGMII_CLKP
DSP6_SRIOSGMII_CLKN 250.00MHz
TI_CDCLVD110ARHBR
U28 DSP6
DSP7_SRIOSGMII_CLKP
DSP7_SRIOSGMII_CLKN 250.00MHz
TI_CDCLVD110ARHBR
U28 DSP7
DSP0_MCM_CLKP
DSP0_MCM_CLKN 250.00MHz
TI_CDCLVD110ARHBR
U33 DSP0
DSP1_MCM_CLKP
DSP1_MCM_CLKN 250.00MHz
TI_CDCLVD110ARHBR
U33 DSP1
DSP2_MCM_CLKP
DSP2_MCM_CLKN 250.00MHz
TI_CDCLVD110ARHBR
U33 DSP2
DSP3_MCM_CLKP
DSP3_MCM_CLKN 250.00MHz
TI_CDCLVD110ARHBR
U33 DSP3
DSP4_MCM_CLKP
DSP4_MCM_CLKN 250.00MHz
TI_CDCLVD110ARHBR
U33 DSP4
DSP5_MCM_CLKP
DSP5_MCM_CLKN 250.00MHz
TI_CDCLVD110ARHBR
U33 DSP5
DSP6_MCM_CLKP
DSP6_MCM_CLKN 250.00MHz
TI_CDCLVD110ARHBR
U33 DSP6
DSP7_MCM_CLKP
DSP7_MCM_CLKN 250.00MHz
TI_CDCLVD110ARHBR
U33 DSP7
ICS583_PCIE_REF_CLKP0
ICS583_PCIE_REF_CLKN0 100.00MHz
IDT_ICS853S12AKI
U34 DSP0
ICS583_PCIE_REF_CLKP1
ICS583_PCIE_REF_CLKN1 100.00MHz
IDT _ICS853S12AKI
U34 DSP1
ICS583_PCIE_REF_CLKP2
ICS583_PCIE_REF_CLKN2 100.00MHz
IDT _ICS853S12AKI
U34 DSP2
ICS583_PCIE_REF_CLKP3
ICS583_PCIE_REF_CLKN3 100.00MHz
IDT_ ICS853S12AKI
U34 DSP3
ICS583_PCIE_REF_CLKP4
ICS583_PCIE_REF_CLKN4 100.00MHz
IDT_ ICS853S12AKI
U34 DSP4
ICS583_PCIE_REF_CLKP5
ICS583_PCIE_REF_CLKN5 100.00MHz
IDT_ICS853S12AKI
U34 DSP5
ICS583_PCIE_REF_CLKP6
ICS583_PCIE_REF_CLKN6 100.00MHz
IDT_ ICS853S12AKI
U34 DSP6
Page 20 of 47
Signal Frequency Source Device
ICS583_PCIE_REF_CLKP7
ICS583_PCIE_REF_CLKN7 100.00MHz
IDT_ ICS853S12AKI
U34 DSP7
ICS583_PCIE_REF_CLKP8
ICS583_PCIE_REF_CLKN8 100.00MHz
IDT_ ICS853S12AKI
U34
PEX8748
U40
5482S_XTALO
5482S_XTALI 25.00MHz Crystal
BCM5482SHA1KFBG
U20
MAIN_48MHZ_CLK_R 48.00MHz Oscillator XILINX XC3S200AN
FPGA1
PCIE_REF_CLK_P
PCIE_REF_CLK_N 100MHz
PCI-E Gold Finger
GF1
IDT_ICS853S12AKI
U34
83PN156_XTAL_OUT
83PN156_XTAL_IN 25.00MHz Crystal
ICS83PN156I
U59
83PN156_SRIO_QN
83PN156_SRIO_QP 156.25MHz Oscillator
80HCPS1616RMI
U10
Table 3: Clock Domains
250Mhz Diff62005_CLK_SSP_CS0
62005_CLK_SSP_CLK
62005_CLK_SSP_MOSI
62005_CLK_SSP_MISO
Control
X'TAL
25Mhz
100Mhz Diff
SRIO_SGMI_CLKP/N
TMS320C6678DSP 0 ~ 7
MCM_CLKP/N
CORE_CLKP/N
DSPn_SRIOSGMII_CLKP/N
250Mhz Diff
250Mhz Diff
100Mhz Diff
166.67Mhz Diff
Clock Diagram
250Mhz Diff
U0
CDCE62005
U4
U3
U2
U1
EN3
TI
CDCLVD110A1:10 LVDS
Clock Buffern 0~7
EN4
DSPn_CORE_CLKP/N
Control
1:10 LVDS
Clock Buffer
TI
CDCLVD110A
n 0~7Control
1:10 LVDS
Clock Buffer
TI
CDCLVD110A
EN2
Control n 0~7
1:10 LVDS
Clock Buffer
TI
CDCLVD110A
EN0
DSPn_MCM_CLKP/N
Control n 0~7
DDR_CLKP/N
166.67Mhz Diff
DSPn_DDR_CLKP/N
Page 21 of 47
DSP3_PCIE_REF_CLKP/N
DSP2_PCIE_REF_CLKP/N
DSP1_PCIE_REF_CLKP/N
DSP0_PCIE_REF_CLKP/N
ICS853S12I
PEX8748_REF_CLKP/N
PCIE_REF_CLK_P/N
100Mhz Diff
Divider
resistor
LVPECL
LVDS
HCSL
DSP2_PCIE_REF_CLKP/N_LVDS
DSP1_PCIE_REF_CLKP/N_LVDS
DSP0_PCIE_REF_CLKP/N_LVDS
DSP3_PCIE_REF_CLKP/N_LVDS
DSP7_PCIE_REF_CLKP/N_LVDS
DSP6_PCIE_REF_CLKP/N_LVDS
DSP5_PCIE_REF_CLKP/N_LVDS
DSP4_PCIE_REF_CLKP/N_LVDS
RC
Transfer
PEX8748_REF_CLKP/N_LVDS
DSP7_PCIE_REF_CLKP/N
DSP6_PCIE_REF_CLKP/N
DSP5_PCIE_REF_CLKP/N
DSP4_PCIE_REF_CLKP/N
PLX
PEX8748
Figure8: DSPC-8682 Carrier Clock Feeding Diagram
Page 22 of 47
2.6 Reset Block Diagram
DSPC-8682 reset mechanism is shown in Figure 9. DSPC-8682 Reset Block Diagram with below
description of the reset sequence on DSPC-8682.
� The FPGA on the card will do the power-on sequence and make all power rails on the card
be ready.
� The FPGA waits for the PWROK on PCI-E golden finger (PCIE_GF_RST#) asserted.
� After PCI-E PWROK asserted as well as all the power on the card valid, the FPGA will
de-assert PEX8748_PCIE_PERST# of PEX8748, the PCI-E switch, 5482S_PHY_RST# of
BCM5482s, the PHY chip, CPS1616_RST# of CPS-1616, SRIO switch, and DSP[0:7]_RESET# on
eight DSP chips.
� To wait for 5mS, the FPGA de-assert the DSP_POR# to eight DSPs.
� To wait for 5mS, the FPAG de-assert the DSP_RESETFULLz to eight DSPs.
� During DSP_RESETFULLz de-asserted, the DSP straps the boot configurations on its own
GPIO pins driven by the FPAG.
� 1ms later after DSP_RESETFULLz de-asserted, the FPGA will set the GPIO pins on the FPGA
side at input, after that, the reset sequence on DSPC-8682 is completed then.
BCM5482S5482S_PHY_RST#
TI
TMS320C6678
PEX8748PEX8748_PCIE_RST#
PCIE_GF_RST#
DSP0 ~ DSP7
XC3S200AN
FPGA
DSP_RESETFULL#
DSP[0..7]_RESET#
DSP_POR#CPS1616_RST#
CPS1616
Figure9: DSPC-8682 Reset Block Diagram
Page 23 of 47
2.7 Reset Sequence
Below figure is provided by TMS320C6678 data manual which describes the reset timings related to
DSP power rails (CVDD, CVDD1, DVDD15 and DVDD18), reference clocks (core clock and DDR3 clock)
and three reset events (RESETz, PORz and RESETFULLz). User can refer to TMS320C6678 Data Manual
on TI webpage for the details.
Figure10: The DSP Reset Sequence on DSPC-8682
Page 24 of 47
2.8 DSP (TI TMS320C6678) Block Diagram
The DSPC-8682 PCI-E add-on card adopts TI 8-core DSP TMS320C6678 and its core frequency is 1GHz.
Figure11: TI TMS320C6678 Block Diagram
2.9 Memory (DDR3)
Four DDR3 memory devices are populated for each DSP on the DSPC-8682 PCI-E add-on card. The
RAM speed is 1333MHz while each DSP connects to four 4G bit (256M x 16) DDR3 devices via DDR
interface.
2.10 SRIO interface
For SRIO connection, It’s has two kind of topology to link. The one DSPC-8682 adopts a ring topology
to chain eight DSPs by one lane SRIO interface. One SRIO lane is connected to previous DSP while
another lane is connected to next DSP on DSPC-8682, e.g. the DSP#7 connects the DSP#0 with x1 SRIO
port and connect the DSP#6 with another x1 SRIO port. The other one topology is link to SRIO GEN2
switch IC (CPS-1616) with 1-laneX2 (Supports Up To 5G baud Per Lane) connected to each DSP.
Page 25 of 47
Figure12: Serial RapidIO Ring
2.11 PCI-E interface
DSPC-8682 adopts a star topology to link host platform with two-lane PCIE interface via a PCI-E Gen3
switch, PEX8748. One PCI-E Gen2 port is designed with two Lanes (supports up to 5G baud per lane)
connected to each DSP.
With PEX8748, it can support up to 12-ports PCI Express switch with 48 lanes of integrated on-chip
SerDes and provide an aggregated bandwidth of up to 768 GT/s. (8.0 GT/s/Lane x 48 SerDes x 2 (full
duplex))
Below table describes the port mapping of PEX8748 on DSPC-8682 while below figure describes the
PCI-E interconnection on DSPC-8682.
Port Function
0 Connects to Host computer (Root Complex) by PCI-E X8
1 Connects to DSP0 through PCI-E X2 interface
2 Connects to DSP1 through PCI-E X2 interface
8 Connects to DSP2 through PCI-E X2 interface
9 Connects to DSP3 through PCI-E X2 interface
10 Connects to DSP4 through PCI-E X2 interface
11 Connects to DSP5 through PCI-E X2 interface
16 Connects to DSP6 through PCI-E X2 interface
17 Connects to DSP7 through PCI-E X2 interface
Page 26 of 47
Table 4: PCI-E port mapping on PEX8748
Figure13: PCIe interconnection
2.12 Ethernet MAC
There are two Gigabit Ethernet MACs in DSP TMS320C6678 and are connected by SGMII SERDES
interface. Therefore, the route of LAN packets is forwarded orderly by LAN port, DSP#0, DSP#1, DSP#2,
DSP#3, DSP#4, DSP#5, DSP#6 and DSP#7. DSPC-8682 adopts a ring topology to chain eight DSPs and
BCM5482S by one lane SGMII interface. One SGMII lane is connected to previous DSP while another
lane is connected to next DSP on DSPC-8682, e.g. the DSP#0 connects the DSP#1 with x1 SGMII port
and connect the DSP#2 with another x1 SGMII port.
On DSPC-8682, a daisy chain for LAN connections in implemented whereas the LAN port is connected
to DSP#0 via a PHY, BCM5482s, to provide 1000BASE-T Gigabit Ethernet feature.
With Ethernet PHY BCM5482S, it supports Ethernet 10/100/1000M bit/s with SGMII interface and
integrates triple-speed Ethernet transceiver-MAC to magnetic, including 1000BASE-T IEEE 802.3ab,
100BASE-TX IEEE802.3u and 10BASE-T IEEE 802.3.
Below figure describes the LAN connection on DSPC-8682.
Page 27 of 47
Figure14: LAN interconnection
2.13 HyperLink interface
Another high-speed interlink, named HyperLink, is implemented on DSPC-8682 to connect each two
DSPs (DSP#0 – DSP#7, DSP#1 – DSP#6, DSP#2 – DSP#5 and DSP#3 – DSP#4) as a pair, and its interface
can provide up to 50GT/s (12.5GT/s per lane) for data transactions.
This HyperLink interface on the TMS320C6678 is used to exchange data between two DSPs with low
latency for the specific process accelerations on DSPC-8682 PCIE card. There are four-lane SerDes
interface designed to operate up to 12.5Gbps per lane. The links of the HyperLink bus on
DSPC-8682 are connected of the DSP#0 and the DSP#7as well as the DSP#1 and DSP#6, DSP#2 and
DSP#5, DSP#3 and DSP#4)
Below figure describes the Hyperlink connection on DSPC-8682.
Page 28 of 47
Figure15: Hyperlink connection
2.14 FGPA XC3S200AN
For FPGA design, Xilinx XC3S200AN is implemented on DSPC-8682 for the power control, DSP boot
configurations, programming clock generators and clock buffers and reset events for DPS farm.
With the programmed FPGA on DSPC-8682, below functions are provided.
� DSP boot mode setting
� Power sequences control
� Enabling / Disabling the device power to meet the power sequence requirement.
� Reset methodology control
� Asserting / De-asserting RESET signals to each chip respectively.
� Configure the clock generator
� Other control functions
Below figure describes the FPGA connection on DSPC-8682.
Page 29 of 47
CLK
MISO
CS0#
PXE8748_INT
CS2#
CS1#
MOSI
INT
PXE8748_SCLK
PXE8748_CS2
PXE8748_CS1
PXE8748_CS0+V1.8
BROADCOM
BCM5482SHA1KFBG
PXE8748_MISO
PXE8748_MOSI
PHY1_LED3
+V3.3
PHY1_LED2
PHY1_LED4
PHY1_LED1
PHY2_LED3PHY2_LED4
PHY2_LED2PHY2_LED1
PXE8748_PCIE_RST#
5482S_PHY_RST#
CPS1616_RST#
5482S_LAN1_ACT
PXE8748
5482S_LAN1_LINK5482S_LAN1_SPEED15482S_LAN1_SPEED2
BCM5482S
CPS1616
5482S_LAN2_LINK5482S_LAN2_SPEED15482S_LAN2_SPEED2
5482S_LAN2_ACT
BROADCOM
IDT
PLX
UCD9244 x 2
PG_VCC0P9VCC5
RT2
RT1
FAN_PWM
PG_VCC5
EN_VCC1P0_2
PG_VCC1P0_2
EN_VCC5
SPI
FPGA
TI_CDCLVD110ARHBR
W83795ADG
SDA_HM
CLK_48M_HM
SCL_HM
HM_ALERT#
CLK_Buf_EN1[0:3]
CLK_Buf_SI1[0:3]
CLK_Buf_CK[0:3]
DVDD_1P8
VCC0P9
VCC1P2
VCC1P5
VCC1P0
VCC3
VCC2P5
Temp_DSP4_7
Hardware
Montor
Temp_DSP0_3
EN_VCC1P0_1
EN_VCC3EN_VCC2P5EN_DVDD1P8
EN_VCC0P9
EN_VCC1P2
PG_CVDD0_3
EN_VCC1P5
POR#
RESET#
RESETFULL#
HOUT
BOOTCOMPLETE
Control
Sequences
Power
Configurations
CLOCK
FPGA_JTAG_TMS
FPGA_JTAG_TDO
FPGA_JTAG_TDI
configurationsBoot & Device
FPGA
JTAG
Control
RESET &
DSP
DSP
Interrupts
Control
PHY
DSP_RESET#DSP_RESETFULL#DSP_POR#
DSP_HOUTDSP_BOOTCOMPLETE
+V3.3
+V1.8
RJ45[1:2]
XILINX_XC3S200AN
RESET+V3.3
+V3.3
+V1.8
PCIE_GF_RST#
FPGA_JTAG_TCK
DSP_GPIO[0 : 15]
GPIO[0:15]
DSPTMS320C6678
PLX
PEX8748
MPS_MP28253EL x4
VOLTERRA_VT237 x4
Power GroupPG_DVDD1P8PG_VCC1P5
PG_CVDD4_7PG_VCC1P0_1
+V3.3
PG_VCC3PG_VCC1P2PG_VCC2P5
62005_CLOCK_PLL_LOCK
62005_CLK_SSP_MISO
TI_CDCE62005
+V3.362005_CLK_SSP_CS0
62005_CLK_SSP_CLKCLOCK Group
62005_CLK_SSP_Power_down#
62005_CLK_SSP_MOSI
Figure16: FPGA connection
Page 30 of 47
2.15 LEDs
The locations of the LED indicators on the DSPC-8682 are shown by below figures. User can find the
indicators easily for specific purpose. The detail descriptions are listed by following sections.
Figure17: TOP Side LED Location
There are LED near CPS-1616, the details are shown below.
LED Function
D1 CPS-1616 error
There are two LEDs near PEX8748, the details are shown below (Table5) .
LED Function
D3 PEX8748 error
D4 PEX8748 interrupt
Table5: PCI-E switch LED
Page 31 of 47
Some LEDs are near XC3S200AN.Four LEDs are used for code debugging and one LED indicates that all
power rails are good. Details are shown as below (Table6)
LED Port
SYSPG_D1 All power rails are good.
FPGA_LED1 Debug LED_1
FPGA_LED2 Debug LED_2
FPGA_LED3 Debug LED_4
FPGA_LED4 Debug LED_3
Table6: FPGA LED
Some LEDs are built in RJ45 connector for RJ45 behavior. The right side LED blinks with green color
when activity occurs normally. The left side LED presents orange color when 1000 BASE-T link is
established. The left side green LED present color when 100 BASE-TX Link is established. If left side LED
is dark, it means 10 BASE-T link is established or no link is established.
Page 32 of 47
3. IO Connector
3.1 Connector Overview
This section describes the pin definition of the connectors on the DSPC-8682 PCIE card. User can have
a detail on the pin signals for further use. For more details, please refer to the related documents from
the website of the manufacturer.
� CN1: The PEX8748, BCM5482S and CPS1616 boundary scan connector, for facility test only.
� CN2: The DSP boundary scan connector, for facility test only.
� CN3: TI 60 pins DSP emulator connector, for software development.
� CN4: RJ45 connectors for LANs. 2 Giga Ethernet ports connected to DSP#0 and DSP#7 for
networking applications.
� CN5: FPGA JTAG connector, for the FPGA debugging and new firmware updating.
� CN6: DC 12V ATX power connector, for increase the 12V input current.
� CN7: FAN connector, for the FAN attached on the heat sink.
� CN8: FAN connector, for the FAN attached on the heat sink.
� COM1: 3 pins UART connector.
� PMBUS1: UCD9244 PMBUS connector.
� 560V2_PWR1: XDS560v2 power connector for XDS560 mezzanine emulator board power
support.
Figure18: Connector Overview
Page 33 of 47
3.2 The PEX8748, BCM5482S and CPS1616 boundary scan connector
In this paragraph, we introduce the boundary scan connector for PEX8748, BCM5482S and CPS1616
CN1: The PEX8748, BCM5482S and CPS1616 boundary scan connector
OUT CHAIN1_JTAG_SW_CTRL (98)
C769
100pF
50V
0402
R788685%
CN1
PH_5x2V_S2.00mm
246810
13579
R134
1K1%
VCC3
OUTCHAIN1_JTAG_TDO(98)OUTCHAIN1_JTAG_TMS(106)OUTCHAIN1_JTAG_TCK(106)
INCHAIN1_JTAG_TDI(103)OUTCHAIN1_JTAG_TRSTN(106)
Figure19:CN1, Boundary Scan for PEX748, BCM5482s and CPS1616
PIN Define PIN Define
1 TRSTn 2 JTAG_SW_CTRL
3 TDI 4 NC
5 TDO 6 GND
7 TMS 8 GND
9 TCK 10 GND
Table7: CN1 Pin Assignment
Page 34 of 47
3.3 TMS320C6678 Boundary Scan Connector
In this paragraph, we introduce the boundary scan connector from the TMS320C6678 DSP.
CN2: TMS320C6678 boundary scan connector
CN2
PH_5x2V_S2.00mm
246810
13579
R126
1K1%
C1
100pF
50V
0402
R43685%
VCC3
OUTCONN40_TCK(106)
INCONN40_TDO(18)OUTCONN40_TDI(106)
OUT JTAG_SW_CTRL (18,106)OUTCONN40_TRSTN(106)
OUTCONN40_TMS(106)
Figure20: CN2, the Boundary Scan for the DSP farm
PIN Define PIN Define
1 TRSTn 2 JTAG_SW_CTRL
3 TDO 4 NC
5 TDI 6 GND
7 TMS 8 GND
9 TCK 10 GND
Table 8: CN2 Pin Assignment
3.4 60 pins DSP emulator connector
In this paragraph, we introduce the 60-pin DSP emulator connector used for XDS562V2.
CN3: 60 pins DSP emulator connector
Page 35 of 47
R2 4.7K
DSP0_TVD
DSP0_EMU_14 DSP0_EMU_14_R
CONN60_TRSTN_1.8V
CONN60_TCK_1.8V
DSP0_EMU_16DSP0_EMU_16_R
DSP_GP0_TDI_LDSP0_EMU_17_R
DSP0_EMU_10DSP0_EMU_10_R
DSP0_EMU_17
DSP0_EMU_03_R DSP0_EMU_03
DSP0_TCKRET
DSP0_EMU_02_RDSP0_EMU_02
CONN60_TDI_1.8V
DSP0_EMU_18DSP0_EMU_18_R
DSP_GP0_TMS_L
DSP0_EMU_11_R DSP0_EMU_11
DSP0_EMU_05_R
DSP0_TCK_RR
DSP0_EMU_05
DSP0_EMU_04DSP0_EMU_04_R
EMU0 and EMU1use to define the id for each DSP codes.
DSP0_EMU_07_R
DSP7_TDO
DSP0_EMU_07
DSP0_EMU_13DSP0_EMU_13_R
DSP_GP0_TRST#
DSP0_EMU_09_R
DSP0_EMU_06_R
DSP0_EMU_09
DSP0_EMU_06
DSP_GP0_TCK_L
TRGRSTZ
DSP0_EMU_15_R
CONN60_TMS_1.8V
DSP0_EMU_15
CONN60_TDIDSP0_EMU_12_R
DSP0_EMU_08DSP0_EMU_08_R
DSP0_EMU_12
Remove terminal resistance
R797 10 5%
R90 10 5%
R149 10 5%
R163 4.7K
R842 10 5%
R875 10 5%
R130 10 5%
R120 NL/10K 1%
R100 10 5%
R864 10 5%
R880 10 5%
R135 10 5%
R103 10 5%
R898 10 5%
R871 10 5%
R876 10 5%
R140 10 5%
R44 10 5%
R106 10 5%R111 100 1%
R872 10 5%
R885 10 5%
R52 10 5%
R141 10 5%
R895 10 5%
R874 10 5%
A1B1
C1
D1PTH
PTH
CN3
BB_30x2V_S1.27mm
A1A2A3A4A5A6A7A8A9
A10A11A12A13A14A15
B1B2B3B4B5B6B7B8B9
B10B11B12B13B14B15
D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15
C1C2C3C4C5C6C7C8C9C10C11C12C13C14C15
H1
H2
DVDD1P8
DVDD1P8BI DSP_EMU_01 (17,26,35,44,53,62,71,80)
OUTCONN60_TMS_1.8V(106)
INDSP7_TDO(18,80)
BIDSP_EMU_00(17,26,35,44,53,62,71,80)
IN DSP0_TCKRET (106)
OUT CONN60_TRSTN_1.8V (106)
OUTCONN60_TCK_1.8V(106)
OUTTRGRSTZ(87)
OUTCONN60_TDI_1.8V(106)
TRGRSTZ
Figure21: CN3, TI 60-pin Emulation Connector
Figure22: Connection the XDS560v2 STM Emulator
Figure23: 60-pin Header Orientation
Page 36 of 47
Figure24: The connection with TI XDS560v2 STM Emulator
Col / Row A B C D
1 GND GND GND NC
2 GND TMS EMU18 GND
3 GND EMU17 TRST# GND
4 GND TDI EMU16 GND
5 GND EMU14 EMU15 GND
6 GND EMU12 EMU13 GND
7 GND TDO EMU11 GND
8 Reserve TVD TCLKRTN GND
9 GND EMU9 EMU10 GND
10 GND EMU7 EMU8 GND
11 GND EMU5 EMU6 GND
12 GND TCLK EMU4 GND
13 GND EMU2 EMU3 GND
14 GND EMU0 EMU1 GND
15 TGRST# GND GND GND
Table 9: CN3 DSP Emulator Pin Assignments
Pin1
Page 37 of 47
3.5 RJ45 LAN connector
In this paragraph, we introduce the RJ45 connector.
CN4: RJ45 connector
R1192 220 5%IN5482S_LAN2_SPEED2(86)
5482S_LAN2_SPEED2
B17 120_100MHz0.5A
B100 120_100MHz0.5A
75
75
75
750.1uF
0.1uF
0.1uF
0.1uF
1000pF
2kV
SHIELD GND
TP0+
TP0-
TP1+
TP1-
TP2+
TP2-
TP3+
TP3-8
5
4
2
1
6
3
7
O
G
G
1
1000pF
3
2kV
7
G SHIELD GND
0.1uF
TP0+
0.1uF
TP0-
TP2-
TP1+
TP3+
TP1-
0.1uF
75
G
TP3-
TP2+
O
75
8
6
0.1uF
5
75
4
75
2
CN4
RJ45_2x1_W/XFMR&LED
A11
A12
A13
A14
H1H2
H3H4
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B5
B1
B2
B3
B4
B7
B8
B9
B10
B6
B13
B14
B11
B12
BI5482S_TRD1_1P(95)
BI5482S_TRD1_0P(95)
BI5482S_TRD1_0N(95)
BI5482S_TRD1_1N(95)
5482S_RJ451_VCCVCC2P5
GND_SHIELD
IN5482S_LAN1_ACT(86)5482S_LAN1_ACT 5482S_LAN1_ACT_RR917 220 5%
5482S_LAN1_LINK_RR1172 220 5%IN5482S_LAN1_LINK(86)
5482S_LAN1_LINK
5482S_LAN1_SPEED2_RR167 220 5%IN5482S_LAN1_SPEED2(86)
5482S_LAN1_SPEED2
IN5482S_LAN1_SPEED1(86)5482S_LAN1_SPEED1_R5482S_LAN1_SPEED1 R918 220 5%
BI5482S_TRD1_2P(95)
R1562 0 5%
BI5482S_TRD1_2N(95)
BI5482S_TRD1_3N(95)
BI5482S_TRD1_3P(95)
BI5482S_TRD2_0P(95)
5482S_LAN2_ACT 5482S_LAN2_ACT_RR901 220 5%IN5482S_LAN2_ACT(86)
IN5482S_LAN2_LINK(86)5482S_LAN2_LINK_R5482S_LAN2_LINK R902 220 5%
BI5482S_TRD2_0N(95)
BI5482S_TRD2_1P(95)
BI5482S_TRD2_1N(95)
VCC2P55482S_RJ452_VCC
BI5482S_TRD2_2P(95)
BI5482S_TRD2_2N(95)
BI5482S_TRD2_3N(95)
BI5482S_TRD2_3P(95)
5482S_LAN2_SPEED1 R1182 220 5%IN5482S_LAN2_SPEED1(86)
5482S_LAN2_SPEED1_R
5482S_LAN2_SPEED2_R
Figure25: CN5, RJ45 LAN port
PIN Define PIN Define
A1 TRD1_0P B1 TRD2_0P
A2 TRD1_0N B2 TRD2_0N
A3 TRD1_1P B3 TRD2_1P
A4 TRD1_1N B4 TRD2_1N
A5 VCC B5 VCC
A6 GND B6 GND
A7 TRD1_2P B7 TRD2_2P
A8 TRD1_2N B8 TRD2_2N
A9 TRD1_3P B9 TRD2_3P
A10 TRD1_3N B10 TRD2_3N
A11 LED1_ LINK B11 LED2_ LINK
A12 LED1_ ACK B12 LED2_ ACK
A13 LED1_SPEED2 B13 LED2_SPEED2
A14 LED1_SPEED1 B14 LED2_SPEED1
Table10: CN4 Pin Assignment
Page 38 of 47
3.6 XILINX XC3S200AN JTAG interface
In this paragraph, we introduce the connector for Xilinx XC3S200AN JTAG interface.
CN5: XILINX XC3S200AN JTAG interface
C78 0.1uF 16V
CN5
PH_6x1V_2.54mm
123456
3VSB
FPGA_JTAG_TCKFPGA_JTAG_TDOFPGA_JTAG_TDIFPGA_JTAG_TMS
Figure26: CN5, the FPGA JTAG for firmware update
PIN Define
1 VCC
2 GND
3 TCK
4 TDO
5 TDI
6 TMS
Table11: CN5 Pin Assignment
Page 39 of 47
3.7 DC 12V ATX power connector
In this paragraph, we introduce the 4-pin 12V ATX connector used to support 12V current rating for
DSPC-8682.
CN6
ATX_3x2H_4.2mm
1
2
3
4
5
6H1
H2
C66310uF16V
VCC12_ATX
C253110uF16V
C6610.1uF16V
Figure27: CN6, 12V connector
PIN Define
1 VCC
2 VCC
3 VCC
4 GND
5 GND
6 GND
Table12: CN6 Pin Assignment
Page 40 of 47
3.8 FAN connector
In this paragraph, we introduce the FAN connector.
CN7: FAN connector
FAN_SPEED1
B27 30_100MHz3A
CN7
WB_3V_2.0mm
123
R147227K5%
C6680.1uF16V
FAN CNN1
D7
BAS32L
300mA12
R1488
4.7K
1%
R1446
10K
5%
C256910uF16V
Figure28: CN7, FAN connector
PIN Define
1 GND
2 VCC
3 Fan speed
Table13: CN7 Pin Assignment
Page 41 of 47
3.9 FAN connector
In this paragraph, we introduce the FAN connector.
CN8: FAN connector
FAN_SPEED2
B108 30_100MHz3A
CN8
WB_3V_2.0mm
123
R146427K5%
C25710.1uF16V
FAN CNN2
D6
BAS32L
300mA12
R679
4.7K
1%
R1463
10K
5%
C257410uF16V
Figure29: CN8, FAN connector
PIN Define
1 GND
2 VCC
3 Fan speed
Table14: CN8 Pin Assignment
Page 42 of 47
4. Jumper and Switch setting
4.1 Boot mode switch
There is one 4-bit sliding switch (SW1) on the board to set the Endian, boot devices and variety of BRA
size for the DSP farm by the FPGA.
Below figure shows the position of the 4-bit sliding switch.
Figure30: The SW1 on DSPC-8682 PCIe Card
Below figure shows the sliding switch circuit and notes the bit number for use.
DSP_BOOT_STRAP3
DSP_BOOT_STRAP0
DSP_BOOT_STRAP2DSP_BOOT_STRAP1
R290 100 1%ONSW1
160_SW_8P_CHS-04TB-2_0
1234 5
8
67R170 10K 5%
R171 10K 5%R289 100 1%
R169 10K 5% R288 100 1%R168 10K 5%
VCC3V3_FPGA
R287 100 1%
Figure31: The SW1 Schematic
Page 43 of 47
The settings of Jumper and switch for DSPC-8682 are described as below table.
Configuration Bit4 Bit3 Bit2 Bit1 Description
Endian Setting - - - ON Big Endian (0)
- - - OFF Little Endian (1)
Boot1 (000) ON ON ON - None Boot (for development)
Boot2 (001) ON ON OFF - I2C Boot from 0x51h SEEPROM
Boot3 (010) ON OFF ON - PCIe Boot
TBD Other states TBD
Table15: The SW1 setting table
The data format configuration, setting is as below.
SW1.bit1 (Endian): 0- Big Endian / 1- Little Endian (default)
The Boot interface of the DSP, the setting is as below.
SW1.bit[4:2]: 000- None boot,
This mode is for the purpose of the development.
SW1.bit[4:2]: 001- I2C boot,
This mode is booting DSP from 0x51h of EEPROM and branch to the PCIE bus for the second
boot (default).
SW1.bit[4:2]: 010- PCIE Boot,
This mode is booting DSP from PCIE interface.
SW1.bit[4:2]: others- reserved for future use.
The default setting of the switch (SW1) on DSPC-8682 is 0x0011b (bit[4:1]: ON, ON, OFF, OFF) for little
endian data format and EEPROM boot from 0x51h.
Page 44 of 47
4.2 S-RIO port wide switch
There is one 4-bit sliding switch (SW2) on the board to set the SRIO configuration. The default routing
table was flashed on EEPROM is SRIO 2x. (It need to re-flash EEPROM if need to change the setting
from 2x to 1x.)
Below figure shows the position of the 4-bit sliding switch.
Below figure shows the sliding switch circuit and notes the quadrant configuration (QCFG) number for
use.
ON
SW2
160_SW_8P_CHS-04TB-2_0
1234 5
8
67
CPS1616_QCFG7CPS1616_QCFG5CPS1616_QCFG3CPS1616_QCFG1R870 0 5%
R869 0 5%R99 0 5%R97 0 5%
Figure32: The SW2 Schematic
Page 45 of 47
The settings of Jumper and switch for DSPC-8682 are described as below table.
Configuration Bit4 Bit3 Bit2 Bit1 Description
QCF[1], QCF[3],
QCF[5], QCF[7]
(0000)
ON ON ON ON The SRIO ports of CPS1616
configure to 2x. (default)
QCF[1], QCF[3],
QCF[5], QCF[7]
(1111)
- - - -
The SRIO ports of CPS1616
configure to 1x. (This setting need
to re-flash routing table from 2x to
1x.)
Table16: The SW2 setting table
Page 46 of 47
5. Mechanical Drawing
Figure33: DSPC-8682 TOP side
Figure34: DSPC-8682 Front Side
Page 47 of 47
Figure 35: DSPC-8682 Bottom Side