DSIDivision of Integrated Systems Design

No switch fabric required

Highlights:

Access and edge routers

Applications:

Truly output queuingHighly integratedLow implementation cost

Up to 32x32 OC-48 portsDedicated physical link between I/O portsZero loss of traffic with no redundancy schemes

Two-chip set

Sophisticated QoS with 16 programmable classes of trafficHighly efficient support for end-to-end flow control

Full Unicast and Multicast supportProven high-speed 3Gbps multidrop serial link structure

Enterprise backbone switchGigabit ethernet3G wireless gatewayStorage area networking

GMDS line card

Gigabit MultiDrop Switch (GMDS)

CSIX compatible I/O interface

S/D

I/F

Linec

ard#3

Queuing&

SchedulingTx

S/D

I/F

Linec

ard#2

Queuing&

SchedulingTx

S/D

I/F

Linec

ard#1

Queuing&

SchedulingTx

S/D

I/F

Linec

ard#4

Queuing&

SchedulingTx

Multi-Pointserial backplane

Line card features:

S/D

I/F

Line

card

#1

Queuing&

SchedulingTx

S/D QueueManager(QM)

Std.RAM

QueueManager(QM)

Std.RAM

QueueManager(QM)

Std.RAM

QueueManager(QM)

Std.RAM

Scheduler(SC)Ingr

ess

Egress

GMDS line card integrates advanced queuing (Queue Manager, QM) and scheduling (Scheduler, SC) functions in a two-chip set architecture. QM manages up to 4 lines from multidrop backplane, storing incoming frames in a high capacity external RAM, and maintaining information about memory usage. SC selects data to be dequeued according to different scheduling algorithms and traffic configuration from QM.

Up to 16 programmable weighted classes of traffic and 4 end-to-end programmable flow control levels supported. The number of QM devices depends on desired number of supported ports. Proven Low-cost line card prototype supporting 8 ports

GMDS Diagram

Line Card Architecture

The Gigabit MultiDrop Switch (GMDS) is a low-cost, high performance switch based on a feasible real output queue architecture. GMDS is based on a two-chip set architecture and a proven high-speed multidrop backplane with dedicated links between I/O ports, which avoid the need for switch fabrics. The GMDS architecture supports sophisticated QoS at the egress ports, which enhance scheduling algorithms effectiveness. Unicast and Multi/Broadcast variable packet size frames are inherently supported for the multidrop backplane, enabling the system for a high efficient bandwidth usage. Ports in GMDS can be scaled in any size from 4x4 to 32x32 OC-48.

Feature System Benefits

External scheduler

• Simpler design. • User defined scheduling algorithms can be integrated. • Weighted, priority, and mixed weighted/priority algorithms supported,

improving system flexibility. • Output queue based robust scheduling algorithm.

External RAM

• Low complexity, reliable and low cost QM design. • High capacity, low cost and relliablestorage. • Number of devices depends on number of switch ports, improving cost

efficiency.

DSIDivision of Integrated Systems Design

Gigabit MultiDrop Switch (GMDS)

Eye diagram @3 Gbps Jitter measurement @3 Gbps

Gigabit multidrop backplane

Trully output queuing architecture is allowed by the multidrop backplane solution. However, traditional stubs result in signal integrity degradation in multidrop backplanes at high-speed, which implies that maximum data-rate on commercial multidrop backplanes is limited to 400 Mbps.

Patent

Pending

Our new developed multidrop serial link structure based on power splitters with matching trace impedance is demonstrated to operate @ 3 Gbps.

Gigabit Multidrop Backplane

GMDS Features

About DSIThe Division of Integrated Systems Design is composed of experienced researchers who are developing commercial products and doing outstanding private and public research in the field of microelectronics since late 80s. The strength of the team is based on its know-how, cutting-edge resources and a set of services which permit to fulfill your company requirements, increasing its competitiveness and international position in new challenging markets.

For more information on DSI’s Gigabit MultiDrop Switch, please contact:

dsi@iuma.ulpgc.es

© 2004 Division of Integrated Systems Design

IUMAUniversidad de Las Palmas de Gran CanariaCampus Universitario de TafiraLas Palmas de Gran Canaria, SPAINTel: +34 928451232 (direct) +34 928451250 (reception desk)Fax: +34 928451243URL: www.iuma.ulpgc.es

Feature System Benefits

Truly OQ architecture • Highly efficient queuing system and QoS traffic shaping

No switch fabric • High reliability and low cost and complexity

Multidrop interconnection • Full Unicast, Multi/Broadband traffic support and end-to-end flow control

Dedicated link between I/O ports

• Highly efficient support for variable packet sizes and bandwidth usage

• Non blocking architecture with no switch fabric.