DS28E05 1- Wire EEPROM - Maxim Integrated · DS28E05 1-Wire EEPROM ... Memory pages can be individually set to write protected or EPROM emulation mode through protection byte settings

DS28E05 1-Wire EEPROM

General DescriptionThe DS28E05 is a 112-byte user-programmable EEPROM organized as 7 pages of 16 bytes each. Memory pages can be individually set to write protected or EPROM emulation mode through protection byte settings. Each part has its own guaranteed unique 64-bit ROM identi-fication number (ROM ID) that is factory programmed into the chip. The DS28E05 communicates over Maxim Integrated’s single contact 1-Wire® interface at overdrive speed with the ROM ID acting as node address in the case of a multiple-device 1-Wire network.

Applications Accessory/PCBIdentification MedicalSensorCalibrationDataStorage AnalogSensorCalibration AftermarketManagementofConsumables

Features Single-Contact1-WireInterface 112BytesUserEEPROMwith1KWriteCycles ProgrammableWriteProtectionandOTPEPROM

EmulationModesforUserMemory UniqueFactory-Programmed64-BitROMIDNumber CommunicateswithHostatUpto76.9kbps

(Overdrive Only) OperatingRange:1.71Vto3.63V,-40°Cto+85°C ±8kVHBMESDProtection(typ)onIOPin 4-BallUCSP,2-PadSFN,3-PinSOT23and6-Pin

TSOCPackages

19-6568; Rev 2; 1/17

Ordering Information appears at end of data sheet.

Typical Application Circuit

1-Wire is a registered trademark of Maxim Integrated Products, Inc.

µC

PIOX

PIOY

100kΩ

DS28E05

RPUP

VCC

Q1

IO

*NOTE: OPTIONAL Q1 LOW-IMPEDANCE BYPASS OR EQUALLY DRIVE LOGIC ‘1’ WITH PIOY

BIDIRECTIONAL

GND

VCC

GND OPEN DRAIN PORT

1kΩ

*PMV65XP


www.maximintegrated.com Maxim Integrated 2

Electrical Characteristics(TA=-40°Cto+85°C,unlessotherwisenoted.)(Note1)

IOVoltageRangetoGND ....................................-0.5Vto3.63VIOSinkCurrent.................................................................±20mAOperating Temperature Range .......................... -40°Cto+85°CJunction Temperature ......................................................+150°C

Storage Temperature Range ............................ -55°Cto+125°CLeadTemperature(soldering,10s) .................................+300°CSoldering Temperature (reflow) ......................................+260°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Absolute Maximum Ratings

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSIO PIN: GENERAL DATA1-WirePullupVoltage VPUP (Note2) 1.71 3.63 V

1-Wire Pullup Resistance RPUPVPUP=2.75Vto3.63V(Note3) 300 1500

ΩVPUP=1.71Vto2.75V(Note3) 300 750

InputCapacitance CIO (Notes4,5) 1500 pF

InputLoadCurrent ILIOpinatVPUP 5 20

µAIOpinatVPUP=1.8V+5% 2 8

High-to-LowSwitchingThreshold VTL (Notes6,7) 0.65 x VPUP

V

InputLowVoltage VILVPUP=2.75Vto3.63V(Notes2,8) 0.5 V

VPUP=1.71Vto2.75V(Notes2,8) 0.3

Low-to-HighSwitchingThreshold VTH (Notes6,9) 0.75 x VPUP

V

SwitchingHysteresis VHYVPUP=2.75Vto3.63V(Notes6,10) 0.3 V

VPUP=1.71Vto2.75V(Notes6,10) 0.17

OutputLowVoltage VOLVPUP=1.89Vto3.63V,IOL=4mA(Note11) 0.4 V

VPUP=1.71Vto1.89V,IOL=2mA(Note11) 0.4

Recovery Time tREC (Notes2,12) 5 µs

Time Slot Duration tSLOT (Notes2,13) 13 µs

IO PIN: 1-Wire RESET, PRESENCE DETECT CYCLEReset Low Time tRSTL (Note2) 48 80 µs

ResetHighTime tRSTH (Note14) 48 µs

Presence Detect Sample Time tMSP (Notes2,15) 8 10 µs

IO PIN: 1-Wire WRITEWrite-Zero Low Time tW0L (Notes2,16) 8 16 µs

Write-One Low Time tW1L (Notes2,16) 0.25 2 µs

IO PIN: 1-Wire READRead Low Time tRL (Notes2,17) 0.25 2-δ µs

Read Sample Time tMSR (Notes2,17) tRL+δ 2 µs



Electrical Characteristics (continued)(TA=-40°Cto+85°C,unlessotherwisenoted.)(Note1)

Note 1: Limitsare100%productiontestedatTA=+25°Cand/orTA=+85°C.Limitsovertheoperatingtemperaturerangeandrel-evant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.

Note 2: System requirement.Note 3: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery

times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.Note 4: TypicalvaluerepresentstheinternalparasitecapacitancewhenVPUP is first applied. Once the parasite capacitance is

charged,itdoesnotaffectnormalcommunication.Note 5: Guaranteedbydesignand/orcharacterizationonly.Notproductiontested.Note 6: VTL,VTH,andVHYareafunctionoftheinternalsupplyvoltage,whichisafunctionofVPUP,RPUP,1-Wiretiming,and

capacitiveloadingonIO.LowerVPUP,higherRPUP,shortertREC,andheaviercapacitiveloadingallleadtolowervaluesofVTL,VTH,andVHY.

Note 7: Voltagebelowwhich,duringafallingedgeonIO,alogic0isdetected.Note 8: ThevoltageonIOmustbelessthanorequaltoVILMAX at all times the master is driving IO to a logic 0 level.Note 9: Voltageabovewhich,duringarisingedgeonIO,alogic1isdetected.Note 10:AfterVTHiscrossedduringarisingedgeonIO,thevoltageonIOmustdropbyatleastVHY to be detected as logic 0.Note 11:TheI-Vcharacteristicislinearforvoltageslessthan1V.Note 12:Appliestoasingledeviceattachedtoa1-Wireline.Note 13:Definesmaximumpossiblebitrate.Equalto1/(tW0LMIN+tRECMIN).Note 14:Anadditionalresetorcommunicationsequencecannotbeginuntiltheresethightimehasexpired.Note 15: Interval after tRSTL during which a bus master can read a logic 0 on IO if there is a DS28E05 present. The power-up pres-

encedetectpulsecouldbeoutsidethisintervalbutwillbecompletewithin2msfora3.3VVPUPor20msfora1.8VVPUP after power-up.

Note 16:εinFigure10representsthetimerequiredforthepullupcircuitrytopullthevoltageonIOupfromVILtoVTH. The actual maximum duration for the master to pull the line low is tW1LMAX+tF-εandtW0LMAX+tF-ε,respectively.

Note 17:δinFigure10representsthetimerequiredforthepullupcircuitrytopullthevoltageonIOupfromVIL to the input-high threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX+tF.

Note 18:CurrentdrawnfromIOduringtheEEPROMprogramminginterval,duringwhichthevoltageatIOmustnotdropbelow1.69V.

Note 19: The tPROG interval begins immediately after the trailing rising edge on IO for the last time slot of the Release byte for a valid Write Memory sequence. Interval ends once the device’s self-timed EEPROM programming cycle is complete and the current drawn by the device has returned from IPROG to IL.

Note 20:Write-cycleenduranceistestedincompliancewithJESD47G.Note 21:Not100%productiontested;guaranteedbyreliabilitymonitorsampling.Note 22:DataretentionistestedincompliancewithJESD47G.Note 23:Guaranteedby100%productiontestatelevatedtemperatureforashortertime;equivalenceofthisproductiontesttothe

data sheet limit at operating temperature range is established by reliability testing.Note 24: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated tem-

peratures is not recommended.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSEEPROMProgrammingCurrent IPROG (Notes5,18) 400 µA

ProgrammingTimefora16-BitSegment tPROG (Note19) 16 ms

Write/EraseCyclingEndurance NCY TA=+85°C(Notes20,21) 1000 —

Data Retention tDR TA=+85°C(Notes22,23,24) 10 Years



Pin Descriptions

Pin Configurations

Detailed DescriptionTheDS28E05combines896bitsofuserEEPROMorga-nized as seven 128-bit pages, 64 bits of administrativedatamemory,anda64-bitROMIDinasinglechip.Datais transferredserially throughthe1-Wireprotocol,whichrequires only a single data lead and a ground return.The user memory can have unrestricted write access (fac-torydefault),orcanbewriteprotectedorputinEPROMemulation mode. Write protection prevents changes to the memory data. EPROM emulation mode logically ANDsmemorydatawithincomingnewdata,whichallowschangingbitsfrom1to0,butnotviceversa.Bychang-ing one bit at a time this mode could be used to create nonvolatile nonresettable counters. For more detailsrefer to ApplicationNote5042:Implementing Nonvolatile, Nonresettable Counters for Embedded Systems.The device’s 64-bit ROM ID can be used to electronically identify the equipment in which the DS28E05 is used. The ROM ID guarantees unique identification and is also used to address the device in a multidrop 1-Wire network environment, where multiple devices reside on a com-mon 1-Wire bus and operate independently of each other. Applications includeaccessory/PCB identification,medi-calsensorcalibrationdatastorage,analogsensorcalibra-tion,andafter-marketmanagementofconsumables.

OverviewThe block diagram in Figure 1 shows the relationships between the major control and memory sections of the DS28E05. The DS28E05 has three main data compo-nents: seven 128-bit pages of user EEPROM, 64 bitsof administrative data memory, and a 64-bit ROM ID.Figure 2 shows the hierarchic structure of the 1-Wire protocol. The bus master must first provide one of the fiveROMfunctioncommands:ReadROM,MatchROM,Search ROM, Skip ROM, or Resume Communication.The protocol required for these ROM function commands is described in Figure8.AfteraROMfunctioncommandissuccessfullyexecuted, thememory functionsbecomeaccessible and the master can select one of the two memory function commands. The function protocols are described in Figure6. All data is read and written least significant bit first.

64-Bit ROM IDEach DS28E05 contains a unique ROM ID that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a cyclic redundancy check (CRC)of the first 56bits.SeeFigure3fordetails.The1-WireCRCisgeneratedusinga polynomial generator consisting of a shift register and XORgatesasshowninFigure4.

PINNAME FUNCTION

SFN BUMP SOT23 TSOC— — 2 3–6 N.C. NotConnected1 A2,B2 1 2 IO 1-WireBusInterface.Open-drainsignalthatrequiresanexternalpullupresistor.2 A1,B1 3 1 GND GroundReference

N.C.

IO

GND

N.C.

N.C.

N.C.

TSOC

+

5

4

6

2

3

1

DS28E05DS28E05GB+

DS28E05

N.C.

1

3 GND

THE SFN PACKAGE IS QUALIFIED FOR ELECTRO-MECHANICALCONTACT USE CASES ONLY. NOT FOR SOLDERING.

SFN(3.5mm x 5mm x 0.35mm)

IO+

0Drr

SOT23

2

UCSP

TOP VIEW BOTTOM VIEW

DS28E05

1

B

A

2

GND

GND

IO

IO

+

GND IO

NOTE:

http://www.maximintegrated.com/an5042




Figure 1. Block Diagram

Figure 2. Hierarchical Structure for 1-Wire Protocol

Figure 3. 64-Bit ROM ID

ThepolynomialisX8+X5+X4+1.Additionalinformationabout the1-WireCyclicRedundancyCheck isavailablein ApplicationNote27:Understanding and Using Cyclic Redundancy Checks with Maxim iButton® Products.

The shift register bits are initialized to 0.Then, startingwiththeleastsignificantbitofthefamilycode,onebitatatimeisshiftedin.Afterthe8thbitofthefamilycodehasbeenentered,theserialnumberisentered.Afterthelastbitof theserialnumberhasbeenentered, theshift reg-istercontainstheCRCvalue.Shiftinginthe8bitsoftheCRCreturnstheshiftregistertoall0s.

iButton is a registered trademark of Maxim Integrated Products, Inc.

DS28E05

1-Wire FUNCTIONCONTROL

1-Wire NET

PARASITE POWER

64-BITROM ID

ADMINISTRATIVE DATA(64 BITS)

USER EEPROM7 PAGES OF

(128 BITS EACH)

MEMORYFUNCTIONCONTROL

AVAILABLE COMMANDS: DATA FIELD AFFECTED:

READ ROMMATCH ROMSEARCH ROMSKIP ROMRESUME

64-BIT ROM ID, RC-FLAG64-BIT ROM ID, RC-FLAG64-BIT ROM ID, RC-FLAGRC-FLAGRC-FLAG

1-Wire ROMFUNCTION COMMANDS

WRITE MEMORYREAD MEMORY

USER MEMORY, ADMINISTRATIVE DATAUSER MEMORY, ADMINISTRATIVE DATA

DS28EL05-SPECIFICMEMORY FUNCTION COMMANDS

COMMAND LEVEL:

DS28E05

MSb

8-BITCRC CODE 48-BIT SERIAL NUMBER

MSb LSb MSb

LSb

LSb

8-BIT FAMILY CODE(0Dh)

MSbLSb





Table 1. Memory Resources

Table 2. Address to Segment Mapping

Memory ResourcesThememoryof theDS28E05 consists of usermemory,administrative data, and a ROM ID.Table 1 shows the size, accessmodeand purpose of the variousmemoryareas.Bracketsaroundanaccessmodeindicatepossiblerestrictions,suchaswriteprotectionorreadprotection.The memory is organized as 8 pages of 16 bytes each (Figure 5). Each page consists of 8 segments. Table 2 shows how the segments relate to a memory address. Pages 0 to 6 are the user memory. Page 7 contains

the administrative data and the ROM ID. The function memory locations 0074h to 0075h depends on the code in the Factory Word (addresses 0076h to 0077h). TheManufacturer ID can be a customer-supplied identification code that assists the application software in identifying theproducttheDS28E05isassociatedwith.Contactthefactory to set up and register a custom manufacturer ID.Write protection or EPROM emulation mode is activated through the Write Memory command by writing to the correspondinglocations(PPAtoPPD)intheadministra-tivedatapage.Onceaprotection isactivated, itcannot

Figure 4. 1-Wire CRC Generator

Legend: (5Fh) → designates memory location 5Fh. Text without brackets refers to the register name.

NAME SIZE (BYTES) ACCESS MODE PURPOSE

Usermemory(EEPROM) 112 Read,(Write) Application-specificdatastorage

Administrativedata 8 Read,(Write),Internal Read Pageprotectionsettings,factorybytes,userbytes/manufacturerID

ROM ID 8 Read,InternalRead 1-Wire network device address

Segment 7 Segment 6 Segment 5 Segment 4 Segment3 Segment 2 Segment 1 Segment 0B1 B0 B1 B0 B1 B0 B1 B0 B1 B0 B1 B0 B1 B0 B1 B0

Page 0 (0Fh) (08h) (00h)Page 1 (1Fh) (18h) (10h)Page 2 (2Fh) (28h) (20h)Page3 (3Fh) (38h) (30h)Page 4 (4Fh) (48h) (40h)Page 5 (5Fh) (58h) (50h)Page 6 (6Fh) (68h) (60h)Page 7 ROM ID Factory MAN.ID/U. PPD PPC PPB PPA

1STSTAGE

2NDSTAGE

3RDSTAGE

4THSTAGE

7THSTAGE

8THSTAGE

6THSTAGE

5THSTAGE

X0 X1 X2 X3 X4

POLYNOMIAL = X8 + X5 + X4 + 1

INPUT DATA

X5 X6 X7 X8



Figure 5. User Memory Map

bereversed.Oncethepageprotectionsarefinalized,thecopy lock nibble (73h, upper) should be set to preventchanges. The protection settings are read-accessible through the Read Memory command. See the Memory Function Commands section for command flow details.The ROM ID uniquely identifies each individual DS28E05 and serves as network address in a multidrop 1-Wire network. The ROM ID can be read through the ROM

Functioncommands;itisalsoread-accessibleaspartofthe 8th memory page. The family code is stored at the lower address (78h).

Memory Function CommandsThe memory function flowchart (Figure6) describes the protocols to access the memory of the DS28E05. The memory is written in segments of 2 bytes.

ADDRESS RANGE TYPE DESCRIPTION PROTECTION CODES0000hto000Fh R/(W) Usermemorypage0 —0010hto001Fh R/(W) Usermemorypage1 —0020hto002Fh R/(W) Usermemorypage2 —0030hto003Fh R/(W) Usermemorypage3 —0040hto004Fh R/(W) Usermemorypage4 —0050hto005Fh R/(W) Usermemorypage5 —0060hto006Fh R/(W) Usermemorypage6 —

0070h* R/(W)PageprotectionPPA,lowernibble:page0;uppernibble:page1

0h:open(factorydefault);Ah:EPROMmode;allothercodes:writeprotected

0071h* R/(W)PageprotectionPPB,lowernibble:page2,uppernibble:page3


0072h* R/(W)PageprotectionPPC,lowernibble:page4,uppernibble:page5


0073h* R/(W)PageprotectionPPD,lowernibble:page6,uppernibble:copylock

0h:open(factorydefault);Ah:EPROMmode;allothercodes:writeprotectedCopylock0h:open(factorydefault);allothercodes:PageprotectionlocationsPPA,PPB,PPC,PPDwriteprotected.Preventschangestothepage modes.

0074h to 0075h R/(W) ManufacturerID/Userbytes —

0076h to 0077h R FactoryWord.Setatfactory.

C3A9h:addresses0074hto0075hareuserbytes.3C56h:addresses0074hto0075harewriteprotectedandhold a Manufacturer ID.

0078hto007Fh RROMID,alternate

readout (family code at address 0078h)

—

*ONCEANIBBLEISPROGRAMMEDTOANYTHINGOTHERTHAN0h,THENIBBLECANNOTBECHANGED.



Figure 6. Memory Functions Flowchart

MASTER TxSTARTING ADDRESS T[15:0]

Y

Y

Y

N

Y

F0hREAD MEMORY?

N

N

ADDRESS< 0080h?

MASTERTx RESET?

MASTERTx RESET?

END OFMEMORY?

MASTER Tx MEMORYFUNCTION COMMAND

DS28EL05 SETS MEMORYADDRESS = (T[15:0])

MASTER Rx (READS BACK)2 DATA BYTES AND VERIFIES

MASTER RxDATA BYTE FROM

MEMORY ADDRESS

DS28EL05INCREMENTS

ADDRESSCOUNTER

MASTERRx “1”s

FROM ROM FUNCTIONSFLOWCHART (FIGURE 8)

TO ROM FUNCTIONSFLOWCHART (FIGURE 8)

MASTER Tx PARAMETER BYTE

Y

Y

Y

55hWRITE MEMORY?

N

MASTERTx FFh RELEASE

BYTE?

PARAMETERBYTE AND FFh BYTE

VALID?

MASTER Tx FFh BYTE

MASTER WAITS 1 x tPROG*

MASTER Rx CS BYTE

MASTER Tx 2 DATA BYTES

MASTERTx RESET?

SEGMENT #= 7?

Y

N

N

Y

MASTERTx RESET?

*1-Wire IDLE HIGH FOR POWER.

Y

N

N

N

MASTERRx “1”s

N

Y

N

DS28EL05INCREMENTS

ADDRESSCOUNTER



Write Memory [55h]The Write Memory command is used to program one or more contiguous 2-byte segments of a memory page. This com-mand is applicable only to memory locations that are not write protected. The parameter byte specifies the page and segmentnumberwherethewritingbegins.ThenewsegmentdataistransmittedinthesequenceB0,B1.Table 2 shows the how these bytes map to the addressed memory page. The command flow allows writing one or multiple adjacent segmentswithinapage.Tosafeguardagainsttransmissionerrors,theDS28E05supportsread-after-writeverification.Incaseofdataerror,themasterabortsthecommandbyissuinga1-Wirereset.TostartthetransfertoEEPROMthemastermusttransmitareleasebyte(FFh).Aftertheprogrammingtimeisover,theDS28E05transmitsaCSbyte.IfapageisinEPROMemulationmode,thenewsegmentdataisthebitwiseANDofthesegmentdatainmemoryandthenew data provided with the command.

Bits 6:4: Memory Page Selection (PAGE #).Thesebitsspecifythememorypagethatistobewrittento.Validmemorypage numbers are 000b (page 0) to 111b (page 7).Bits 3:1: Starting Segment Selection (SEG #). These bits specify the location within the selected memory page where thewritingbegins.Forpages0to6validsegmentnumbersare000b(startofmemorypage)to111b(lastsegmentofmemorypage).Validsegmentnumbersforpage7are000b,001b,and010b.

Table 3. Parameter Byte Bitmap

Note: The bits marked as 0 must be transmitted as 0 for the parameter byte to be valid.

Write MemoryCommandCode 55hParameterByte Targetpageselection,startingsegmentnumber(Table3).Restrictions The memory page must not be write protected.

ProtocolVariations Writing within a page.Writing through the end of the page.

Error conditions Invalid parameter byte.The memory page is write protected.

CSByte AAh=success.33h=Thecommandfailedbecausethepageiswriteprotected.

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 00 PAGE# SEG# 0



Read Memory [F0h]TheReadMemorycommandisusedtoreadthememory.Thecommandneedsa16-bitstartingaddressTA1,TA2.Theparameterbytespecifiestheloweraddressbyte(TA1,T[6:0])wherethereadingbegins.Aftertheparameterbyte,themastertransmitsTA2(T[15:8]),whichmustbe00tobevalid.Thereadingcanstartatanyvalidstartingaddressandcontinuetroughtheendofthememory.Ifmemorypage7isreadandthemastercontinuesreading,theresultingdataisFFh.ThemastercanendtheReadMemorycommandatanytimebyissuingaresetpulse.

1-Wire Bus SystemThe 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances the DS28E05 is a slave device. The discussion of this bus system is broken down into three topics: hardware configuration,transactionsequence,and1-Wiresignaling(signaltypesand timing). The 1-Wire protocol defines bus transactions intermsofthebusstateduringspecifictimeslots,whichare initiated on the falling edge of sync pulses from the bus master.

Hardware ConfigurationThe1-Wirebushasonlyasingle linebydefinition; it isimportant that each device on the bus be able to drive it at the appropriate time.To facilitate this, each deviceattached to the 1-Wire bus must have open-drain or three-state outputs. The 1-Wire port of the DS28E05 is open drain with an internal circuit equivalent to that shown in Figure7.

Table 4. Parameter Byte Bitmap

Note: The bit marked as 0 must be transmitted as 0 for the parameter byte to be valid.

Figure 7. Hardware Configuration

Read MemoryCommandCode F0hParameterByte Starting memory address (Table 4).Restrictions None.Thiscommandcanbeissuedatanytime.ProtocolVariations None.Error conditions Invalid parameter byte.CSByte N/A

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 00 TA1

Rx

RPUP

IL

VPUP

BUS MASTER

THREE STATEOR OPEN-DRAIN

PORT PIN

100Ω MOSFETAT 3.3V OR

200Ω MOSFET AT 1.8V

Tx

Rx

Tx

DATA

DS28E05 1-Wire PORT

Rx = RECEIVETx = TRANSMIT



A multidrop bus consists of a 1-Wire bus with multipleslaves attached. The DS28E05 supports overdrive speed of76.9kbps(max)onlyandcannotbeusedtogetherwithstandard speed or dual-speed 1-Wire slaves on the bus. The value of the pullup resistor primarily depends on the 1-Wirepullupvoltage,networksizeand loadconditions.The DS28E05 requires a pullup resistor of maximum 1.5kΩfor3.3Voperationorapullupresistorofmaximum750Ωfor1.8Voperation.The idle state for the 1-Wire bus is high. If for any reason atransactionmustbesuspended,thebusmustbeleftinthe idle state if the transaction is to resume. If this does notoccurandthebusisleftlowformorethan16µs,oneor more devices on the bus could be reset.

Transaction SequenceThe protocol for accessing the DS28E05 through the 1-Wireportisasfollows:• Initialization• ROMFunctionCommand• MemoryFunctionCommand• Transaction Data

InitializationAlltransactionsonthe1-Wirebusbeginwithaninitializa-tion sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The pres-ence pulse lets the bus master know that the DS28E05 is onthebusandisreadytooperate.Formoredetails,seethe 1-Wire Signaling section.

1-Wire ROM Function CommandsOnce the bus master has detected a presence, it canissue one of the five ROM function commands that the DS28E05 supports.All ROM function commands are 8bitslong.Alistofthesecommandsfollows(seetheflow-chart in Figure8).

Read ROM [33h]The Read ROM command allows the bus master to read theDS28E05’sROMID(8-bitfamilycode,unique48-bitserial number, and8-bitCRC).This commandcanonlybe used if there is a single slave on the bus. If more than oneslave ispresenton thebus,adatacollisionoccurs

when all slaves try to transmit at the same time (open drainproducesawired-ANDresult).Thefamilycodeand48-bit serial number as read by the master are unlikely to matchtheCRC.

Match ROM [55h]TheMatchROMcommand,followedbya64-bitROMID,allows the bus master to address a specific DS28E05 on a multidrop bus. Only the DS28E05 that exactly matches the 64-bit ROM ID responds to the following memory functioncommand.Allotherslaveswaitforaresetpulse.This command can be used with a single or multiple devices on the bus.

Search ROM [F0h]When a system is initially brought up, the bus mastermight not know the number of devices on the 1-Wire bus or their ROM ID numbers. By taking advantage of thewired-ANDpropertyofthebus,themastercanuseapro-cess of elimination to identify the ID of all slave devices. ForeachbitoftheIDnumber,startingwiththeleastsig-nificantbit, thebusmaster issuesa tripletof timeslots.On the first slot, each slave device participating in thesearch outputs the true value of its ID number bit. On the secondslot,eachslavedeviceparticipatinginthesearchoutputs the complemented value of its ID number bit. On the thirdslot, themasterwrites the truevalueof thebitto be selected.All slave devices that do notmatch thebit written by the master stop participating in the search. If bothof the readbitsarezero, themaster knows thatslavedevicesexistwithbothstatesofthebit.Bychoos-ingwhichstate towrite, thebusmasterbranches in thesearch tree. After one complete pass, the bus masterknowstheROMIDnumberofasingledevice.Additionalpasses identify the ID numbers of the remaining devices. Refer to ApplicationNote187:1-Wire Search Algorithm foradetaileddiscussion,includinganexample.

Skip ROM [CCh]This command can save time in a single-drop bus sys-tem by allowing the bus master to access the memory functions without providing the 64-bit ROM ID. If more thanoneslave ispresenton thebusand, forexample,a read command is issued following the Skip ROM com-mand,datacollisionoccursonthebusasmultipleslavestransmit simultaneously (open-drain pulldowns produce a wired-ANDresult).




Figure 8. ROM Functions Flowchart

DS28EL05 TxPRESENCE PULSE

BUS MASTER TxRESET PULSE

BUS MASTER Tx ROMFUNCTION COMMAND

DS28EL05 TxCRC BYTE

DS28EL05 TxFAMILY CODE

(1 BYTE)

DS28EL05 TxSERIAL NUMBER

(6 BYTES)

RC = 0

MASTER Tx BIT 0

RC = 0 RC = 0 RC = 0

YYY

Y

Y

Y

Y

33hREAD ROMCOMMAND?

N55h

MATCH ROMCOMMAND?

BIT 0 MATCH? BIT 0 MATCH?

N

N N

N N

N N

F0hSEARCH ROMCOMMAND?

NCCh

SKIP ROMCOMMAND?

N

RC = 1

MASTER Tx BIT 1

MASTER Tx BIT 63

BIT 1 MATCH?

BIT 63 MATCH?

Y

Y

RC = 1

FROM MEMORY FUNCTIONFLOWCHART (FIGURE 6)

TO MEMORY FUNCTIONSFLOWCHART (FIGURE 6)

DS28EL05 Tx BIT 0DS28EL05 Tx BIT 0MASTER Tx BIT 0

BIT 1 MATCH?

BIT 63 MATCH?



Y

RC = 1?

Y

A5hRESUME

COMMAND?N

N

Y

YMASTER TxRESET?

N



Resume Command [A5h]To maximize the data throughput in a multidrop environ-ment,theResumecommandisavailable.Thiscommandchecks the status of theRCbit and, if it is set, directlytransfers control to the memory functions, similar to aSkipROMcommand.Theonlyway toset theRCbit isthrough successfully executing the Match ROM or Search ROMcommand.Once theRCbit isset, thedevicecanrepeatedly be accessed through the Resume command. Accessinganotherdeviceon thebusclears theRCbit,preventing two or more devices from simultaneously responding to the Resume command.

1-Wire SignalingThe DS28E05 requires strict protocols to ensure data integrity. The protocol consists of four types of signaling ononeline:resetsequencewithresetpulseandpresencepulse,write-zero,write-one,andread-data.Exceptforthepresencepulse, thebusmaster initiatesall fallingedges.The DS28E05 communicates at overdrive speed only.Togetfromidletoactive,thevoltageonthe1-Wire lineneedstofallfromVPUPbelowthethresholdVTL. To get fromactivetoidle,thevoltageneedstorisefromVIL(MAX) pastthethresholdVTH. The time it takes for the voltage to make this rise is seen in Figure9asε,anditsdurationdepends on the pullup resistor (RPUP) used and the capacitance of the 1-Wire network attached. The voltage VIL(MAX) is relevant for the DS28E05 when determining a logicallevel,nottriggeringanyevents.Figure 9 shows the initialization sequence required to begin any communication with the DS28E05. A resetpulse followed by a presence pulse indicates that the DS28E05isreadytoreceivedata,giventhecorrectROM

and memory function command. If the bus master uses slew-ratecontrolonthefallingedge,itmustpulldowntheline for tRSTL+tF to compensate for the edge.After the bus master has released the line it goes intoreceivemode.Nowthe1-WirebusispulledtoVPUP through thepullupresistor.WhenthethresholdVTHiscrossed,theDS28E05 waits and then transmits a presence pulse by pullingthelinelow.Todetectapresencepulse,themastermust test the logical state of the 1-Wire line at tMSP.

Read-/Write-Time SlotsData communication with the DS28E05 takes place in time slots that carry a single bit each. Write time slots transport data from bus master to slave. Read time slots transfer data from slave to master. Figure 10 illustrates the definitions of the write- and read-time slots.Allcommunicationbeginswiththemasterpullingthedataline low. As the voltage on the 1-Wire line falls belowthethresholdVTL,theDS28E05startsitsinternaltiminggenerator that determines when the data line is sampled during a write time slot and how long data is valid during a read time slot.

Master-to-SlaveFor a write-one time slot, the voltage on the data linemust have crossed the VTH threshold before the write-one low time tW1L(MAX)isexpired.Forawrite-zerotimeslot, the voltage on the data line must stay below theVTH threshold until the write-zero low time tW0L(MIN) is expired.Forthemostreliablecommunication,thevoltageon thedata line shouldnot exceedVIL(MAX) during the entire tW0L or tW1Lwindow.AftertheVTH threshold has beencrossed,theDS28E05needsarecoverytimetREC before it is ready for the next time slot.

Figure 9. Initialization Procedure: Reset and Presence Pulse

RESISTOR MASTER DS28EL05

tRSTL

tRSTH

MASTER Tx "RESET PULSE" MASTER Rx "PRESENCE PULSE"

VPUPVIHMASTER

VTH

VTLVIL(MAX)

0V

ε

tF

tREC

tMSP



Slave-to-MasterAread-datatimeslotbeginslikeawrite-onetimeslot.ThevoltageonthedatalinemustremainbelowVTL until the read low time tRL is expired. During the tRLwindow,whenrespondingwitha0,theDS28E05startspullingthedata

linelow;itsinternaltiminggeneratordetermineswhenthispulldown ends and the voltage starts rising again. When respondingwitha1,theDS28E05doesnotholdthedatalinelowatall,andthevoltagestartsrisingassoonastRL is over.

Figure 10. Read/Write Timing Diagrams

RESISTOR MASTER

RESISTOR MASTER

RESISTOR MASTER DS28EL05

ε

ε

δ

VPUPVIHMASTER

VTH

VTLVIL(MAX)

0VtF

VPUPVIHMASTER

VTH

VTLVIL(MAX)

0VtF

VPUPVIHMASTER

VTH

VTLVIL(MAX)

0VtF

tSLOT

tW1L

tRECtSLOT

tSLOT

tW0L

tREC

MASTERSAMPLINGWINDOW

tRL

tMSR

WRITE-ONE TIME SLOT

WRITE-ZERO TIME SLOT

READ-DATA TIME SLOT



The sum of tRL+δ(risetime)ononesideandtheinternaltiming generator of the DS28E05 on the other side define the master sampling window (tMSR(MIN) to tMSR(MAX)),inwhich the master must perform a read from the data line. For themost reliable communication, tRL should be as shortaspermissible,andthemastershouldreadclosetobut no later than tMSR(MAX).Afterreadingfromthedataline, the master must wait until tSLOT is expired. This guarantees sufficient recovery time tREC for the DS28E05 togetreadyforthenexttimeslot.NotethattREC specified herein applies only to a single DS28E05 attached to a 1-Wireline.Formultideviceconfigurations,tREC must be extended to accommodate the additional 1-Wire device input capacitance.

Improved Network Behavior (Switchpoint Hysteresis)Ina1-Wireenvironment, line termination ispossibleonlyduring transients controlled by the bus master (1-Wire driver). 1-Wire networks, therefore, are susceptible tonoise of various origins. Depending on the physical size and topology of the network, reflections from end pointsand branch points can add up or cancel each other to some extent. Such reflections are visible as glitches or

ringingon the1-Wirecommunication line.Noisecoupledonto the 1-Wire line from external sources can also result insignalglitching.Aglitchduringtherisingedgeofatimeslot can cause a slave device to lose synchronization with the master and, consequently, result in a SearchROM command coming to a dead end or cause a device-specific function command to abort. The DS28E05 uses a 1-Wire front-end with built-in hysteresis at the low-to-high switchingthresholdVTH.IfanegativeglitchcrossesVTH butdoesnotgobelowVTL,itisnotrecognized(Figure11).

1-Wire Communication ExamplesSee Table 5 and Table 6 for the 1-Wire communication legend and data direction codes.

Figure 11. Noise Suppression Scheme

Table 5. 1-Wire Communication Legend

Table 6. Data Direction Codes

SYMBOL DESCRIPTIONRST 1-Wire reset pulse generated by masterPD 1-Wire presence detect pulse generated by slave

Select CommandanddatatosatisfytheROMfunctionprotocolPB Parameter byteCS CommandSuccessindicator

Release FFhbytesentbythemastertostartawriteactivityintheslaveWM Command“WriteMemory”RM Command“ReadMemory”

<n bytes> Transfer of n bytes<data to EOP> Transfer of as many bytes as are needed to reach the end of the page

Data Transfer of 2 bytes segment dataFFloop IndefiniteloopwherethebusmasterreadsFFhbytes

Master-to-Slave Slave-to-Master Master waits (1-Wire idle high)

VPUP

VTH

VTLVHY

0V



Package InformationFor the latest package outline information and land patterns(footprints),gotowww.maximintegrated.com/packages.Notethata“+”,“#”,or“-”inthepackagecodeindicatesRoHSstatusonly.Packagedrawingsmayshowadifferentsuffixcharacter,butthedrawingpertainstothepackageregardlessofRoHSstatus.

Ordering Information

1-Wire Communication Examples (continued)

+Denotes a lead(Pb)-free/RoHS-compliant package.T = Tape and reel.

PART TEMP RANGE PIN-PACKAGEDS28E05X+T -40ºCto+85ºC 4UCSP(2.5kpcs)DS28E05R+T -40ºCto+85ºC 3SOT23(3kpcs) DS28E05P+T -40ºCto+85ºC 6TSOC(4kpcs)DS28E05P+ -40ºCto+85ºC 6TSOCDS28E05GB+T -40ºCto+85ºC 2SFN

PACKAGE TYPE

PACKAGE CODE

OUTLINE NO.

LAND PATTERN NO.

4UCSP Z40B0+1 21-100035Refer to

Application Note 1891

3SOT23 U3+2 21-0051 90-01796TSOC D6+1 21-0382 90-0321

2SFN S23A5N+1 21-0661Refer to

Application Note 4132

Wait tPROGRST WM PB FFh

FFh

Write Memory

Writing within a page, not reaching the end of the page.

PD Select DataData

DataData

FFh

FFh

00h

DataData

Release

Repeat

CS = AAh RST

RST RM

Read Memory

Starting at address 33h, reading 6 bytes

PD Select

RST

FF Loop

FF Loop

FF Loop

Wait tPROGRST WM PB

Writing through the end of the page.

PD Select Release

Repeat

CS = AAh

Wait tPROGRST WM PB

Writing fails with protection error

PD Select Release CS = 33h

RST WM

Invalid parameter byte

PD Select PB = 7Eh

FF LoopRST RM

Invalid parameter byte

PD Select PB = 80h

RST<6 bytes>

00h

00h

<10 bytes>RST RM

Starting at the manufacturer ID, reading beyond the end of memory

PD Select PB = 76h

PB = 33h

http://pdfserv.maximintegrated.com/package_dwgs/21-100035.PDF

https://www.maximintegrated.com/en/app-notes/index.mvp/id/1891

https://www.maximintegrated.com/en/app-notes/index.mvp/id/1891


http://pdfserv.maximintegrated.com/land_patterns/90-0179.PDF


http://pdfserv.maximintegrated.com/land_patterns/90-0321.PDF


http://www.maximintegrated.com/en/app-notes/index.mvp/id/4132

http://www.maximintegrated.com/en/app-notes/index.mvp/id/4132

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.


© 2017 MaximIntegratedProducts,Inc. 17

Revision HistoryREVISIONNUMBER

REVISIONDATE DESCRIPTION PAGES

CHANGED0 12/12 Initial release —1 1/14 ExpandedVPUP(min)to2.75VandVIL(max)to0.5V 1,2

2 1/17 AddedSFNpackage,updatedFeatures, Electrical Characteristicstable,Pin Configurations,Pin Descriptions,Ordering Information,andPackage Information 1–16

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

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DS28E05 1- Wire EEPROM - Maxim Integrated · DS28E05 1-Wire EEPROM ... Memory pages can be individually set to write protected or EPROM emulation mode through protection byte settings