DS2153Q E1 Single–Chip Transceiver

�Copyright 1995 by Dallas Semiconductor Corporation.All Rights Reserved. For important information regardingpatents and other intellectual property rights, please refer toDallas Semiconductor data books.

DS2153QE1 Single–Chip Transceiver

DS2153Q

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FEATURES

• Complete E1(CEPT) PCM–30/ISDN–PRI transceiverfunctionality

• Onboard line interface for clock/data recovery andwaveshaping

• 32–bit or 128–bit jitter attenuator

• Generates line build–outs for both 120 ohm and 75ohm lines

• Frames to FAS, CAS, and CRC4 formats

• Dual onboard two–frame elastic store slip buffers thatcan connect to backplanes up to 8.192 MHz

• 8–bit parallel control port that can be used on eithermultiplexed or non–multiplexed buses

• Extracts and inserts CAS signaling

• Detects and generates Remote and AIS alarms

• Programmable output clocks for Fractional E1, H0,and H12 applications

• Fully independent transmit and receive functionality

• Full access to both Si and Sa bits

• Three separate loopbacks for testing

• Large counters for bipolar and code violations, CRC4code word errors, FAS errors, and E bits

• Pin compatible with DS2151Q T1 Single–Chip Trans-ceiver

• 5V supply; low power CMOS

• Industrial grade version (–40°C to +85°C) available(DS2153QN)

PIN ASSIGNMENT

LIN

E IN

TE

RFA

CE

PARALLEL CONTROLPORT

FR

AM

ER

ELA

ST

IC S

TO

RE

S

FUNCTIONAL BLOCKS

7891011121314151617

3938373635343332313029

18 19 20 21 22 23 24 25 26 27 28

6 5 4 3 2 1 44 43 42 41 40

TSERTCLKDVDDTSYNCTLINKTLCLKTCHBLKTRINGTVDDTVSSTTIP

ALEWR

RLINKRLCLKDVSSRCLK

RCHCLKRSER

RSYNCRLOS/LOTC

SYSCLK

RC

HB

LKA

CLK

IB

TS

RT

IPR

RIN

GR

VD

DR

VS

SX

TAL1

XTA

L2IN

T1

INT

2

CS

RD

AD

7A

D6

AD

5A

D4

AD

3A

D2

AD

1A

D0

TC

HC

LK

DALLAS

DS2153Q

E1 SCT

ACTUAL SIZE OF44–PIN PLCC

LON

G &

SH

OR

T H

AU

L

DESCRIPTIONThe DS2153Q T1 Single–Chip Transceiver (SCT) con-tains all of the necessary functions for connection to E1lines. The onboard clock/data recovery circuitry covertsthe AMI/HDB3 E1 waveforms to a NRZ serial stream.

The DS2153 automatically adjusts to E1 22 AWG (0.6mm) twisted–pair cables from 0 to 1.5 KM. The devicecan generate the necessary G.703 waveshapes forboth 75 ohm and 120 ohm cables. The onboard jitter

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attenuator (selectable to either 32 bits or 128 bits) canbe placed in either the transmit or receive data paths.The framer locates the frame and multiframe bound-aries and monitors the data stream for alarms. It is alsoused for extracting and inserting signaling data, Si, andSa–bit information. The device contains a set of 718–bit internal registers which the user can access andcontrol the operation of the unit. Quick access via theparallel control port allows a single micro to handlemany E1 lines. The device fully meets all of the latest E1specifications including ITU G.703, G.704, G.706,G.823, and I.431 as well as ETSI 300 011 and 300 233.

TABLE OF CONTENTS1. Introduction2. Parallel Control Port3. Control and Test Registers4. Status and Information Registers5. Error Count Registers6. Sa Data Link Control and Operation7. Signaling Operation8. Transmit Idle Registers9. Clock Blocking Registers10. Elastic Store Operation11. Additional (Sa) and International (Si)

Bit Operation12. Line Interface Control Function13. Timing Diagrams, Synchronization Flowchart,

and Transmit flow Diagram14. DC and AC Characteristics

1.0 INTRODUCTIONThe analog AMI waveform off of the E1 line is trans-former coupled into the RRING and RTIP pins of theDS2153Q. The device recovers clock and data from theanalog signal and passes it through the jitter attenuationmux to the receive side framer where the digital serialstream is analyzed to locate the framing pattern. If

needed, the receive side elastic store can be enabled inorder to absorb the phase and frequency differencesbetween the recovered E1 data stream and an asynch-ronous backplane clock which is provided at theSYSCLK input.

The transmit side of the DS2153Q is totally independentfrom the receive side in both the clock requirements andcharacteristics. The transmit formatter will provide thenecessary data overhead for E1 transmission. Oncethe data stream has been prepared for transmission, it issent via the jitter attenuation mux to the waveshapingand line driver functions. The DS2153Q will drive the E1line from the TTIP and TRING pins via a coupling trans-former.

Reader’s NoteThis data sheet assumes a particular nomenclature ofthe E1 operating environment. There are 32 8–bit time-slots in E1 systems which are numbered 0 to 31. Time-slot 0 is transmitted first and received first. These 32timeslots are also referred to as channels with a num-bering scheme of 1 to 32. Timeslot 0 is identical to chan-nel 1, timeslot 1 is identical to channel 2, and so on.Each timeslot (or channel) is made up of eight bits whichare numbered 1 to 8. Bit number 1 is the MSB and istransmitted first. Bit number 8 is the LSB and is trans-mitted last. Throughout this data sheet, the followingabbreviations will be used:

FAS Frame Alignment SignalCAS Channel Associated SignalingMF MultiframeSi International BitsCRC4 Cyclical Redundancy CheckCCS Common Channel SignalingSa Additional bitsE–bit CRC4 Error bits



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DS2153Q BLOCK DIAGRAM Figure 1–1

RC

LKR

LIN

K

RLC

LKR

CH

BLK

RC

HC

LK

RS

ER

SY

SC

LK

RS

YN

C

TC

LK

TS

ER

TS

YN

C

TC

HC

LK

TC

HB

LK

CS

WR

(R/W

)R

D(D

S)

ALE

(AS

)A

D0

– A

D7

INT

1/IN

T2

RR

ING

RT

IP

TR

ING

TT

IP

AC

LKI

XTA

L1X

TAL2

RLO

S

XTA

L/V

CO

/PLL

Filt

erP

eak

Det

ect

Clo

ck/

Dat

a

Rec

over

y

Line

Driv

ers

Wav

eS

hapi

ng

Par

alle

l Con

trol

Por

t(r

oute

d to

all

bloc

ks)

32.7

68 M

Hz

Rec

eive

Sid

eF

ram

er

Tran

smit

Sid

e F

orm

atte

r

Sa

Bit

Ext

ract

ion

Tim

ing

Con

trol

Ela

stic

Sto

re

mux

Loss

of

cloc

k

data

sync

Ela

stic

Sto

re

Tim

ing

Con

trol

Sa

Inse

rtLo

gic

TLI

NK

TLC

LK

BT

S

TC

LK D

etec

t

Local Loopback

Jitter Attenuation Mux(can be placed in either the transmit or receive paths)

Remote Loopback

Framer Loopback

AIS Generation

HDB3 Encode

CRC4 GenerationIdle Code Insertion

Signaling Insertion

Sa Bit Insertion

E Bit InsertionSi Bit Insertion

FAS Word Insertion

HDB3 Decoder

BPV Counter

Synchronizer

Alarm Detection

CRC4 Error Count

E Bit Count

FAS Error Count

Signaling Extraction



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PIN DESCRIPTION Table 1–1

PIN SYMBOL TYPE DESCRIPTION

1234

AD4AD5AD6AD7

I/O Address/Data Bus . A 8–bit multiplexed address/data bus.

5 RD(DS) I Read Input (Data Strobe) .

6 CS I Chip Select . Must be low to read or write the port.

7 ALE(AS) I Address Latch Enable (Address Strobe) . A positive going edge serves todemultiplex the bus.

8 WR(R/W) I Write Input (Read/Write) .

9 RLINK O Receive Link Data . Outputs the full receive data stream including the Sabits. See Section 13 for timing details.

10 RLCLK O Receive Link Clock . 4 KHz to 20 KHz demand clock for the RLINK output;controlled by RCR2. See Section 13 for timing details.

11 DVSS – Digital Signal Ground . 0.0 volts. Should be tied to local ground plane.

12 RCLK O Receive Clock . Recovered 2.048 MHz clock.

13 RCHCLK O Receive Channel Clock . 256 KHz clock which pulses high during the LSBof each channel. Useful for parallel to serial conversion of channel data. SeeSection 13 for timing details.

14 RSER O Receive Serial Data . Received NRZ serial data, updated on rising edgesof RCLK or SYSCLK.

15 RSYNC I/O Receive Sync . An extracted pulse, one RCLK wide, is output at this pin whichidentifies either frame (RCR1.6=0) or multiframe boundaries (RCR1.6=1). Ifthe elastic store is enabled via the RCR2.1, then this pin can be enabled to bean input via RCR1.5 at which a frame boundary pulse is applied. See Section13 for timing details.

16 RLOS/LOTC O Receive Loss of Sync/Loss of Transmit Clock . A dual function output.If TCR2.0=0, will toggle high when the synchronizer is searching for the E1frame and multiframe; if TCR2.0=1, will toggle high if the TCLK pin has nottoggled for 5 µs.

17 SYSCLK I System Clock . 1.544 MHz or 2.048 MHz clock. Only used when the elasticstore functions are enabled via RCR2.1. Should be tied low in applicationsthat do not use the elastic store. If tied high for at least 100 µs, will force alloutput pins (including the parallel port) to 3–state.

18 RCHBLK O Receive Channel Block . A user programmable output that can be forcedhigh or low during any of the 32 E1 channels. Useful for blocking clocks toa serial UART or LAPD controller in applications where not all E1 channelsare used such as Fractional E1, 384K bps service (H0), 1920K bps (H12),or ISDN–PRI. Also useful for locating individual channels in drop–and–insertapplications. See Section 13 for timing details.

19 ACLKI I Alternate Clock Input . Upon a receive carrier loss, the clock applied at thispin (normally 2.048 MHz) will be routed to the RCLK pin. If no clock is routedto this pin, then it should be tied to DVSS.



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PIN DESCRIPTIONTYPESYMBOL

20 BTS I Bus Type Select . Strap high to select Motorola bus timing; strap low toselect Intel bus timing. This pin controls the function of the RD(DS),ALE(AS), and WR(R/W) pins. If BTS=1, then these pins assume the functionlisted in parenthesis ().

2122

RTIPRRING

– Receive Tip and Ring . Analog inputs for clock recovery circuitry; connectsto a 1:1 transformer (see Section 12 for details).

23 RVDD – Receive Analog Positive Supply . 5.0 volts. Should be tied to DVDD andTVDD pins.

24 RVSS – Receive Signal Ground . 0.0 volts. Should be tied to local ground plane.

2526

XTAL1XTAL2

– Crystal Connections . A pullable 8.192 MHz crystal must be applied tothese pins. See Section 12 for crystal specifications.

27 INT1 O Receive Alarm Interrupt 1 . Flags host controller during alarm conditionsdefined in Status Register 1. Active low, open drain output.

28 INT2 O Receive Alarm Interrupt 2 . Flags host controller during conditions definedin Status Register 2. Active low, open drain output.

29 TTIP – Transmit Tip . Analog line driver output; connects to a step–up transformer(see Section 12 for details).

30 TVSS – Transmit Signal Ground . 0.0 volts. Should be tied to local ground plane.

31 TVDD – Transmit Analog Positive Supply . 5.0 volts. Should be tied to DVDD andRVDD pins.

32 TRING – Transmit Ring . Analog line driver outputs; connects to a step–up trans-former (see Section 12 for details).

33 TCHBLK O Transmit Channel Block . A user programmable output that can be forcedhigh or low during any of the 32 E1 channels. Useful for blocking clocks toa serial UART or LAPD controller in applications where not all E1 channelsare used such as Fractional E1, 384K bps service (H0), 1920K bps (H12),or ISDN–PRI. Also useful for locating individual channels in drop–and–insertapplications. See Section 13 for timing details.

34 TLCLK O Transmit Link Clock . 4 KHz to 20 KHz demand clock for the TLINK input;controlled by TCR2. See Section 13 for timing details.

35 TLINK I Transmit Link Data . If enabled, this pin will be sampled on the falling edgeof TCLK to insert the Sa bits See Section 13 for timing details.

36 TSYNC I/O Transmit Sync . A pulse at this pin will establish either frame or multiframeboundaries for the DS2153Q. Via TCR1.1, the DS2153Q can be pro-grammed to output either a frame or multiframe pulse at this pin. See Section13 for timing details.

37 DVDD – Digital Positive Supply . 5.0 volts. Should be tied to RVDD and TVDD pins.

38 TCLK I Transmit Clock . 2.048 MHz primary clock. Needed for proper operation ofthe parallel control port.

39 TSER I Transmit Serial Data . Transmit NRZ serial data, sampled on the falling edgeof TCLK.



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PIN DESCRIPTIONTYPESYMBOL

40 TCHCLK O Transmit Channel Clock . 256 KHz clock which pulses high during the LSBof each channel. Useful for parallel to serial conversion of channel data. SeeSection 13 for timing details.

41424344

AD0AD1AD2AD3

I/O Address/Data Bus . A 8–bit multiplexed address/data bus.

DS2153Q REGISTER MAP

ADDRESS R/W REGISTER NAME ADDRESS R/W REGISTER NAME

00 R BPV or Code Violation Count 1 20 R/W Transmit Align Frame

01 R BPV or Code Violation Count 2 21 R/W Transmit Non–Align Frame

02 R CRC4 Count 1/FAS Error Count1

22 R/W Transmit Channel Blocking 1

03 R CRC4 Error Count 2 23 R/W Transmit Channel Blocking 2

04 R E–Bit Count 1/FAS Error Count2

24 R/W Transmit Channel Blocking 3

05 R E–Bit Count 2 25 R/W Transmit Channel Blocking 4

06 R Status 1 26 R/W Transmit Idle 1

07 R Status 2 27 R/W Transmit Idle 2

08 R/W Receive Information 28 R/W Transmit Idle 3

10 R/W Receive Control 1 29 R/W Transmit Idle 4

11 R/W Receive Control 2 2A R/W Transmit Idle Definition

12 R/W Transmit Control 1 2B R/W Receive Channel Blocking 1

13 R/W Transmit Control 2 2C R/W Receive Channel Blocking 2

14 R/W Common Control 1 2D R/W Receive Channel Blocking 3

15 R/W Test 1 2E R/W Receive Channel Blocking 4

16 R/W Interrupt Mask 1 2F R Receive Align Frame

17 R/W Interrupt Mask 2

18 R/W Line Interface Control

19 R/W Test 2

1A R/W Common Control 2

1B R/W Common Control 3

1E R Synchronizer Status

1F R Receive Non–Align Frame



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ADDRESS REGISTER NAMER/WADDRESSREGISTER NAMER/W

30 R Receive Signaling 1 40 R/W Transmit Signaling 1










3A R Receive Signaling 11 4A R/W Transmit Signaling 11

3B R Receive Signaling 12 4B R/W Transmit Signaling 12

3C R Receive Signaling 13 4C R/W Transmit Signaling 13

3D R Receive Signaling 14 4D R/W Transmit Signaling 14

3E R Receive Signaling 15 4E R/W Transmit Signaling 15

3F R Receive Signaling 16 4F R/W Transmit Signaling 16

Note: the Test Registers 1 and 2 are used only by the factory; these registers must be cleared (set to all zeros) onpower–up initialization to insure proper operation.

2.0 PARALLEL PORTThe DS2153Q is controlled via a mutliplexed bidirec-tional address/data bus by an external microcontrolleror microprocessor. The DS2153Q can operate witheither Intel or Motorola bus timing configurations. If theBTS pin is tied low, Intel timing will be selected; if tiedhigh, Motorola timing will be selected. All Motorola bussignals are listed in parenthesis (). See the timing dia-grams in the AC Electrical Characteristics for moredetails. The mutliplexed bus on the DS2153Q savespins because the address information and data informa-tion share the same signal paths. The addresses arepresented to the pins in the first portion of the bus cycleand data will be transferred on the pins during secondportion of the bus cycle. Addresses must be valid priorto the falling edge of ALE(AS), at which time theDS2153Q latches the address from the AD0 to AD7pins. Valid write data must be present and held stableduring the later portion of the DS WR pulses. In a readcycle, the DS2153Q outputs a byte of data during thelatter portion of the DS or RD pulses. The read cycle is

terminated and the bus returns to a high impedancestate as RD transitions high in Intel timing or as DS tran-sitions low in Motorola timing.

3.0 CONTROL AND TEST REGISTERSThe operation of the DS2153Q is configured via a set ofseven registers. Typically, the control registers are onlyaccessed when the system is first powered up. Oncethe DS2153Q has been initialized, the control registerswill only need to be accessed when there is a change inthe system configuration. There are two Receive Con-trol Register (RCR1 and RCR2), two Transmit ControlRegisters (TCR1 and TCR2), and three Common Con-trol Registers (CCR1, CCR2 and CCR3). Each of theseven registers are described in this section.

The Test Registers at addresses 15 and 19 hex are usedby the factory in testing the DS2153Q. On power–up,the Test Registers should be set to 00 hex in order for theDS2153Q to operate properly.



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RCR1: RECEIVE CONTROL REGISTER 1 (Address=10 Hex)

(MSB) (LSB)

RSMF RSM RSIO – – FRC SYNCE RESYNC

SYMBOL POSITION NAME AND DESCRIPTION

RSMF RCR1.7 RSYNC Multiframe Function . Only used if the RSYNC pin is pro-grammed in the multiframe mode (RCR1.6=1).0=RSYNC outputs CAS multiframe boundaries1=RSYNC outputs CRC4 multiframe boundaries

RSM RCR1.6 RSYNC Mode Select .0=frame mode (see the timing in Section 13)1=multiframe mode (see the timing in Section 13)

RSIO RCR1.5 RSYNC I/O Select .0=RSYNC is an output (depends on RCR1.6) 1=RSYNC is an input (only valid if elastic store enabled) (note: this bit mustbe set to zero when RCR2.1=0)

– RCR1.4 Not Assigned . Should be set to zero when written.


FRC RCR1.2 Frame Resync Criteria .0=resync if FAS received in error 3 consecutive times1=resync if FAS or bit 2 of non–FAS is received in error 3 consecutive times

SYNCE RCR1.1 Sync Enable .0=auto resync enabled1=auto resync disabled

RESYNC RCR1.0 Resync . When toggled from low to high, a resync is initiated. Must becleared and set again for a subsequent resync.

SYNC/RESYNC CRITERIA Table 3–1

FRAME ORMULTIFRAME

LEVELSYNC CRITERIA RESYNC CRITERIA ITU SPEC.

FAS FAS present in frames N and N +2, and FAS not present in frameN + 1.

Three consecutive incorrect FASreceived.

Alternate (RCR1.2=1) the abovecriteria is met or three consecu-tive incorrect bit 2 of non–FASreceived.

G.7064.1.14.1.2

CRC4 Two valid MF alignment wordsfound within 8 ms.

915 or more CRC4 code wordsout of 1000 received in error.

G.7064.24.3.2

CAS Valid MF alignment word foundand previous time slot 16 con-tains code other than all zeros.

Two consecutive MF alignmentwords received in error.

G.7325.2



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RCR2: RECEIVE CONTROL REGISTER 2 (Address=11 Hex)

(MSB) (LSB)

Sa8S Sa7S Sa6S Sa5S Sa4S RSCLKM RESE –


Sa8S RCR2.7 Sa8 Bit Select . Set to one to report the Sa8 bit at the RLINK pin; set to zeroto not report the Sa8 bit.





RSCLKM RCR2.2 Receive Side SYSCLK Mode Select . 0=if SYSCLK is 1.544 MHz 1=if SYSCLK is 2.048 MHz

RESE RCR2.1 Receive Side Elastic Store Enable . 0=elastic store is bypassed 1=elastic store is enabled


TCR1: TRANSMIT CONTROL REGISTER 1 (Address=12 Hex)

(MSB) (LSB)

– TFPT T16S TUA1 TSiS TSA1 TSM TSIO


– TCR1.7 Not Assigned . Should be set to zero when written to.

TFPT TCR1.6 Transmit Timeslot 0 Pass Through . 0=FAS bits/Sa bits/Remote Alarm sourced internally from the TAF andTNAF registers 1=FAS bits/Sa bits/Remote Alarm sourced from TSER

T16S TCR1.5 Transmit Timeslot 16 Data Select . 0=sample timeslot 16 at TSER pin 1=source timeslot 16 from TS1 to TS16 registers

TUA1 TCR1.4 Transmit Unframed All Ones .0=transmit data normally 1=transmit an unframed all one’s code at TPOS and TNEG

TSiS TCR1.3 Transmit International Bit Select . 0=sample Si bits at TSER pin 1=source Si bits from TAF and TNAF registers (in this mode, TCR1.6 mustbe set to 0)



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TSA1 TCR1.2 Transmit Signaling All Ones . 0=normal operation 1=force timeslot 16 in every frame to all ones

TSM TCR1.1 TSYNC Mode Select . 0=frame mode (see the timing in Section 13) 1=CAS and CRC4 multiframe mode (see the timing in Section 13)

TSIO TCR1.0 TSYNC I/O Select . 0=TSYNC is an input 1=TSYNC is an output

Note: See Figure 13–9 for more details about how the Transmit Control Registers affect the operation of theDS2153Q.

TCR2: TRANSMIT CONTROL REGISTER 2 (Address=13 Hex)

(MSB) (LSB)

Sa8S Sa7S Sa6S Sa5S Sa4S – AEBE P16F


Sa8S TCR2.7 Sa8 Bit Select . Set to one to source the Sa8 bit from the TLINK pin; set tozero to not source the Sa8 bit.





– TCR2.2 Not Assigned . Should be set to zero when written.

AEBE TCR2.1 Automatic E–Bit Enable . 0=E–bits not automatically set in the transmit direction 1=E–bits automatically set in the transmit direction

P16F TCR2.0 Function of Pin 16 . 0=Receive Loss of Sync (RLOS)1=Loss of Transmit Clock (LOTC)

CCR1: COMMON CONTROL REGISTER 1 (Address=14 Hex)

(MSB) (LSB)

FLB THDB3 TG802 TCRC4 RSM RHDB3 RG802 RCRC4


FLB CCR1.7 Framer Loopback . 0=loopback disabled 1=loopback enabled



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THDB3 CCR1.6 Transmit HDB3 Enable . 0=HDB3 disabled 1=HDB3 enabled

TG802 CCR1.5 Transmit G.802 Enable . See Section 13 for details. 0=do not force TCHBLK high during bit 1 of timeslot 26 1=force TCHBLK high during bit 1 of timeslot 26

TCRC4 CCR1.4 Transmit CRC4 Enable . 0=CRC4 disabled 1=CRC4 enabled

RSM CCR1.3 Receive Signaling Mode Select . 0=CAS signaling mode 1=CCS signaling mode

RHDB3 CCR1.2 Receive HDB3 Enable . 0=HDB3 disabled 1=HDB3 enabled

RG802 CCR1.1 Receive G.802 Enable . See Section 13 for details. 0=do not force RCHBLK high during bit 1 of timeslot 26 1=force RCHBLK high during bit 1 of timeslot 26

RCRC4 CCR1.0 Receive CRC4 Enable . 0=CRC4 disabled 1=CRC4 enabled

FRAMER LOOPBACKWhen CCR1.7 is set to a one, the DS2153Q will enter aFramer LoopBack (FLB) mode. This loopback is usefulin testing and debugging applications. In FLB, theDS2153Q will loop data from the transmit side back tothe receive side. When FLB is enabled, the followingwill occur:

1. data will be transmitted as normal at TTIP andTRING

2. data off the E1 line at RTIP and RRING will beignored

3. the RCLK output will be replaced with the TCLKinput.

CCR2: COMMON CONTROL REGISTER 2 (Address=1A Hex)

(MSB) (LSB)

ECUS VCRFS AAIS ARA RSERC LOTCMC RLB LLB


ECUS CCR2.7 Error Counter Update Select . 0=update error counters once a second 1=update error counters every 62.5 ms (500 frames)

VCRFS CCR2.6 VCR Function Select . 0=count BiPolar Violations (BPVs) 1=count Code Violations (CVs)

AAIS CCR2.5 Automatic AIS Generation . 0=disabled 1=enabled

ARA CCR2.4 Automatic Remote Alarm Generation . 0=disabled 1=enabled



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RSERC CCR2.3 RSER Control . 0=allow RSER to output data as received under all conditions 1=force RSER to one under loss of frame alignment conditions

LOTCMC CCR2.2 Loss of Transmit Clock Mux Control . Determines whether the transmitside formatter should switch to the ever present RCLK if the TCLK shouldfail to transition (see Figure 1.1). 0=do not switch to RCLK if TCLK stops 1=switch to RCLK if TCLK stops

RLB CCR2.1 Remote Loopback . 0=loopback disabled 1=loopback enabled

LLB CCR2.0 Local Loopback . 0=loopback disabled 1=loopback enabled

REMOTE LOOPBACKWhen CCR2.1 is set to a one, the DS2153Q will beforced into Remote LoopBack (RLB). In this loopback,data recovered off of the E1 line from the RTIP andRRING pins will be transmitted back onto the E1 line(with any BPV’s that might have occurred intact) via theTTIP and TRING pins. Data will continue to passthrough the receive side of the DS2153Q as it wouldnormally and the data at the TSER pin will be ignored.Data in this loopback will pass through the jitter attenua-tor. Please see Figure 1.1 for more details.

LOCAL LOOPBACKWhen CCR2.0 is set to a one, the DS2153Q will beforced into Local LoopBack (LLB). In this loopback,data will continue to be transmitted as normal through

the transmit side of the SCT. Data being received atRTIP and RRING will be replaced with the data beingtransmitted. Data in this loopback will pass through thejitter attenuator. Please see Figure 1.1 for more details.

AUTOMATIC ALARM GENERATIONWhen either CCR2.4 or CCR2.5 is set to one, theDS2153Q monitors the receive side to determine if anyof the following conditions are present: loss of receiveframe synchronization, AIS alarm (all ones) reception,or loss of receive carrier (or signal). If any one (or more)of the above conditions is present, then the DS2151Qwill either force an AIS alarm (if CCR2.5=1) or a RemoteAlarm (CCR2.4=1) to be transmitted via the TTIP andTRING pins. It is an illegal state to have both CCR2.4and CCR2.5 set to one at the same time.

CCR3: COMMON CONTROL REGISTER 3 (Address=1B Hex)

(MSB) (LSB)

TESE TCBFS TIRFS ESR LIRST – TSCLKM –


TESE CCR3.7 Transmit Elastic Store Enable.0 = elastic store is disabled1 = elastic store is enabled

TCBFS CCR3.6 Transmit Channel Blocking Registers (TCBR) Function Select . 0=TCBRs define the operation of the TCHBLK output pin 1=TCBRs define which signaling bits are to be inserted

TIRFS CCR3.5 Transmit Idle Registers (TIR) Function Select . 0=TIRs define in which channels to insert idle code 1=TIRs define in which channels to insert data from RSER

ESR CCR3.4 Elastic Stores Reset . Setting this bit from a one to a zero will force theelastic stores to a known depth. Should be toggled after SYSCLK has been



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applied and is stable. Must be set and cleared again for a subsequentreset. Do not leave this bit set high.

LIRST CCR3.3 Line Interface Reset . Setting this bit from a zero to a one will initiate aninternal reset that affects the slicer, AGC, clock recovery state machine,and jitter attenuator. Normally this bit is only toggled on power–up. Must becleared and set again for a subsequent reset.

– CCR3.2 Not Assigned . Should be set to zero when written.

TSCLKM CCR3.1 Transmit Backplane Clock Select. Must be set like RCR2.2.0 = 1.544 MHz1 = 2.048 MHz

– CCR3.0 Not Assigned . Should be set to zero when written.

POWER–UP SEQUENCEOn power–up, after the supplies are stable, theDS2153Q should be configured for operation by writingto all of the internal registers (this includes the Test Reg-isters) since the contents of the internal registers cannotbe predicted on power–up. Next, the LIRST bit shouldbe toggled from zero to one to reset the line interface cir-cuitry (it will take the DS2153Q about 40 ms to recoverfrom the LIRST bit being toggled). Finally, after the SY-SCLK input is stable, the ESR bit should be toggled froma zero to a one and back to zero (this step can beskipped if the elastic store is not being used).

4.0 STATUS AND INFORMATIONREGISTERSThere is a set of four registers that contain informationon the current real time status of the DS2153Q, StatusRegister 1 (SR1), Status Register 2 (SR2), ReceiveInformation Register (RIR), and Synchronizer StatusRegister (SSR). When a particular event has occurred(or is occurring), the appropriate bit in one of these fourregisters will be set to a one. All of the bits in these regis-ters operate in a latched fashion (except for the SSR).This means that if an event occurs and a bit is set to aone in any of the registers, it will remain set until the userreads that bit. The bit will be cleared when it is read andit will not be set again until the event has occurred againor if the alarm is still present.

The user will always precede a read of the SR1, SR2,and RIR registers with a write. The byte written to theregister will inform the DS2153Q which bits the userwishes to read and have cleared. The user will write a

byte to one of these three registers, with a one in the bitpositions he or she wishes to read and a zero in the bitpositions he or she does not wish to obtain the latestinformation on. When a one is written to a bit location,the read register will be updated with current value and itwill be cleared. When a zero is written to a bit position,the read register will not be updated and the previousvalue will be held. A write to the status and informationregisters will be immediately followed by a read of thesame register. The read result should be logicallyAND’ed with the mask byte that was just written and thisvalue should be written back into the same register toinsure that bit does indeed clear. This second write stepis necessary because the alarms and events in the sta-tus registers occur asynchronously in respect to theiraccess via the parallel port. This write–read–writescheme allows an external microcontroller or micropro-cessor to individually poll certain bits without disturbingthe other bits in the register. This operation is key in con-trolling the DS2153Q with higher–order software lan-guages.

The SSR register operates differently than the otherthree. It is a read only register and it reports the status ofthe synchronizer in real time. This register is not latchedand it is not necessary to precede a read of this registerswith a write.

The SR1 and SR2 registers have the unique ability toinitiate a hardware interrupt via the INT1 and INT2 pinsrespectively. Each of the alarms and events in the SR1and SR2 can be either masked or unmasked from theinterrupt pins via the Interrupt Mask Register 1 (IMR1)and Interrupt Mask Register 2 (IMR2) respectively.



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RIR: RECEIVE INFORMATION REGISTER (Address=08 Hex)

(MSB) (LSB)

TESF TESE JALT RESF RESE CRCRC FASRC CASRC


TESF RIR.7 Transmit Elastic Store Full. Set when the elastic store fills and a frame isdeleted.

TESE RIR.6 Transmit Elastic Store Empty. Set when the elastic store empties and aframe is repeated.

JALT RIR.5 Jitter Attenuator Limit Trip . Set when the jitter attenuator FIFO reaches towithin 4–bits of it’s limit; useful for debugging jitter attenuation operation.

RESF RIR.4 Elastic Store Full . Set when the elastic store buffer fills and a frame isdeleted.

RESE RIR.3 Elastic Store Empty . Set when the elastic store buffer empties and aframe is repeated.

CRCRC RIR.2 CRC Resync Criteria Met. Set when 915/1000 code words are received inerror.

FASRC RIR.1 FAS Resync Criteria Met . Set when three consecutive FAS words arereceived in error.

CASRC RIR.0 CAS Resync Criteria Met . Set when two consecutive CAS MF alignmentwords are received in error.

SSR: SYNCHRONIZER STATUS REGISTER (Address=1E Hex)

(MSB) (LSB)

CSC5 CSC4 CSC3 CSC2 CSC0 FASSA CASSA CRC4SA


CSC5 SSR.7 CRC4 Sync Counter Bit 5 . MSB of the 6–bit counter.

CSC4 SSR.6 CRC4 Sync Counter Bit 4 .



CSC0 SSR.3 CRC4 Sync Counter Bit 0 . LSB of the 6–bit counter. The next to LSB bit isnot accessible. This bit will toggle each time the CRC4 MF search times outat 8 ms.

FASSA SSR.2 FAS Sync Active . Set while the synchronizer is searching for alignment atthe FAS level.

CASSA SSR.1 CAS MF Sync Active . Set while the synchronizer is searching for the CASMF alignment word.

CRC4SA SSR.0 CRC4 MF Sync Active . Set while the synchronizer is searching for theCRC4 MF alignment word.



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CRC4 SYNC COUNTERThe CRC4 Sync Counter increments each time the 8 msCRC4 multiframe search times out. The counter iscleared when the DS2153Q has successfully obtainedsynchronization at the CRC4 level. The counter canalso be cleared by disabling the CRC4 mode(CCR1.0=0). This counter is useful for determining the

amount of time the DS2153Q has been searching forsynchronization at the CRC4 level. Annex B of CCITTG.706 suggests that if synchronization at the CRC4level cannot be obtained within 400 ms, then the searchshould be abandoned and proper action taken. TheCRC4 Sync Counter will rollover.

SR1: STATUS REGISTER 1 (Address=06 Hex)

(MSB) (LSB)

RSA1 RDMA RSA0 RSLIP RUA1 RRA RCL RLOS


RSA1 SR1.7 Receive Signaling All Ones . Set when the contents of timeslot 16 con-tains less than three zeros over 16 consecutive frames. This alarm is notdisabled in the CCS signaling mode.

RDMA SR1.6 Receive Distant MF Alarm . Set when bit 6 of timeslot 16 in frame 0 hasbeen set for two consecutive multiframes. This alarm is not disabled in theCCS signaling mode.

RSA0 SR1.5 Receive Signaling All Zeros . Set when over a full MF, timeslot 16 con-tains all zeros.

RSLIP SR1.4 Receive Elastic Store Slip Occurrence . Set when the elastic store haseither repeated or deleted a frame of data.

RUA1 SR1.3 Receive Unframed All Ones . Set when an unframed all ones code isreceived at RTIP and RRING.

RRA SR1.2 Receive Remote Alarm . Set when a remote alarm is received at RTIP andRRING.

RCL SR1.1 Receive Carrier Loss . Set when 255 consecutive zeros have beendetected at RTIP and RRING.

RLOS SR1.0 Receive Loss of Sync . Set when the device is not synchronized to thereceive E1 stream.



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ALARM CRITERIA Table 4–1

ALARM SET CRITERIA CLEAR CRITERIA CCITTSPEC.

RSA1(receive signalingall ones)

over 16 consecutive frames (one fullMF) timeslot 16 contains less than 3zeros

over 16 consecutive frames (one fullMF) timeslot 16 contains 3 or morezeros

G.7324.2

RSA0(receive signalingall zeros)

over 16 consecutive frames (one fullMF) timeslot 16 contains all zeros

over 16 consecutive frames (one fullMF) timeslot 16 contains at least asingle one

G.7325.2

RDMA(receive distantmultiframe alarm)

bit 6 in timeslot 16 of frame 0 set toone for two consecutive MF

bit 6 in timeslot 16 of frame 0 set tozero for a two consecutive MF

O.1622.1.5

RUA1(receive unframedall ones)

less than 3 zeros in two frames (512bits)

more than 2 zeros in two frames (512bits)

O.1621.6.1.2

RRA(receive remotealarm)

bit 3 of non–align frame set to one for3 consecutive occasions

bit 3 of non–align frame set to zero for3 consecutive occasions

O.1622.1.4

RCL(receive carrierloss)

255 consecutive zeros received in 255–bit times, at least 32 ones arereceived

G.775

SR2: STATUS REGISTER 2 (Address=07 Hex)

(MSB) (LSB)

RMF RAF TMF SEC TAF LOTC RCMF TSLIP


RMF SR2.7 Receive CAS Multiframe . Set every 2 ms (regardless if CAS signaling isenabled or not) on receive multiframe boundaries. Used to alert the hostthat signaling data is available.

RAF SR2.6 Receive Align Frame . Set every 250 µs at the beginning of align frames.Used to alert the host that Si and Sa bits are available in the RAF and RNAFregisters.

TMF SR2.5 Transmit Multiframe . Set every 2 ms (regardless if CRC4 is enabled) ontransmit multiframe boundaries. Used to alert the host that signaling dataneeds to be updated.

SEC SR2.4 One Second Timer . Set on increments of one second based on RCLK. IfCCR2.7=1, then this bit will be set every 62.5 ms instead of once a second.

TAF SR2.3 Transmit Align Frame . Set every 250 µs at the beginning of align frames.Used to alert the host that the TAF and TNAF registers need to be updated.

LOTC SR2.2 Loss of Transmit Clock . Set when the TCLK pin has not transitioned forone channel time (or 3.9 µs). Will force pin 16 high if enabled via TCR2.0.Based on RCLK.

RCMF SR2.1 Receive CRC4 Multiframe . Set on CRC4 multiframe boundaries; will con-tinue to be set every 2 ms on an arbitrary boundary if CRC4 is disabled.

TSLIP SR2.0 Transmit Elastic Store Slip. Set when the elastic store has either re-peated or deleted a frame of data.



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IMR1: INTERRUPT MASK REGISTER 1 (Address=16 Hex)

(MSB) (LSB)

RSA1 RDMA RSA0 RSLIP RUA1 RRA RCL RLOS


RSA1 IMR1.7 Receive Signaling All Ones .0=interrupt masked 1=interrupt enabled

RDMA IMR1.6 Receive Distant MF Alarm . 0=interrupt masked 1=interrupt enabled

RSA0 IMR1.5 Receive Signaling All Zeros . 0=interrupt masked 1=interrupt enabled

RSLIP IMR1.4 Receive Elastic Store Slip Occurrence . 0=interrupt masked 1=interrupt enabled

RUA1 IMR1.3 Receive Unframed All Ones . 0=interrupt masked 1=interrupt enabled

RRA IMR1.2 Receive Remote Alarm . 0=interrupt masked 1=interrupt enabled

RCL IMR1.1 Receive Carrier Loss . 0=interrupt masked 1=interrupt enabled

RLOS IMR1.0 Receive Loss of Sync . 0=interrupt masked 1=interrupt enabled



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IMR2: INTERRUPT MASK REGISTER 2 (Address=17 Hex)

(MSB) (LSB)

RMF RAF TMF SEC TAF LOTC RCMF TSLIP


RMF IMR2.7 Receive CAS Multiframe . 0=interrupt masked 1=interrupt enabled

RAF IMR2.6 Receive Align Frame . 0=interrupt masked 1=interrupt enabled

TMF IMR2.5 Transmit Multiframe . 0=interrupt masked 1=interrupt enabled

SEC IMR2.4 One Second Timer . 0=interrupt masked 1=interrupt enabled

TAF IMR2.3 Transmit Align Frame . 0=interrupt masked 1=interrupt enabled

LOTC IMR2.2 Loss Of Transmit Clock . 0=interrupt masked 1=interrupt enabled

RCMF IMR2.1 Receive CRC4 Multiframe . 0=interrupt masked 1=interrupt enabled

TSLIP IMR2.0 Transmit Side Elastic Store Slip.0 = interrupt masked1 = interrupt enabled

5.0 ERROR COUNT REGISTERSThere are a set of four counters in the DS2153Q thatrecord bipolar or code violations, errors in the CRC4SMF code words, E bits as reported by the far end, and word errors in theFAS. Each of these four counters are automaticallyupdated on either one second boundaries (CCR2.7=0)or every 62.5 ms (CCR2.7=1) as determined by thetimer in Status Register 2 (SR2.4). Hence, these regis-ters contain performance data from either the previoussecond or the previous 62.5 ms. The user can use theinterrupt from the timer to determine when to read theseregisters. The user has a full second(or 62.5 ms) to read the counters before the data is lost.

5.1 BPV or Code Violation CounterViolation Count Register 1 (VCR1) is the most signifi-cant word and VCR2 is the least significant word of a

16–bit counter that records either BiPolar Violations(BPVs) or Code Violations (CVs). If CCR2.6=0, then theVCR counts bipolar violations. Bipolar violations aredefined as consecutive marks of the same polarity. Inthis mode, if the HDB3 mode is set for the receive sidevia CCR1.2, then HDB3 code words are not counted asBPVs. If CCR2.6=1, then the VCR counts code viola-tions as defined in CCITT O.161. Code violations aredefined as consecutive bipolar violations of the samepolarity. In most applications, the DS2153Q should beprogrammed to count BPVs when receiving AMI codeand to count CVs when receiving HDB3 code. Thiscounter increments at all times and is not disabled byloss of sync conditions. The counter saturates at 65,535and will not rollover. The bit error rate on a E1 line wouldhave to be greater than 10**–2 before the VCR wouldsaturate.



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VCR1: UPPER BIPOLAR VIOLATION COUNT REGISTER 1 (Address=00 Hex)VCR2: LOWER BIPOLAR VIOLATION COUNT REGISTER 2 (Address=01 Hex) (MSB) (LSB)

V15 V14 V13 V12 V11 V10 V9 V8

V7 V6 V5 V4 V3 V2 V1 V0


V15 VCR1.7 MSB of the 16–bit bipolar or code violation count

V0 VCR2.0 LSB of the 16–bit bipolar or code violation count

5.2 CRC4 Error CounterCRC4 Count Register 1 (CRCCR1) is the most signifi-cant word and CRCCR2 is the least significant word of a10–bit counter that records word errors in the CyclicRedundancy Check 4 (CRC4). Since the maximum

CRC4 count in a one second period is 1000, this countercannot saturate. The counter is disabled during loss ofsync at either the FAS or CRC4 level; it will continue tocount if loss of multiframe sync occurs at the CAS level.

CRCCR1: CRC4 COUNT REGISTER 1 (Address=02 Hex) CRCCR2: CRC4 COUNT REGISTER 2 (Address=03 Hex) (MSB) (LSB)

(note 1) (note 1) (note 1) (note 1) (note 1) (note 1) CRC9 CRC8

CRC7 CRC6 CRC5 CRC4 CRC3 CRC2 CRC1 CRC0


CRC9 CRCCR1.1 MSB of the 10–bit CRC4 error count

CRC0 CRCCR2.0 LSB of the 10–bit CRC4 error count

NOTES:1. The upper six bits of CRCCR1 at address 02 are the most significant bits of the 12–bit FAS error counter.

5.3 E–Bit CounterE–bit Count Register 1 (EBCR1) is the most significantword and EBCR2 is the least significant word of a 10–bitcounter that records Far End Block Errors (FEBE) asreported in the first bit of frames 13 and 15 on E1 linesrunning with CRC4 multiframe. These count registers

will increment once each time the received E–bit is set tozero. Since the maximum E–bit count in a one secondperiod is 1000, this counter cannot saturate. Thecounter is disabled during loss of sync at either the FASor CRC4 level; it will continue to count if loss of multi-frame sync occurs at the CAS level.

VCR1

VCR2

CRCCR1

CRCCR2



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EBCR1: E–BIT COUNT REGISTER 1 (Address=04 Hex) EBCR2: E–BIT COUNT REGISTER 2 (Address=05 Hex) (MSB) (LSB)

(note 1) (note 1) (note 1) (note 1) (note 1) (note 1) EB9 EB8

EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0


EB9 EBCR1.1 MSB of the 10–bit E–Bit count

EB0 EBCR2.0 LSB of the 10–bit E–Bit count

NOTES:1. The upper six bits of EBCR1 at address 04 are the least significant bits of the 12–bit FAS error counter.

5.4 FAS Bit Error CounterFAS Count Register 1 (FASCR1) is the most significantword and FASCR2 is the least significant word of a12–bit counter that records word errors in the FrameAlignment Signal in timeslot 0. This counter is disabled

during loss of frame synchronization conditions, it is notdisabled during loss of synchronization at either theCAS or CRC4 multiframe level. Since the maximumFAS word error count in a one second period is 4000,this counter cannot saturate.

FASCR1: FAS BIT COUNT REGISTER 1 (Address=02 Hex)FASCR2: FAS BIT COUNT REGISTER 2 (Address=04 Hex) (MSB) (LSB)

FAS11 FAS10 FAS9 FAS8 FAS7 FAS6 (note 2) (note 2)

FAS5 FAS4 FAS3 FAS2 FAS1 FAS0 (note 1) (note 1)


FAS11 FASCR1.7 MSB of the 12–bit FAS error count

FAS0 FASCR2.2 LSB of the 12–bit FAS error count

NOTES:1. The lower two bits of FASCR1 at address 02 are the most significant bits of the 10–bit CRC4 error counter.

2. The lower two bits of FASCR2 at address 04 are the most significant bits of the 10–bit E–Bit counter.

6.0 Sa DATA LINK CONTROL ANDOPERATIONThe DS2153Q provides for access to the proposed E1performance monitor data link in the Sa bit positions.The device allows access to the Sa bits either via a set oftwo internal registers (RNAF and TNAF) or via twoexternal pins (RLINK and TLINK).

On the receive side, the Sa bits are always reported inthe internal RNAF register (see Section 11 for more

details). All five Sa bits are always output at the RLINKpin. See Section 13 for detailed timing. Via RCR2, theuser can control the RLCLK pin to pulse during any com-bination of Sa bits. This allows the user to create a clockthat can be used to capture the needed Sa bits.

On the transmit side, the individual Sa bits can be eithersourced from the internal TNAF register (TCR1.6=0) orfrom the external TLINK pin. Via TCR2, the DS2153Qcan be programmed to source any combination of the

EBCR1

EBCR2

FASCR1

FASCR2



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additional bits from the TLINK pin. If the user wishes topass the Sa bits through the DS2153Q without thembeing altered, then the device should be set up to sourceall five Sa bits via the TLINK pin and the TLINK pinshould be tied to the TSER pin. Please see the timingdiagrams and the transmit data flow diagram in Section13 for examples.

7.0 SIGNALING OPERATIONThe Channel Associated Signaling (CAS) bitsembedded in the E1 stream can be extracted from the

receive stream and inserted into the transmit stream bythe DS2153Q. Each of the 30 channels has four signal-ing bits (A/B/C/D) associated with it. The numbers inparenthesis () are the channel associated with a particu-lar signaling bit. The channel numbers have beenassigned as described in the ITU documents. Forexample, channel 1 is associated with timeslot 1 andchannel 30 is associated with timeslot 31. There is a setof 16 registers for the receive side (RS1 to RS16) and 16registers on the transmit side (TS1 to TS16). Thesignaling registers are detailed below.

RS1 TO RS16: RECEIVE SIGNALING REGISTERS (Address=30 to 3F Hex) (MSB) (LSB)

0 0 0 0 X Y X X

A(1) B(1) C(1) D(1) A(16) B(16) C(16) D(16)

A(2) B(2) C(2) D(2) A(17) B(17) C(17) D(17)

A(3) B(3) C(3) D(3) A(18) B(18) C(18) D(18)

A(4) B(4) C(4) D(4) A(19) B(19) C(19) D(19)

A(5) B(5) C(5) D(5) A(20) B(20) C(20) D(20)

A(6) B(6) C(6) D(6) A(21) B(21) C(21) D(21)

A(7) B(7) C(7) D(7) A(22) B(22) C(22) D(22)

A(8) B(8) C(8) D(8) A(23) B(23) C(23) D(23)

A(9) B(9) C(9) D(9) A(24) B(24) C(24) D(24)

A(10) B(10) C(10) D(10) A(25) B(25) C(25) D(25)

A(11) B(11) C(11) D(11) A(26) B(26) C(26) D(26)

A(12) B(12) C(12) D(12) A(27) B(27) C(27) D(27)

A(13) B(13) C(13) D(13) A(28) B(28) C(28) D(28)

A(14) B(14) C(14) D(14) A(29) B(29) C(29) D(29)

A(15) B(15) C(15) D(15) A(30) B(30) C(30) D(30)


X RS1.0/1/3 Spare Bits

Y RS1.2 Remote Alarm Bit (integrated and reported in SR1.6)

A(1) RS2.7 Signaling Bit A for Channel 1

D(30) RS16.0 Signaling Bit D for Channel 30

Each Receive Signaling Register (RS1 to RS16) reportsthe incoming signaling from two timeslots. The bits inthe Receive Signaling Registers are updated on multi-frame boundaries so the user can utilize the Receive

Multiframe Interrupt in the Receive Status Register 2(SR2.7) to know when to retrieve the signaling bits. Theuser has a full 2 ms to retrieve the signaling bits beforethe data is lost. The RS registers are updated under all

RS1 (30)

RS2 (31)

RS3 (32)

RS4 (33)

RS5 (34)

RS6 (35)

RS7 (36)

RS8 (37)

RS9 (38)

RS10 (39)

RS11 (3A)

RS12 (3B)

RS13 (3C)

RS14 (3D)

RS15 (3E)

RS16 (3F)



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conditions. Their validity should be qualified by check-ing for synchronization at the CAS level. In CCS signal-ing mode, RS1 to RS16 can also be used to extractsignaling information. Via the SR2.7 bit, the user will be

informed when the signaling registers have been loadedwith data. The user has 2 ms to retrieve the data beforeit is lost.

TS1 TO TS16: TRANSMIT SIGNALING REGISTERS (Address=40 to 4F Hex) (MSB) (LSB)

0 0 0 0 X Y X X

A(1) B(1) C(1) D(1) A(31) B(16) C(16) D(16)

A(2) B(2) C(2) D(2) A(32) B(17) C(17) D(17)

A(3) B(3) C(3) D(3) A(33) B(18) C(18) D(18)

A(4) B(4) C(4) D(4) A(34) B(19) C(19) D(19)

A(5) B(5) C(5) D(5) A(35) B(20) C(20) D(20)

A(6) B(6) C(6) D(6) A(36) B(21) C(21) D(21)

A(7) B(7) C(7) D(7) A(37) B(22) C(22) D(22)

A(8) B(8) C(8) D(8) A(38) B(23) C(23) D(23)

A(9) B(9) C(9) D(9) A(39) B(24) C(24) D(24)

A(10) B(10) C(10) D(10) A(40) B(25) C(25) D(25)

A(11) B(11) C(11) D(11) A(41) B(26) C(26) D(26)

A(12) B(12) C(12) D(12) A(42) B(27) C(27) D(27)

A(13) B(13) C(13) D(13) A(43) B(28) C(28) D(28)

A(14) B(14) C(14) D(14) A(44) B(29) C(29) D(29)

A(15) B(15) C(15) D(15) A(45) B(30) C(30) D(30)


X TS1.0/1/3 Spare Bits

Y TS1.2 Remote Alarm Bit

A(1) TS2.7 Signaling Bit A for Channel 1

D(30) TS16.0 Signaling Bit D for Channel 30

Each Transmit Signaling Register (TS1 to TS16) con-tains the CAS bits for two timeslots that will be insertedinto the outgoing stream if enabled to do so via TCR1.5.On multiframe boundaries, the DS2153Q will load thevalues present in the Transmit Signaling Register intoan outgoing signaling shift register that is internal to thedevice. The user can utilize the Transmit Multiframe bitin Status Register 2 (SR2.5) to know when to update thesignaling bits. The bit will be set every 2 ms and the userhas 2 ms to update the TSR’s before the old data will beretransmitted.

The TS1 register is special because it contains the CASmultiframe alignment word in its upper nibble. Theupper nibble must always be set to 0000 or else the ter-minal at the far end will lose multiframe synchronization.If the user wishes to transmit a multiframe alarm to thefar end, then the TS1.2 bit should be set to a one. If noalarm is to be transmitted, then the TS1.2 bit should becleared. The three remaining bits in TS1 are the sparebits. If they are not used, they should be set to one. InCCS signaling mode, TS1 to TS16 can also be used toinsert signaling information. Via the SR2.5 bit, the user

TS1 (40)

TS2 (41)

TS3 (42)

TS4 (43)

TS5 (44)

TS6 (45)

TS7 (46)

TS8 (47)

TS9 (48)

TS10 (49)

TS11 (4A)

TS12 (4B)

TS13 (4C)

TS14 (4D)

TS15 (4E)

TS16 (4F)



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will be informed when the signaling registers need to beloaded with data. The user has 2 ms to load the databefore the old data will be retransmitted. Via theCCR3.6 bit, the user has the option to use the TransmitChannel Blocking Registers (TCBRs) to determine on achannel by channel basis, which signaling bits are to beinserted via the TSRs (the corresponding bit in theTCBRs=1) and which are to be sourced from the TSERpin (the corresponding bit in the TCBRs=0). See the

Transmit Data Flow diagram in Section 13 for moredetails.

8.0 TRANSMIT IDLE REGISTERSThere is a set of five registers in the DS2153Q that canbe used to custom tailor the data that is to be transmittedonto the E1 line, on a channel by channel basis. Each ofthe 32 E1 channels can be forced to have a user definedidle code inserted into them.

TIR1/TIR2/TIR3/TIR4: TRANSMIT IDLE REGISTERS (Address=26 to 29 Hex) (MSB) (LSB)

CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1





CH32 TIR4.7 Transmit Idle Registers . 0=do not insert the Idle Code into this channel

CH1 TIR1.0 1=insert the Idle Code into this channel

NOTE:If CCR3.5=1, then a zero in the TIRs implies that channel data is to be sourced from TSER and a one implies thatchannel data is to be sourced from the RSER pin.

TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address=2A Hex)

(MSB) (LSB)

TIDR7 TIDR6 TIDR5 TIDR4 TIDR3 TIDR2 TIDR1 TIDR0


TIDR7 TIDR.7 MSB of the Idle Code

TIDR0 TIDR.0 LSB of the Idle Code

Each of the bit positions in the Transmit Idle Registers(TIR1/TIR2/TIR3/TIR4) represent a timeslot in the out-going frame. When these bits are set to a one, the corre-sponding channel will transmit the Idle Code containedin the Transmit Idle Definition Register (TIDR). In theTIDR, the MSB is transmitted first. Via the CCR3.5 bit,the user has the option to use the TIRs to determine on achannel by channel basis, if data from the RSER pinshould be substituted for data from the TSER pin. In this

mode, if the corresponding bit in the TIRs is set to one,then data will be sourced from the RSER pin. If the cor-responding bit in the TIRs is set to zero, then data forthat channel will sourced from the TSER pin. See theTransmit Data Flow diagram in Section 13 for moredetails.

TIR1 (26)

TIR2 (27)

TIR3 (28)

TIR4 (29)



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9.0 CLOCK BLOCKING REGISTERSThe Receive Channel Blocking Registers(RCBR1/RCBR2/RCBR3/RCBR4) and the TransmitChannel Blocking Registers (TCBR1/TCBR2/TCBR3/TCBR4) control the RCHBLK and TCHBLK pinsrespectively. The RCHBLK and TCHCLK pins are userprogrammable outputs that can be forced either high orlow during individual channels. These outputs can beused to block clocks to a USART or LAPD controller inISDN–PRI applications. When the appropriate bits areset to a one, the RCHBLK and TCHCLK pins will be held

high during the entire corresponding channel time. Seethe timing in Section 13 for an example. The TCBRshave alternate mode of use. Via the CCR3.6 bit, theuser has the option to use the TCBRs to determine on achannel by channel basis, which signaling bits are to beinserted via the TSRs (the corresponding bit in theTCBRs=1) and which are to be sourced from the TSERpin (the corresponding bit in the TCBR=0). See theTransmit Data Flow diagram in Section 13 for moredetails.

RCBR1/RCBR2/RCBR3/RCBR4: RECEIVE CHANNEL BLOCKING REGISTERS(Address=2B to 2E Hex) (MSB) (LSB)






CH32 RCBR4.7 Receive Channel Blocking Registers . 0=force the RCHBLK pin to remain low during this channel time

CH1 RCBR1.0 1=force the RCHBLK pin high during this channel time

TCBR1/TCBR2/TCBR3/TCBR4: TRANSMIT CHANNEL BLOCKING REGISTERS (Address=22 to 25 Hex) (MSB) (LSB)






CH32 TCBR4.7 Transmit Channel Blocking Registers . 0=force the TCHBLK pin to remain low during this channel time

CH1 TCBR1.0 1=force the TCHBLK pin high during this channel time

NOTE:If CCR3.6=1, then a zero in the TCBRs implies that signaling data is to be sourced from TSER and a one implies thatsignaling data for that channel is to be sourced from the Transmit Signaling (TS) registers. See definition below.

RCBR1 (2B)

RCBR2 (2C)

RCBR3 (2D)

RCBR4 (2E)

TCBR1 (22)

TCBR2 (23)

TCBR3 (24)

TCBR4 (25)



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TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3.6 = 1 (MSB) (LSB)

CH20 CH4 CH19 CH3 CH18 CH2 CH17* CH1*




* = CH1 and CH17 should be set to one to allow the internal TS1 register to create the CAS Multiframe Alignment Wordand Spare/Remote Alarm bits.

10.0 ELASTIC STORE OPERATIONThe DS2153Q has an onboard two frame (512 bits)elastic store. This elastic store can be enabled viaRCR2.1. If the elastic store is enabled (RCR2.1=1),then the user must provide either a 1.544 MHz(RCR2.2=0) or 2.048 MHz (RCR2.2=1) clock at theSYSCLK pin. If the elastic store is enabled, then theuser has the option of either providing a frame sync atthe RSYNC pin (RCR1.5=1) or having the RSYNC pinprovide a pulse on frame or multiframe boundaries(RCR1.5=0). If the user wishes to obtain pulses at theframe boundary, then RCR1.6 must be set to zero and ifthe user wishes to have pulses occur at the multiframeboundary, then RCR1.6 must be set to one. If the userselects to apply a 1.544 MHz clock to the SYSCLK pin,then every fourth channel will be deleted and the F–bitposition inserted (forced to one). Hence channels 1, 5,9, 13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24,and 28) will be deleted. Also, in 1.544 MHz applications,the RCHBLK output will not be active in channels 25through 32 (or in other words, RCBR4 is not active).See Section 13 for more details. If the 512–bit elasticbuffer either fills or empties, a controlled slip will occur. Ifthe buffer empties, then a full frame of data (256 bits) willbe repeated at RSER and the SR1.4 and RIR.3 bits willbe set to a one. If the buffer fills, then a full frame of datawill be deleted and the SR1.4 and RIR.4 bits will be set toa one.

11.0 ADDITIONAL (Sa) ANDINTERNATIONAL (Si) BIT OPERATIONThe DS2153Q provides for access to both the Addi-tional (Sa) and International (Si) bits. On the receiveside, the RAF and RNAF registers will always report thedata as it received in the Additional and International bitlocations. The RAF and RNAF registers are updatedwith the setting of the Receive Align Frame bit in StatusRegister 2 (SR2.6). The host can use the SR2.6 bit toknow when to read the RAF and RNAF registers. It has250 µs to retrieve the data before it is lost.

On the transmit side, data is sampled from the TAF andTNAF registers with the setting of the Transmit AlignFrame bit in Status Register 2 (SR2.3). The host canuse the SR2.3 bit to know when to update the TAF andTNAF registers. It has 250 µs to update the data or elsethe old data will be retransmitted. Data in the Si bit posi-tion will be overwritten if either the DS2153Q is pro-grammed: (1) to source the Si bits from the TSER pin,(2) in the CRC4 mode, or (3) have automatic E–bit inser-tion enabled. Data in the Sa bit position will be overwrit-ten if any of the TCR2.3 to TCR2.7 bits are set to one.Please see the register descriptions for TCR1 andTCR2 and the Transmit Data Flow diagram in Section13 for more details.

TCBR1

TCBR2

TCBR3

TCBR4



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RAF: RECEIVE ALIGN FRAME REGISTER (Address=2F Hex)

(MSB) (LSB)

Si 0 0 1 1 0 1 1


Si RAF.7 International Bit.

0 RAF.6 Frame Alignment Signal Bit.







RNAF: RECEIVE NON–ALIGN FRAME REGISTER (Address=1F Hex)

(MSB) (LSB)

Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8


Si RNAF.7 International Bit.

1 RNAF.6 Frame Non–Alignment Signal Bit.

A RNAF.5 Remote Alarm.

Sa4 RNAF.4 Additional Bit 4.





TAF: TRANSMIT ALIGN FRAME REGISTER (Address=20 Hex)

(MSB) (LSB)

Si 0 0 1 1 0 1 1


Si TAF.7 International Bit.

0 TAF.6 Frame Alignment Signal Bit.





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TNAF: TRANSMIT NON–ALIGN FRAME REGISTER (Address=21 Hex)

(MSB) (LSB)



Si TNAF.7 International Bit.

1 TNAF.6 Frame Non–Alignment Signal Bit.

A TNAF.5 Remote Alarm.

Sa4 TNAF.4 Additional Bit 4.





12.0 LINE INTERFACE FUNCTIONSThe line interface function in the DS2153Q containsthree sections; (1) the receiver which handles clock anddata recovery, (2) the transmitter which waveshapes

and drives the E1 line, and (3) the jitter attenuator. Eachof the these three sections is controlled by the Line Inter-face Control Register (LICR) which is described below.

LICR: LINE INTERFACE CONTROL REGISTER (Address=18 Hex) (MSB) (LSB)

L2 L1 L0 EGL JAS JABDS DJA TPD


LB2 LICR.7 Line Build Out Bit 2 . Transmit waveshape setting; see Table 12.2.



EGL LICR.4 Receive Equalizer Gain Limit . 0 = –12 dB1 = –30 dB

JAS LICR.3 Jitter Attenuator Select . 0=place the jitter attenuator on the receive side 1=place the jitter attenuator on the transmit side

JABDS LICR.2 Jitter Attenuator Buffer Depth Select .0=128 bits 1=32 bits (use for delay sensitive applications)

LICR



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DJA LICR.1 Disable Jitter Attenuator . 0=jitter attenuator enabled 1=jitter attenuator disabled

TPD LICR.0 Transmit Power Down . 0=normal transmitter operation 1=powers down the transmitter and 3–states the TTIP and TRING pins

12.1 Receive Clock and Data RecoveryThe DS2153Q contains a digital clock recovery system.See the DS2153Q Block Diagram in Section 1 and Fig-ure 12.1 for more details. The DS2153Q couples to thereceive E1 shielded twisted pair or COAX via a 1:1transformer. See Table 12.3 for transformer details. TheDS2153Q automatically adjusts to the E1 signal beingreceived at the RTIP and RRING pins and can handleE1 twisted pair cables of 0.6 mm (22 AWG) from 0 to 1.5KM in length. The crystal attached at the XTAL1 andXTAL2 pins is multiplied by four via an internal PLL andfed to the clock recovery system. The clock recoverysystem uses both edges of the clock from the PLL circuitto form a 32 times oversampler which is used to recoverthe clock and data. This oversampling technique offersoutstanding jitter tolerance (see Figure 12.2).

Normally, the clock that is output at the RCLK pin is therecovered clock from the E1 AMI/HDB3 waveform pres-

ented at the RTIP and RRING inputs. When no AMI sig-nal is present at RTIP and RRING, a Receive CarrierLoss (RCL) condition will occur and the RCLK can besourced from either the ACLKI pin or from the crystalattached to the XTAL1 and XTAL2 pins. The DS2153Qwill sense the ACLKI pin to determine if a clock is pres-ent. If no clock is applied to the ACLKI pin, then it shouldbe tied to RVSS to prevent the device from falsely sens-ing a clock. See Table 12.1. If the jitter attenuator iseither placed in the transmit path or is disabled, theRCLK output can exhibit short high cycles of the clock.This is due to the highly oversampled digital clock recov-ery circuitry. If the jitter attenuator is placed in thereceive path (as is the case in most applications), the jit-ter attenuator restores the RCLK to being close to 50%duty cycle. Please see the Receive AC Timing Charac-teristics in Section 14 for more details.

SOURCE OF RCLK UPON RCL Table 12–1

ACLKI PRESENT? RECEIVE SIDE JITTERATTENUATOR

TRANSMIT SIDE JITTERATTENUATOR

yes ACLKI via the jitter attenuator ACLKI

no centered crystal TCLK via the jitter attenuator

12.2 Transmit Waveshaping and Line DrivingThe DS2153Q uses a set of laser–trimmed delay linesalong with a precision Digital–to–Analog Converter(DAC) to create the waveforms that are transmitted ontothe E1 line. The waveforms created by the DS2153Qmeet the ITU specifications. See Figure 12.3. The user

will select which waveform is to be generated by prop-erly programming the L2/L1/L0 bits in the Line InterfaceControl Register (LICR). The DS2153Q can set set upin a number of various configurations depending on theapplication. See Table 12.2 and Figure 12.1.



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LINE BUILD OUT SELECT IN LICR Table 12–2

L2 L1 L0 APPLICATION TRANSFORMER RETURN LOSS Rt

0 0 0 75 ohm normal 1:1.15 step–up NM 0 ohms

0 0 1 120 ohm normal 1:1.15 step–up NM 0 ohms

0 1 0 75 ohm normalwith protectionresistors

1:1.15 step–up NM 8.2 ohms

0 1 1 120 ohm normalwith protectionresistors

1:1.15 step–up NM 8.2 ohms

1 0 0 75 ohm with highreturn loss

1:1.15 step–up 21 dB 27 ohms

1 1 0 75 ohm with highreturn loss


1 0 0 120 ohm withhigh return loss


NM=Not Meaningful

Due to the nature of the design of the transmitter in theDS2153Q, very little jitter (less then 0.00 5UIpp broad-band from 10 Hz to 100 KHz) is added to the jitter pres-ent on TCLK. Also, the waveforms that they create areindependent of the duty cycle of TCLK. The transmitterin the DS2153Q couples to the E1 transmit shielded

twisted pair or COAX via a 1:1.15 or 1:1.36 step uptransformer as shown in Figure 12.1. In order for thedevices to create the proper wavefroms, this trans-former used must meet the specifications listed inTable 12.3.

TRANSFORMER SPECIFICATIONS Table 12–3

SPECIFICATION RECOMMENDED VALUE

Turns Ratio 1:1 (receive) and 1:1.15 or 1:1.36 (transmit) ±5%

Primary Inductance 600 µH minimum

Leakage Inductance 1.0 µH maximum

Interwinding Capacitance 60 pF maximum

DC Resistance 1.2 ohms maximum

12.3 Jitter AttenuatorThe DS2153Q contains an onboard jitter attenuator thatcan be set to a depth of either 32 or 128 bits via theJABDS bit in the Line Interface Control Register (LICR).The 128–bit mode is used in applications where largeexcursions of wander are expected. The 32–bit mode isused in delay sensitive applications. The characteris-tics of the attenuation are shown in Figure 12.4. The jit-ter attenuator can be placed in either the receive path orthe transmit path by appropriately setting or clearing theJAS bit in the LICR. Also, the jitter attenuator can be dis-abled (in effect, removed) by setting the DJA bit in the

LICR. In order for the jitter attenuator to operate prop-erly, a crystal with the specifications listed in Table 12.4below must be connected to the XTAL1 and XTAL2 pins.

The jitter attenuator divides the clock provided by the8.192 MHz crystal at the XTAL1 and XTAL2 pins by tocreate an output clock that contains very little jitter.Onboard circuitry will pull the crystal (by switching in orout load capacitance) to keep it long term averaged tothe same frequency as the incoming E1 signal. If theincoming jitter exceeds either 120 UIpp (buffer depth is128–bits) or 28 UIpp (buffer depth is 32–bits), then the



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022697 30/48

DS2153Q will divide the attached crystal by either 3.5 or4.5 instead of the normal 4 to keep the buffer from over-flowing. When the device divides by either 3.5 or 4.5, it

also sets the Jitter Attenuator Limit Trip (JALT) bit in theReceive Information Register (RIR.5).

CRYSTAL SELECTION GUIDELINES Table 12–4

PARAMETER SPECIFICATION

Parallel Resonant Frequency 8.192 MHz

Mode Fundamental

Load Capacitance 18 pF to 20 pF (18.5 pF nominal)

Tolerance ±50 ppm

Pullability CL=10 pF, delta frequency=+175 to +250 ppmCL=45 pF, delta frequency=–175 to –250 ppm

Effective Series Resistance 30 ohms maximum

Crystal Cut AT

DS2153Q EXTERNAL ANALOG CONNECTIONS Figure 12–1+5V

+68 µF0.1 µF

0.1 µF

0.1 µF

8.192 MHz

DVDD

DVSS

RVDD

RVSS

TVDD

TVSS

XTAL1

XTAL2

TTIP

TRING

RTIP

RRING

DS2153Q

0.1 µF

Rr Rr

1.15:1

E1 TRANSMITPAIR

E1 RECEIVELINE

0.47 µF(NON–POLARIZED)

(OR 1.36:1)

1:1

Rt

Rt

0.01 µF

NOTES:1. All resistor values are ±1%.

2. The Rt resistors are used to increase the transmitter return loss or to protect the device from over–voltage.

3. The Rr resistors are used to terminate the receive E1 line.

4. For 75 ohm termination, Rr=37.5 ohms/for 120 ohm termination Rr=60 ohms.

5. See the separate Application Note for details on how to construct a protected interface.



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DS2153Q JITTER TOLERANCE Figure 12–2

MINIMUM TOLERANCELEVEL AS PER

ITU G.823

DS2153QTOLERANCE

10 100 1K 10K 100K1

1K

100

10

1

0.1

1.5

0.2

40

20 2.4K 18K

FREQUENCY (Hz)

UN

IT IN

TE

RV

ALS

(U

lpp)

DS2153Q TRANSMIT WAVEFORM TEMPLATE Figure 12–3

269 ns

G.703TEMPLATE

194 ns

219 ns

–250 –200 –150 –100 –50 0 50 100 150 200 250

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

SC

ALE

D A

MP

LIT

UD

E

(in 7

5 oh

m s

yste

ms,

1.0

on

the

scal

e=2.

37V

peak

in 1

20 o

hm s

yste

ms,

1.0

on

the

scal

e=3.

00V

peak

)

TIME (ns)



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DS2153Q JITTER ATTENUATION Figure 12–4

ITU G.7XXPROHIBITED AREA

1 10 100 1K 10K 100K

FREQUENCY (Hz)

0 dB

–20 dB

–40 dB

–60 dB

JIT

TE

R A

TT

EN

UA

TIO

N (

dB)

13.0 TIMING DIAGRAMS/SYNCHRONIZATION FLOWCHART/TRANSMIT DATA FLOWDIAGRAM

RECEIVE SIDE TIMING Figure 13–1

15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15FRAME# 16 1 2 3 4 5 614

RSYNC1

RSYNC2

RLCLK3

RLINK4

NOTES:1. RSYNC in the frame mode (RCR1.6=0).

2. RSYNC in the multiframe mode (RCR1.6=1).

3. RLCLK is programmed to output just the Sa4 bit.

4. RLINK will always output all five Sa bits as well as the rest of the receive data stream.

5. This diagram assumes the CAS MF begins with the FAS word.



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RECEIVE SIDE BOUNDARY TIMING (WITH ELASTIC STORES DISABLED) Figure 13–2

RCLK

RSER

RSYNC

RCHCLK

RCHBLK1

RLCLK2

RLINK

LSBMSB MSB

CHANNEL 32 CHANNEL 1 CHANNEL 2

RLCLK3

RLCLK4


Sa4 Sa5 Sa6 Sa7 Sa8

NOTES:1. RCHBLK is programmed to block channel 2.

2. RLINK is programmed to output the Sa4 bits.

3. RLINK is programmed to output the SA4 and SA8 bits.

4. RLINK is programmed to output the Sa5 and Sa7 bits.

5. Shown is a non–align frame boundary.



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1.544 MHz BOUNDARY TIMING WITH ELASTIC STORE(S) ENABLED Figure 13–3

SYSCLK

RSER1,

RSYNC2

RSYNC3

RCHCLK

RCHBLK4

CHANNEL 24/32 CHANNEL 1/2CHANNEL 23/31

LSB MSB LSB MSBFTSER

NOTES:1. Data from the E1 channels 1, 5, 9, 13, 17, 21, 25, and 29 is dropped (channel 2 from the E1 link is mapped to

channel 1 of the T1 link, etc.) and the F–bit position is added (forced to one).

2. RSYNC is in the output mode (RCR1.5=0).

3. RSYNC is in the input mode (RCR1.5=1).

4. RCHBLK is programmed to block channel 24.

2.048 MHz BOUNDARY TIMING WITH ELASTIC STORE(S) ENABLED Figure 13–4

SYSCLK

RSER,

RSYNC1

RSYNC2

RCHCLK

RCHBLK3

CHANNEL 32 CHANNEL 1CHANNEL 31

LSB MSB LSBTSER

NOTES:1. RSYNC is in the output mode (RCR1.5=0).


3. RCHBLK is programmed to block channel 1.



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TRANSMIT SIDE TIMING Figure 13–5

15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15FRAME# 16 1 2 3 4 5 614

TSYNC1

TSYNC2

TCLK3

TLINK3

NOTES:1. TSYNC in the frame mode (TCR1.1=0).

2. TSYNC in the multiframe mode (TCR1.1=1).

3. TLINK is programmed to source only the Sa4 bit.

4. This diagram assumbes both the CAS MF and the CRC4 begin with the align frame.



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TRANSMIT SIDE BOUNDARY TIMING Figure 13–6

TCLK

TSER

TSYNC1

TSYNC2

TCHCLK

CHANNEL 2CHANNEL 1

TCHBLK3

TLCLK4

TLINK4 Don’t Care

LSB Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8 MSB MSBLSB

Don’t Care

TLCLK5

TLINK5 Don’t CareDon’t Care

NOTES:1. TSYNC is in the input mode (TCR1.0=0).

2. TSYNC is in the output mode (TCR1.0=1).

3. TCHBLK is programmed to block channel 2.

4. TLINK is programmed to source the Sa4 bits.

5. TLINK is programmed to source the Sa7 and Sa8 bits.

6. Shown is a non–align frame boundary.

7. See Figures 13.3 and 13.4 for details on timing with the transmit side elastic store enabled.



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G.802 TIMING Figure 13–7

TIMESLOT# 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4

RSYNC/TSYNC

RCHCLK/TCHCLK

RCHBLK/TCHBLK1

LSB MSB

TIMESLOT 25 TIMESLOT 26

RCLK/TCLK

RSER/TSER

RCHCLK/TCHCLK

RCHBLK/TCHCLK

DETAIL

NOTE:1. RCHBLK or TCHBLK is programmed to pulse high during timeslots 1 to 15, 17 to 25, and during bit 1 of time-

slot 26.



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DS2153Q SYNCHRONIZATION FLOWCHART Figure 13–8

POWER UP

RLOS=1

FAS SYNC

SYNC DECLARED

CRITERIA METFASSA=0

CAS MULTIFRAMESEARCH (IF ENABLED

VIA CCR1.3)CASSA=1

CAS SYNCCRITERIA MET

CASSA=0RLOS=0

RLOS=1

RESYNC IFRCR1.1=0

INCREMENT CRC4SYNC COUNTER;

CRC4SA=0

8 MSTIMEOUT

CRC4 MULTIFRAMESEARCH (IF ENABLED

VIA CCR.0)CRC4SA=1

CRC4 SYNC CRITERIAMET; CRC4SA=0;

RESET CRC4 SYNCCOUNTER

SET FASRC(RIR.1)

FAS RESYNCCRITERIA MET

CHECK FOR FASFRAMING ERROR

(DEPENDS ONRCR1.2)

CRC4 RESYNCCRITERIA MET

CHECK FOR >=915OUT OF 1000 CRCWORD ERRORS

IF CRC4 IS ON(CCR1.0=1)

CAS RESYNCCRITERIA MET;

SET CASRC(RIR.0)

CHECK FOR CASMF WORD ERROR

IF CAS IS ON(CCR1.3=0)

(RIR.2)



= REGISTER

= DEVICE PIN

= SELECTOR

KEY

TSER TLINK

TS1 TO TS16

AISGENERATION

TRANSMIT SIGNALLINGALL ONES(TCR1.2)

TTIP,TRING

TAF

TNAF

TIMESLOT 0PASS–THROUGH

(TCR1.6)

Si BIT INSERTIONCONTROL(TCR1.3)

Sa BIT INSERTIONCONTROL (TCR2.3

THRU TCR2.7)

IDLE CODE/CHANNEL

SIGNALING BIT

CRC4 ENABLE(CCR1.4)

TRANSMIT UNFRAMEDALL ONES (TCR1.4) OR

AUTO AIS (CCR2.5)

CODE WORDGENERATION

AISGENERATION

0

0

0

0

0

0 1

1

1

1

1

1

1

INSERTION CONTROL

TIDR

TIR FUNCTION SELECT

0 1

RSER(note 1)

(CCR3.5)

INSERTION CONTROLVIA TIR1/2/3/4

TCBR1/2/3/4

TCR1.5

CCR3.6

NOTE:1. TCLK must be tied to RCLK (or SYSCLK if the elastic store is enabled) and

TSYNC must be tied to RSYNC for data to be properly sourced from RSER.

CRC4 MULTIFRAMEALIGNMENT WORD

GENERATION (CCR1.4)

E–BIT GENERATION(TCR2.1)

AUTO REMOTEALARM GENERATION

(CCR2.4)

0

RECEIVE SIDECRC4 ERROR

DETECTOR

0

0

1

1

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DS2153Q TRANSMIT DATA FLOW Figure 13–9



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ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground –1.0V to +7.0VOperating Temperature 0°C to 70°C (–40°C to +85°C for DS2153QN)Storage Temperature –55°C to +125°CSoldering Temperature 260°C for 10 seconds

* This is a stress rating only and functional operation of the device at these or any other conditions above thoseindicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratingconditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATION CONDITIONS (0°C to 70°C)(–40°C to +85°C for DS2153QN)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES

Logic 1 VIH 2.0 VDD +0.3 V

Logic 0 VIL –0.3 +0.8 V

Supply for DS2153Q VDD 4.75 5.25 V 1

Supply for DS2153QN VDD 4.80 5.25 V 1

CAPACITANCE (tA=25°C)


Input Capacitance CIN 5 pF

Output Capacitance COUT 7 pF

DC CHARACTERISTICS (0°C to 70°C; VDD=5V + 5%)(–40°C to +85°C; VDD=5V +5%/–4% for DS2153QN)


Supply Current @ 5V IDD 60 mA 2

Input Leakage IIL –1.0 +1.0 µA 3

Output Leakage ILO 1.0 µA 4

Output Current (2.4V) IOH –1.0 mA

Output Current (0.4V) IOL +4.0 mA

NOTES:1. Applies to RVDD, TVDD, and DVDD.

2. TCLK=2.048 MHz.

3. 0.0V < VIN < VDD.

4. Applies to INT1 and INT2 when 3–stated.



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AC CHARACTERISTICS – PARALLEL PORT (0°C to 70°C; VDD=5V + 5%)(–40°C to +85°C; VDD=5V +5%/–4% for DS2153QN)


Cycle Time tCYC 250 ns

Pulse Width, DS Low or RD High PWEL 150 ns

Pulse Width, DS High or RD Low PWEH 100 ns

Input Rise/Fall Times tR, tF 30 ns

R/W Hold Time tRWH 10 ns

R/W Setup Time Before DS High tRWS 50 ns

CS Setup Time Before DS, WR orRD active

tCS 20 ns

CS Hold Time tCH 0 ns

Read Data Hold Time tDHR 10 50 ns

Write Data Hold Time tDHW 0 ns

Muxed Address Valid to AS orALE fall

tASL 20 ns

Muxed Address Hold Time tAHL 10 ns

Delay Time DS, WR or RD to ASor ALE Rise

tASD 25 ns

Pulse Width AS or ALE High PWASH 40 ns

Delay Time, AS or ALE to DS,WR or RD

tASED 20 ns

Output Data Delay Time from DSor RD

tDDR 20 100 ns

Data Setup Time tDSW 80 ns



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INTEL READ BUS AC TIMING Figure 14–1

ALE

WR

RD

CS

AD0-AD7

tCYC

PWASH

PWEH

tASD

tASED

tASL tDDR

tCH

tDHR

tASD

tCS

tAHL

PWEL

INTEL WRITE BUS AC TIMING Figure 14–2

ALE

WR

RD

CS

AD0-AD7

PWASH

tASD

tASL

tCH

tAHL

tASD tASED

PWEHPWEL

tDSW

tDHW

tCS

tCYC



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MOTOROLA BUS AC TIMING Figure 14–3

AS

DS

R/W

AD0-AD7(READ)

CS

AD0-AD7(WRITE)

PWASH

PWELtCYC

tRWS

tASD

tRWH

tDDR tDHR

tCHtCS

tAHL

tASL

tDHW

tDSW

tAHL

tASL

tASED

PWEH



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AC CHARACTERISTICS – RECEIVE SIDE (0°C to 70°C; VDD=5V ± 5%)(–40°C to +85°C; VDD=5V +5%/–4% for DS2153QN)


ALCKI/RCLK Period tCP 488 ns

RCLK Pulse Width tCHtCL

180180

244244

nsns

1

RCLK Pulse Width tCHtCL

90200

244244

nsns

2

SYSCLK Period tSPtSP

648488

nsns

34

SYSCLK Pulse Width tSHtSL

5050

ns

RSYNC Set Up to SYSCLK Fal-ling

tSU 25 tSH–5 ns

RSYNC Pulse Width tPW 50 ns

SYSCLK Rise/Fall Times tR, tF 25 ns

Delay RCLK or SYSCLK to RSERValid

tDD 70 ns

Delay RCLK or SYSCLK toRCHCLK

tD1 50 ns

Delay RCLK or SYSCLK toRCHBLK

tD2 50 ns

Delay RCLK or SYSCLK toRSYNC

tD3 50 ns

Delay RCLK to RLCLK tD4 50 ns

Delay RCLK to RLINK Valid tD5 50 ns

NOTES:1. Jitter attenuator enabled in the receive side path.

2. Jitter attenuator disabled or enabled in the transmit path.

3. SYSCLK=1.544 MHz.

4. SYSCLK=2.048 MHz.



DS2153Q

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RECEIVE SIDE AC TIMING Figure 14–4

RCLK

RSER

RCHCLK

RCHBLK

RSYNC1

RSYNC2

RLCLK3

RLINK3

tD5

tCL tCH

tCP

tSU

tD4

tPW

tD3

tDD

MSB OF

SYSCLK

tR tFtSL tSH

tSP

CHANNEL 1

tD1

tD2

NOTES:1. RSYNC is in the output mode (RCR1.5=0).


3. RLCLK and RLINK only have a timing relationship to RCLK; no timing relationship between RLCLK/RLINKand RSYNC is implied.

4. RCLK can exhibit a short high time if the jitter attenuator is either disabled or in the transmit path.



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AC CHARACTERISTICS – TRANSMIT SIDE (0°C to 70°C; VDD=5V + 5%)(–40°C to +85°C; VDD=5V +5%/–4% for DS2153QN)


TCLK Period tP 488 ns

TCLK Pulse Width tCHtCL

7575

nsns

TSER, TLINK Set Up to TCLKFalling

tSU 25 ns 1

TSER, TLINK Hold from TCLKFalling

tHD 25 ns 1

TSYNC Setup to TCLK Falling tHD 25 tCH–5 ns

TSYNC Pulse Width tPW 25 ns

TCLK Rise/Fall Times tR, tF 25 ns

Delay TCLK to TCHCLK tD1 50 ns

Delay TCLK to TCHBLK tD2 50 ns

Delay TCLK to TSYNC tD3 50 ns

Delay TCLK to TLCLK tD4 50 ns

NOTES:1. If the transmit side elastic store is enabled,then TSER is sampled on the falling edge of SYSCLK and the

parameters tSU and tHD still apply.



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TRANSMIT SIDE AC TIMING Figure 14–5

TCLK

TSER4

TCHCLK

TCHBLK

TSYNC1

TSYNC2

TLCLK3

TLINK3

tR tF tCL

tPtCH

tSU

tHDtD1

tD2

tD3

tPWtSU

tD4

tHDtSU

MSBLSB

NOTES:1. TSYNC is in the output mode (TCR1.0=1).

2. TSYNC is in the input mode (TCR1.0=0).

3. No timing relationship between TSYNC and TLCLK/TLINK is implied.

4. TSER is sampled on the falling edge of SYSCLK if the transmit side elastic store is enabled.



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DS2153Q E1 SINGLE–CHIP TRANSCEIVER 44–PIN PLCC

C

A1A2

A

B

B1

.075 MAXN1

.150MAX

NOTE 1

D1 D

CH1

E

E1

e1

E2

D2

NOTE1: PIN 1 IDENTIFIER TO BE LOCATED IN ZONE INDICATED.

INCHES

DIM MIN MAX

A 0.165 0.180

A1 0.090 0.120

A2 0.020 –

B 0.026 0.033

B1 0.013 0.021

C 0.009 0.012

CH1 0.042 0.048

D 0.685 0.695

D1 0.650 0.656

D2 0.590 0.630

E 0.685 0.695

E1 0.650 0.656

E2 0.590 0.630

e1 0.050 BSC

N 44 –



Documents

DS2153Q E1 Single–Chip Transceiver