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The Microchip name and logo, the Microchip logo and PIC are registered trademarks and MiWi is a trademark of Microchip Technology Incorporated in the U.S.A. and other countries. All other trademarks are the property of their registered owners. © 2015 Microchip Technology Inc. All rights reserved. 1/15DS00001742B
Adding Connectivityto Your Design
www.microchip.com/connectivity
Microchip offers support for a variety of wired and wireless communication
protocols, including peripheral devices and solutions that are integrated with a
PIC® Microcontroller (MCU).
Wireless connectivity options include: Wi-Fi®, Bluetooth®, 802.15.4/ZigBee® and
our proprietary MiWi™ wireless networking protocol. Other connectivity protocols
supported include USB (device, host, OTG and hubs), Ethernet, CAN, LIN, IrDA®
and RS-485.
All of these protocols are supported with free software libraries, low-cost
development platforms and free samples.
1
FROM THE EDITOR
Embedded Systems Engineering is published by Extension
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ARM, Intel, IP and USBSo much going on! Here’s a snapshot of what’s
crossed my desk in only the last week.
By Chris A. Ciufo, Editor-in-Chief, Embedded Systems Engineering
INTEL AND 6TH GENERATION CORE CPUSFresh on the heels of Intel’s Broadwell (22nm) CPU refresh announcement in June comes
August’s announcement of Skylake. While few material details are available, the 6600K SKU
is the Core i5 and the 6700K SKU is the Core i7. Yet only the “6” at the beginning of the part
number is predictable—the rest of Intel’s nomenclature has gone so far off the rails that even Intel’s trusty
ark.intel.com website isn’t as useful as it once was. (I dare you to figure out Intel’s roadmap from Ark!)
Meaning, for those of us not under NDA, it’s hard to tell the difference between Broadwell, Broadwell-H, and
Skylake (which also has suffixes to which I’m not privy). Broadwell was actually announced in 2014 but Intel
had fab process problems so it was pulled back. Yet Skylake’s schedule continued. The slightly lifted-Skylake
kimono reveals that these 6th-gen Core CPUs are for high-end gaming laptops and PCs, with improved perfor-
mance and a new Z170 Southbridge with loads of peripherals (though strangely not USB 3.1).
It’s interesting that scores of embedded board vendors recently announced Haswell SBCs, and I assume that
when the embedded versions of Skylake are announced (late Fall?) everyone will rush to then announce
Skylake 6th-gen Core boards.
I’m looking forward to the Intel Developers Forum 2015 in just two weeks. (Fun fact: IDF is earlier this year since I presume Intel got tired of Apple’s WWDC upstaging it.)
Perhaps at IDF 2015 I’ll find that one key chart that puts all of this into context. But don’t get me started
on the Atom roadmap: that one’s just as confusing.
ARM’S MBED OS AND SECURITYMeanwhile over in the ARM camp, the company’s IoT strategy is unfolding like an elegant origami swan. Except
I have no idea what that means. Even though last Fall’s announcement of mbed OS was mostly content-free, we
know that ARM is looking to make all things IoT easy and create a cookbook for designers. As ARM’s VP Ian Drew
told me: “even an artist who is not a designer should be able to create something.” mbed OS—and its related mod-
ules like μvisor and security—are designed to work together: from ARM silicon up to the application API.
And ARM is dead serious about IoT security. While I notice that Intel’s McAfee (security tools) building in Santa
Clara now says “Intel Security,” Intel’s security announcements aren’t coming as fast and furious as are ARM’s. In
February, ARM bought IoT security company Offspark with a plan to convert PolarSSL into mbed TLS (Transport
Layer Security). It should be available with mbed OS in August 2015.
And as we went to press, ARM bought Israel’s Sansa Security to “embed security at every potential attack point” in
the connected device chain,” said ARM’s CTO Mike Muller. For the last six months, ARM has been beefing up the
company’s TrustZone IP plus creating security packages for the Cortex-R (real-time) CPUs used in transportation
and control systems. I’m unclear on how Sansa’s chipsets fit with ARM’s lighter-weight IoT end node vision.
USB TYPE-CThe USB-IF’s Type-C either-way connector is all the rage, and you’ll be hearing more about it. I’ve written
several articles on it already, and more vendors are announcing products. Synopsys has new USB Type-C IP for
those designing SoCs; Pericom Semiconductor [one of our sponsors] has rolled out a whole family of switches,
crossbars, and redrivers; and Lattice Semiconductor has announced plans for “SuperMHL” ICs for Type-C.
SuperMHL is an open standard that lets smartphones and tablets drive 8K/120 video to high-res monitors
and projectors. The MHL standard is already on 750 million devices (but not Apple products). The vision, says
Lattice’s Abdullah Raouf, Sr. PMM for Wired Video Solutions, is to use Type-C’s incredible speed and alternate
channels to allow a powerful mobile device to replace the laptop or desktop. Just add a USB 3.0/3.1 keyboard
and mouse, and today’s mobiles easily exceed the corporate laptops people lug to meetings.
20152
IN THIS ISSUE
CONTENTS
Special Features
Software Quality and the Industrial Internet
of Things: Why it Matters NOW
By John Paliotta, Vector Software 3
Advances in Architecture allow ARM Processors to
Tackle Endpoints and Gateways, for the Cloud
By Dave Bursky, Senior Editor 5
USB
Cover Story
Summing Up Circuit Protection for USB 3.0
and USB in Automotive Applications
By VP Pai, ProTek Devices 8
USB Type-C: Doing Away with a
Difference Makes a Difference
By Anne Fisher, Managing Editor 12
Is Glass Losing Its Touch?
By Sri Peruvemba, Cambrios Technologies Corp. 14
Product Showcases
Hardware
Access I/O Products Inc. 16
Teledyne LeCroy 17
Microchip Technology 19
Software
Middleware
HCC Embedded 21
Ethernet
What’s Promising to Widen Ethernet AVB’s Scope?
By Caroline Hayes, Senior Editor 32
Analog High Speed Communication Devices for 40G/100GB
Ethernet Require a Totally New Approach to Test
Cédric Mayor, Chief Technical Officer, Presto Engineering, Inc.,
Caen, France 36
Product Showcases
ICs
Microchip Technology 39
Departments
From the Editor
ARM, Intel, IP and USB
By Chris A. Ciufo, Editor-in-Chief, Embedded; Extension Media 1
PCI Express
Brick by Brick: Q&A with PCI-SIG President and Chairman
Al Yanes and PCI-SIG Board Member Ramin Neshati
By Anne Fisher, Managing Editor 22
RAS Data Protection Considerations for PCI Express Designs
By Richard Solomon, Synopsys 24
GHz Timing Giving You the Jitters? Three
Things You Need to Know
By Chris A. Ciufo, Editor-in-Chief, Embedded; Extension Media 26
Product Showcases
Application Solutions
Access I/O Products Inc. 28
Hardware
General Standards Corporation 29
Teledyne LeCroy 30
3
SPECIAL FEATURE
www.embeddedsystemsengineering.com
Software Quality and the Industrial Internet of Things: Why it Matters NOWWhich manufacturers are on the glide path to realizing increased productivity and more with the IIoT?
By John Paliotta, Vector Software
The International Telecommunication Union defines the
Internet of Things (IoT) as a global infrastructure for the
information society, enabling advanced services by inter-
connecting physical and virtual things based on existing
and evolving interoperable information and communica-
tion technologies. What’s already clear is that in a nutshell,
with every electronic device having network connectivity
(see Figure), every manufacturer of electronic devices will
essentially be in the software business.
THE COMMON THREADThe broader Internet of Things trend generally refers to
consumer applications such as wearables, home automa-
tion, kitchen appliances, etc. There has been a similar
evolution in the industrial sector that embraces these
concepts, known as Industry 4.0, the Fourth Industrial
Revolution, or more simply, the Industrial Internet of
Things (IIoT).
The IIoT is more specific than the IoT, and includes the inte-
gration of complex devices and systems with networked
sensors and software. According to the Industrial Internet
Consortium, “The Industrial Internet is an internet of
things, machines, computers and people, enabling intel-
ligent industrial operations using advanced data analytics
for transformational business outcomes. It embodies the
convergence of the global industrial ecosystem, advanced
computing and manufacturing, pervasive sensing and
ubiquitous network connectivity.”
The ability to connect these types of systems will signifi-
cantly impact business operations. The IIoT can utilize the
power of intelligent technologies to reinvent business
processes and production methods while creating new
revenue streams and transforming the modern workforce.
For example, IIoT technologies are already helping to
increase productivity, reduce operating costs and improve
safety conditions for employees.
Manufacturers are introducing increased automation and
flexible production techniques to improve productivity,
while connected sensor networks monitor logistics to create more efficient
operations and reduce costs. Embedded technology in freight applications
is able to optimize routes to save fuel and reduce delivery costs, or alert
relevant personnel in the event of mechanical breakdowns, saving sub-
stantial resources—and even lives. Unmanned vehicles are being used to
inspect remote pipelines in harsh environments to help keep employees
safe. A common thread throughout all of these applications is that they
are being powered by advanced embedded software technology.
IIOT: DON’T LET ME BE MISUNDERSTOODTo quote the recent “Winning with the Industrial Internet of Things”
report , the Industrial Internet of Things is “arguably the biggest driver
of productivity and growth in the next decade” and it will “accelerate
the reinvention of sectors that account for almost two-thirds of world
output.” The report states that the Industrial Internet of Things has the
potential to add $14.2 trillion to the global economy by 2030.
However, although early adopters are realizing the benefits of the IIoT,
its widespread adoption is hampered by skepticism and lack of under-
standing. According to the same study, “CEOs and executives express
remarkable confidence (96 percent) that the senior leadership in their
organizations grasp at least something of the nature of the IIoT… but
far fewer say their leaders have completely understood it (38 percent).”
A similar study was conducted in collaboration with the World Economic
Forum which surveyed more than 90 market leaders who are actively pur-
suing IIoT initiatives. The vast majority (88 percent) said that they still
Figure 1. Courtesy Vector Software.
20154
SPECIAL FEATURE
do not fully understand the underlying business models and long-term
implications of the IIoT.
IS INDUSTRY PREPARED FOR IOT?With the Internet of Things happening at a broad level, in every industry,
there will be many new vendors providing applications, middleware
and connected devices. Many of these vendors will be new to building
embedded software, engineering robust software, or both. Additionally,
consumers and manufacturers alike will expect the operation of the
connected devices to be seamless and reliable and deliver a positive user
experience in general. Consider how Apple destroyed Nokia and Black-
berry. Was it with better electronic components? Not really—it was with
better software, which provided a better user experience.
Let’s revisit the point earlier that the transformation to an Internet of
Things-enabled environment means that every manufacturer of elec-
tronic devices will essentially be in the software business. Vendors with
a legacy of building mission-critical embedded software for industries
like automotive and industrial controls should have a sizeable advantage
in transitioning to IIoT. They have already solved many of the real-time
embedded challenges for application partitioning, redundancy and long
up-times.
Vendors with no previous software experience, or with experience
building consumer-grade software, are likely to grossly underestimate
the challenges associated with supporting IIoT.
In either case, as more software applications have a requirement for
dependable and uninterrupted operation, vendors will need to imple-
ment processes that can deliver quality software.
SOFTWARE UNDER SCRUTINYAs production environments and business-critical applications continue
to become more dependent on the products whose functionality is con-
trolled by software, the quality of the software has started to come under
scrutiny, particularly in situations where safety, security or human life is
exposed to risk if the software fails.
The biggest challenge that software developers face is balancing testing
completeness with time-to-market. Often the fear is losing the “first
mover advantage” for the sake of testing completeness. However, sacri-
ficing quality for time to market is a dangerous choice that can have a
significant effect on brand value.
In the normal product life cycle for a software application, 1.0 is the initial
release to customers. In subsequent releases, bugs are fixed, and function-
ality that was missing from 1.0 is released. The product typically reaches
a point at which users are happy with the quality and the features of the
product.
The Quality Deficit sits between the first release of the product and when
the market considers the product to be of good quality. Minimizing or
eliminating this Quality Deficit should be high on the priority list of every
organization that is building software.
JOURNEY TO QUALITYTo tackle this challenge involves addressing the second
challenge that development teams face: allocating
development resources between requirements, design,
coding and testing. Historically, the workflow has been
as follows:
Most development teams place the highest priority
placed on coding, with less emphasis on the Applica-
tion Programming Interface (API) and test case design.
Generally, groups will assign senior staff to code devel-
opment and junior staff to testing. However, if this
model were to be completely reversed, then the most
valuable software development products would have a
complete and flexible API, and the test cases prove the
correctness of this API.
If a great API is developed, and tests formalize the cor-
rect behavior to this API, then the actual code writing
can be done by junior staff, the code can be re-factored
with confidence, and quality will be greatly improved.
A final challenge to address on the journey to software
quality is that most groups maintain a variety of test
types, and a different group in the organization “owns”
each type of test. It is very common for the developers
to create and maintain low-level tests, while the
Quality Assurance (QA) department is responsible for
the others.
The QA tests are generally run only after several weeks
of development, when hundreds of source changes have
been integrated into the code base. This makes finding
the root cause of a broken test time consuming and
frustrating. The solution to this challenge is to treat
test cases as a valuable asset of the organization and
leverage them across the entire team and application
life cycle.
CONCLUSIONThere is an increasingly important role for software
quality as the industry adapts to the Industrial Internet
of Things and the fourth industrial revolution. Organi-
zations that do not adjust their development processes
to enable them to produce higher quality applications
are risking not only their brand, but also their very
existence. Organizations that do adapt will thrive.
John Paliotta is co-founder and chief technology officer of
Vector Software.
5
SPECIAL FEATURE
www.embeddedsystemsengineering.com
Advances in Architecture allow ARM Processors to Tackle Endpoints and Gateways, for the Cloud
By Dave Bursky, Senior Editor
T he plethora of devices that connect to the cloud, and even many of
the devices in the cloud, are empowered by embedded processors
that deliver a wide range of performance to execute the desired tasks.
The tasks range from simple endpoints that sense and collect data
such as temperature, vibration, pressure, or other parameters. The
endpoints, in turn, are linked to the next level via wireless or wired
networks. This next level consists of more complex edge devices (gate-
ways) that aggregate and preprocess the data collected from endpoints
to reduce the quantity of data and then feed that data into the cloud,
where it is routed to the appropriate server.
EMBEDDED PROCESSORS PROVIDE INTELLIGENCETo provide the necessary “intelligence’”, higher-performance but low-
power embedded processors are needed in the endpoints. To that end,
ARM has expanded its Cortex-M processor family with the addition of
the Cortex®-M7 processor, which delivers twice the DSP performance
of the previously released Cortex®-M4, but is software compatible.
Based on data from various market research organizations such as
Gartner, International Data Corp., and the Semiconductor Industry
Association, as well as from ARM itself, ARM’s over 200 Cortex-M
series customers have shipped about 4.3 billion Cortex-M series cores
in 2014, and 1.6 billion in Q1 2015. Companies such as Atmel, Freescale
Semiconductor, Marvell, ST Microelectronics, Texas Instruments and
many other vendors have embedded these processor cores into various
microcontrollers or custom application-specific integrated circuits.
The Cortex-M7 will be able to take on higher-end embedded applica-
tions in next-generation connected devices, vehicles, drones, street
lighting, appliances, and many other applications where a full-blown
Linux-based operating system is not required.
Cortex-M7 can run IoT operating systems such as ARM-developed
mbed™ OS that provide secure, reliable communications within the
home or enterprise and out into the cloud. The Cortex-M7 can also run
traditional embedded RTOSes for control applications.
The higher performance point of the Cortex-M7 processor is well
suited to intelligent end-point devices in markets such as industrial,
lighter-weight access points and applications that require real-time
response along with high-performance. Of course, ARM also offers
still higher-performance processor cores in its Cortex A-series
family, but those cores are not as suitable for real-time
applications since they employ memory management
units that limit the core’s ability to provide real-time
deterministic behavior or respond in just a few cycles
to interrupts.
To give the Cortex-M7 the performance and capabilities
needed by the more demanding applications, designers
crafted efficient memory interfaces such as tightly-
coupled memories (TCMs) for real-time response, and
Instruction and Data caches for efficient access to large
memories and powerful peripherals. Additionally,
direct-memory-access (DMA) into the tightly-coupled
memories via the slave version of ARM’s AHB bus, and
the AHBP to access existing AHB peripherals and mem-
ories give the processor the ability to respond quickly
and handle a wide range of I/O requirements (Figure 1).
Figure 1: The ARM® Cortex®-M7 processor core packs improved DSP compute capabilities as well as tightly-coupled memories and a wide array of peripheral support functions that let it deliver double the DSP performance of the M4 as well as higher overall performance. (TCM = tightly coupled memory, FPU = floating-point unit, WIC = wake-up interrupt controller, ETM = embedded trace macrocell, ECC = error checking and correction, MPU = memory protection unit.)
20156
SPECIAL FEATURE
“With the Cortex-M7, functions such as voice recognition, sensor fusion
or performance optimization of control applications can be directly
transferred over to new designs”
Figure 2: The STM32F7-SOM-1A Module from Emcraft Systems provides a designer with a full starter kit for designing applications using the M7 core. In addition to the board, the company has ported a μClinix software package to the platform.
The compatibility of the Cortex-M7 with previous M-series
processors gives the Cortex-M7 a wide range of pre-built
resources that companies can leverage to quickly develop
system-on-a-chip solutions for use in endpoints, home
gateways, edge devices, data aggregation hardware and
many other applications. Compilers, libraries and even
application code will all benefit with an easy migration from
previous devices. This should shorten development times
and allow SoCs that integrate the new Cortex-M7 core to be
used to generate devices, possibly by the end of 2015.
SOFTWARE COMPATIBILITY SHORTENS DEVELOPMENT TIMESoftware and hardware compatibility with previous Cortex-
M-series processors will allow designers to reuse hours to
months of software development done on the older proces-
sors to directly transfer to the Cortex-M7 core, thus greatly
reducing the time to develop applications. Functions such
as voice recognition, sensor fusion or performance optimi-
zation of control applications can be directly transferred
over to new designs and execute more efficiently. Embedded
designers will find that their time spent finely optimizing
application code on older processors can be directly ported
to new devices built around the enhanced Cortex-M7 core.
Hence the new performance enhancements of the Cortex-
M7 can be utilized with little or no software work.
The CPU core in the Cortex-M7 processor has a six-stage
superscalar pipeline with branch prediction, and the DSP
extensions allow the core to perform single-cycle 16- or
32-bit multiply-accumulate (MAC) operations, single-cycle
dual 16-bit MAC operations, as well as 8/16-bit SIMD
(single-instruction/multiple-data) arithmetic. Also in the
Cortex-M7 is a double-precision floating-point unit that
delivers higher accuracy for applications such as required
by precise positioning in the home or the enterprise and by
GPS.
Inside the Cortex-M7 core, instruction and data buses have
been enlarged to 64 bits vs the 32-bit buses used in previous
M-series processors. That enables multiple instructions
to be fetched in each clock cycle. Additionally, the high
performance 64-bit AXI system bus provides a system
interconnect capability that is new for Cortex-M-class
cores. It’s optimized for throughput by supporting multiple
transactions and queuing of transactions. Attached to the
AXI bus are configurable instruction and data caches that
provide low-latency buffering of information as it is fetched
from slower memories. The resulting architecture enhances
the processor’s ability to work with external memories to
handle large data arrays and programs.
HIGH-PERFORMANCE MICROCONTROLLERS LEVERAGE THE CORTEX-M7 CORESeveral of the early licensees of the Cortex-M7 core include
Atmel, Freescale and STMicroelectronics. These vendors
and others are developing microcontrollers that can tackle
endpoint, gateway and edge applications. For example,
both Atmel and Freescale have crafted full general-
purpose microcontrollers around the Cortex-M7 core
(the SAM70 and Kinetis families, respectively), while
STMicro has developed a chip that integrates most of
the functionality of a home gateway that is an offshoot
of its STM32 F7 series of microcontrollers.
Additionally, other development partners such as
Emcraft Systems have crafted development kits based
on the Cortex-M7. For example, the STM32F7-SOM-
1A Module from Emcraft is based on the STMicro
STM32F746 microcontroller that runs at up to 200
MHz, packs 320 kbytes of RAM and 1 Mbyte of Flash
(Figure 2). In addition to the MCU, the board adds 32
Mbytes of SDRAM, 16 Mbytes of NOR flash, an Eth-
ernet PHY and still other resources.
The microcontrollers in Atmel’s SAM70 series can
operate at frequencies of up to 300 MHz and deliver
over 600 DMIPS of computational throughput. The
architecture allows for lower power consumption, high-
speed data stream handling and the ability to handle
video streams. In the future Atmel expects to migrate
the processor to a 40nm process that will enhance the
performance by about another 30%. The company has
optimized the SAM70 microcontroller family for auto-
motive infotainment and telematics applications by
adding Ethernet AVB and MediaLB support on the chip.
Advanced analog interfaces and timers will also let the
processors handle various motor control and robotics
applications.
7
SPECIAL FEATURE
www.embeddedsystemsengineering.com
Designers at Freescale are also leveraging the improve-
ments in the Cortex-M7—the enhanced pipeline
supports execution of multiple instructions per clock,
improving the throughput of the core. Power modes
such as high-speed run mode and very low-power run
mode dynamically change the power management of
Kinetis devices. High-speed run mode will complete
tasks as quickly as possible, while the very-low-power
run mode can be used to extract more processing from
the Cortex-M7 core at lower CPU speeds.
HIGH SPEED CAN ACTUALLY LOWER POWER CONSUMPTIONThe higher processing performance can be used to per-
form functions in a shorter amount of time. Specifically,
there are two aspects of the processing performance
that will affect end applications–especially those
requiring lower power consumption. First, having
more capabilities per clock cycle will allow a task to be
completed at lower system clock speeds. Digital filters
which previously required 200 MHz to operate can now
be done at 100 MHz. In addition, the computational
improvements will allow designs to take advantage
of low-power run modes as the improvements can be
realized at all CPU speeds. Second, another strategy
for low-power design is completing tasks as quickly
as possible. Along with the processing throughput,
the Cortex-M7 supports higher CPU speeds. So when
using the new core to its fullest capabilities, time spent
in active modes processing can be reduced, which will
allow applications to spend more time in low-power
modes.
With a top clock frequency of 200 MHz, the STM32
F7 microcontrollers take advantage of the six-stage
pipeline and FPU to achieve a throughput of up to 1000
CoreMarks (Figure 3). In addition to the Cortex-M7
core, designers at STMicro included two independent
mechanisms to reach 0-wait-state performance from
both internal and external memories: using the com-
pany’s Adaptive Real-Time (ART Accelerator™) for
internal embedded Flash, and employing the L1 cache
for both execution and data access from internal and
external memories.
Designers of the STM32 F7 optimized the entire
system by integrating multiple new peripheral sup-
port functions around the Cortex-M7 processor core.
Lots of timers, a crypto/hash processor, a true random
number generator, multichannel DACs and ADCs, a
high-throughput AXI and multi-AHB bus matrix, and
many other features are all integrated on the chip (refer
back to Figure 3). One of the more novel features is a large SRAM with
a scattered architecture. The SRAM contains a total of 320 kbytes that
is divided into a 240 kbyte and a 16 kbyte block on the bus matrix,
16 kbytes of instruction TCM RAM and 4 kbytes of backup SRAM.
This scattered approach lets the large SRAM block support large data
buffers and multiple software stacks, while the backup SRAM allows
data retention in the lowest power modes for quick recovery, and the
data and instruction TCM blocks support critical real-time data and
program execution.
The high performance of the Cortex-M7 and its compatibility with
previous generation Cortex-M series processors gives designers a
jumpstart in developing next-generation microcontrollers or SoC solu-
tions. The ability to operate at frequencies of 200 MHz and above will
actually let the processors conserve energy and lower system power
consumption in many of endpoints and lightweight access points.
In the future, the transition to smaller process nodes will further
enhance the performance while lowering the operating power to
deliver leading edge solutions in systems ranging from endpoints
such as sensor nodes and smart wearables to critical monitoring and
maintenance functions for intelligent edge devices and routers.
This article was sponsored by ARM.
Figure 3: The high-level of integration done by STMicro on its STM32 F7 microcontroller provides designers with a highly configurable solution that delivers double the performance of previous-generation M-series processors.
20158
engineers’ guide to USB
Summing Up Circuit Protection for USB 3.0 and USB in Automotive ApplicationsAs automakers continue to build more and more computing functions into cars,
USB will play a big role, whether for data transfer or basic charging.
By VP Pai, ProTek Devices
V ersion 3.0 of the Universal Serial Bus (USB) specification
has been around now since 2008. The technology is now well
established across myriad devices requiring high speed data transfer
rates. One analyst firm estimated some 70 million USB 3.0 devices
shipped in 2011. A further estimate claims this will balloon to more
than three billion global USB 3.0 device shipments by 2018. For
anyone involved in implementing USB designs, there’s a lot riding on
this technology. USB is critical to computing devices that are in turn
also critical to everyday business or personal use. Thus proper circuit
protection against electrical transients that can break such devices
is a must. But, how is it best to implement proper circuit protection
for USB 3.0? Also, in general, USB plays a key role in other big appli-
cations, like automotive. So, what are some of the key considerations
for USB in such an application?
USB 3.0 OVERVIEWFirst, a review of the USB 3.0 specification is in order. USB 3.0
offered a generational leap in performance capabilities over USB 2.0.
It increased data rates by 10 times. It also expanded transmission
lines to three differential pairs (compared to one in the previous 2.0
standard). USB was introduced in 1996 with version 1.0. It provided
1.5Mbit/sec in low-speed (LS) mode and 12Mbit/sec in full-speed
(FS) mode. In 2000 USB 2.0 entered the market. The new high-speed
(HS) mode then boosted transfer speeds up to 480Mbit/sec. It was
downwards compatible to low-speed and full-speed mode.
The USB 2.0 interface is still widely used in consumer electronics.
Billions of devices such as camcorders, digital cameras, digital music
players, game consoles, DVD/Blue-Ray players and TVs use one or all
of these USB standards. It’s also widespread in portable devices such
as smartphones and in networking equipment like DSL/router units.
When the USB 3.0 specification was released it demonstrated full
USB 2.0 functionality (HS, FS, LS). It also showcased the new sepa-
rate ultra-high speed data link, called SuperSpeed. The SuperSpeed
link works with separate differential data lines for download (host
=> device, called TX direction). This is also the case for upload in RX
direction (device => host). The maximum data rate in SuperSpeed
mode is 5Gbit/sec. The combination of USB 2.0 functionality and
the new SuperSpeed mode required new cable construction. This
new construction had to serve three differential coupled signal lines
(TX+/Tx-, RX+/Rx- and D+/D-). The VCC and the GND line complete
the cable set.
USB ENGINEERING DESIGN CONSIDERATIONSElectronics engineers must consider a host of require-
ments when designing-in a USB 3.0 link. For example,
full impedance-matched 90-Ohm differential design for
all PCB lines and interconnection cables is mandatory. In
addition non-differential coupled lines have to be mini-
mized. They have significant impact to eye pattern inner
eye opening. Also, trace-width and trace-separation of the
90-Ohm differential are critical.
The coupled PCB traces should not be too narrow, to avoid
additional loss and to be robust enough for manufacturing.
A trace-width of 0.007” (0.178mm) and a separation of
0.007” (0.178mm) between the differential traces are ideal
for production. Identical delay (trace length) between the
positive and the negative line (including the USB 3.0 cable)
of the differential coupled link (minimizing in pair skew)
is needed. This is important to keep signal integrity high
and to avoid common mode reflection.
FACTORING IN CIRCUIT PROTECTIONA USB 3.0 standard-A connector section can easily and
cost-effectively be designed in combination with appro-
priate electrostatic discharge (ESD) circuit protection
devices. For example, the SuperSpeed TX and RX data pairs
can be protected by a transient voltage suppressor array
(TVS array) that is capable of protecting many data lines,
such as up to four lines. The D+ D- regular USB 2.0 pair can
then be protected by a TVS array designed to protect up to
a couple of data lines. It would be ideal to use a TVS array
Figure 1. TVS Array layout recommendation in USB 3.0+2.0 application
9
engineers’ guide to USB
www.eecatalog.com/usb
The Microchip name and logo and the Microchip logo are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. USB Type-C is a trademark of the USB Implementers Forum. All other trademarks are the property of their registered owners. © 2015 Microchip Technology Inc. All rights reserved. 7/15DS00001982A
www.microchip.com/usb
Microchip’s Smart Hub Controllers are 4-port, SuperSpeed (SS)/Hi-Speed (HS),
Features
engineers’s’ gguide to UUSSB
Built-In IntelligenceSuperSpeed Smart Hubs ExpandingSystem Interfaces Beyond USB
201510
engineers’ guide to USB
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11
engineers’ guide to USB
www.eecatalog.com/usb
that can also protect the VCC BUS. Ultra-low line to ground capacitance is
also necessary. This is ideal for use in any high-speed application.
SMALL FOOTPRINT NEEDSMiniaturization requirements for ESD protection devices has introduced
additional problems. This includes higher clamping and less robustness
compared to larger die geometries. For example, clamping for an 8kV
contact discharge, per IEC 61000-4-2, is a very low ~6 V measured at the
30nSec point.
Ultra high-speed data transmission systems have a severe design obstacle.
Designs must ensure a certain level of signal integrity at a receiver. High
signal integrity is important to achieve a low bit error rate. For example,
for USB 3.0 SuperSpeed a bit error rate of 1E-12 is typical. In a real system,
the signal rise-time/fall-time is limited by the TX and the RX impedance
(90 Ohm differential). And, this is in combination with all parasitic capaci-
tance at TX side and RX side. These parasitic capacitances are inside the
USB 3.0 transceiver, and/or externally on the PCB. External parasitics can
be caused by unmatched PCB lines, the USB 3.0 connector, or other shunt
capacitors. Values of shunt capacitors are to be kept as small as possible.
The low pass frequency response of the USB 3.0 cable has to be taken
into account as well. To compensate the attenuation of high frequency
content, the signal is tuned by a dedicated equalization on the TX and
on the RX side.
USB AND OTHER APPLICATIONS IN AUTOMOTIVEToday’s automobiles rely on more and more electronics systems and the
reliance increases with each new generation. USB has become a go-to data
transfer connection in today’s models. But, USB is just one of many auto-
motive applications requiring advanced circuit protection.
The Automotive Electronics Council (AEC-Q101) provides standards for
automotive circuit protection. This includes: AEC-Q101-001 (electrostatic
discharge [ESD] test – human body model); AEC-Q101-002 (ESD test –
machine model); AEC-Q101-003 (wire bond shear test); AEC-Q101-004
(miscellaneous test methods such as unclamped inductive switching,
dielectric integrity, and destructive physical analysis); and AEC-Q101-
005 (ESD test – capacitive discharge model).
These standards are applied to various automotive systems to provide
proper circuit protection. In the 1970s, automobiles generally had just
the engine control unit (ECU) as the sole electronics device. Today, it is
estimated cars have between 30 and 100 microprocessor devices. They
are used to power various systems that are either important to safety,
convenience or entertainment. They include USB ports, Ethernet ports,
CANBus lines, LINBus, antenna, display interfaces, power systems, fuel
injection management systems, and many more.
201512
engineers’ guide to USB
USB Type-C: Doing Away with a Difference Makes a Difference A connector technology that does away with a source of consumer frustration will
invigorate the industrial, smartphones/tablets, automotive and other markets, too.
By Anne Fisher, Managing Editor
W ith a traditional USB connector, the orientation of the connector
makes a difference. One orientation works. The other doesn’t. Ger-
vais Fong, senior product marketing manager of USB PHY IP at Synopsys,
calls non USB Type-C connectors “three-try connectors.” “First,” Fong
explains, “you plug in your connector, it is not quite aligned correctly, two,
you think you have the orientation wrong and you flip it around, three,
having discovered that flipping it from the way you first had it is clearly
the wrong orientation, you flip it back, and it finally works.”
Fong, along with Ajay Srikrishna, Cypress Semiconductor’s vice presi-
dent of USB Business Unit, and Ganesh Subramaniam, product family
executive for USB Type-C at Cypress, shared insights recently on the USB
Type-C specification.
EECatalog: How is USB Type-C shaking things up?
Gervais Fong, Synopsys: USB Type-C could well become the fastest
adopted USB standard in history. What is really quite amazing is that the
USB Type-C specification was released back in August of last year and in
the short space of seven months, with Apple’s release of a Macbook with
Type-C, one of the most high-profile companies in the consumer space
released a product that supports the new Type–C specification. That
speed of adoption is almost unheard of [for] a brand new standard.
Not only did Apple announce its product with Type-C, but Google
announced its latest Chromebook, Pixel, which also has Type-C on it, and
Nokia announced a tablet with a single Type-C connector for data and
power. And there is a host of third-party smartphones rushing to offer
Type-C as the standardized USB connection.
Ganesh Subramaniam, Cypress Semiconductor: The entire USB
ecosystem is changing because of USB Type-C, not just the semicon-
ductor industry. The marketplace, specifically PC original equipment
manufacturers, has recognized the obvious benefits of Type-C, including
the reversible connector, slim form factor and its ability to do way more
than just USB. There is an ongoing refresh cycle in the ecosystem, and we
are seeing changes faster than we have seen in previous USB standards
updates. Every kind of device, whether it is a smartphone, desktop, laptop
or power adapter, is being refreshed to support this standard. Even
devices that previously did not utilize the USB standard,
like power adapters, are changing.
EECatalog: How are you addressing any design complexity
associated with Type-C?
Fong, Synopsys: Yes, the design complexity at the system
level for Type-C is actually quite high. A single cable con-
nector must be able to handle both data and power and be
reversible, seamless and invisible to the user.
One of the things we do at Synopsys is to serve on the
working groups for standards including USB Type-C, so
we not only help develop these standards, but we also
gather knowledge as we participate in the work groups.
We investigate the best way to implement new standards
like Type-C, and we incorporate that knowledge into the
IP that we provide for the standard.
So, for example, for PHY IP, we use the knowledge gained
from the working groups to design the most area-efficient
implementation for a Type-C PHY. On the controller side,
we look at the features that are required and that designers
ask for to enable an efficient Type-C design.
Ajay Srikrishna, Cypress Semiconductor: Since the
USB Implementers Forum has not frozen the USB Type-C
specification yet, the spec is still evolving. Changes are
coming and we want to make sure our customers are not
subject to long wait times. Cypress’ advantage here is in the
“The USB Type-C specification is truly one connector to rule them all, which speaks directly to the original intent of the USB standard.”
Gervais Fong,
Synopsys
Ganesh Subramaniam,
Cypress Semiconductor
Ajay Srikrishna, Cypress
Semiconductor
13
engineers’ guide to USB
www.eecatalog.com/usb
programmability of our solution. Customers will
not need to wait very long or need to get a brand
new chip altogether. If, for example, the customer
is using a fixed function solution or simple analog
front end instead of a programmable solution, it
becomes imperative that they spin new silicon
each time there is an update.
During a recent USB interoperability event, the
compliance suite was changing the night before
the testing was going to take place. We were able
to flash firmware onto our products and upgrade
our customer solutions, get our product certified
and get our customer certified as well. Had the
programmability not been there, they would have
failed certification and would have had a longer
cycle to achieve compliance.
Fong, Synopsys: We make additional enhance-
ments to our Type-C IP in such a way that how
engineers use our IP—ad the overall design
paradigm—can be implemented in a way that
engineers are already accustomed to for non
Type-C USB designs. Helping designers very easily
adopt new IP for Type-C and to do it effectively
and efficiently is our goal.
And that’s why, for example, we have an IP Proto-
typing Kit for USB 3.1 that will enable designers
to prototype their Type-C system and verify it
is working properly before they ramp up volume
production. Making the designer’s job easier in
turn results in lower cost, less risk, higher quality
and better time to market.
Subramaniam, Cypress: The USB Type-C
specification is truly one connector to rule them
all, which speaks directly to the original intent
of the USB standard. It brings the ability to serve
multiple power profiles from 7.5W to 100W in a
small, reversible connector. At first glance, who
could possibly think that Type-C could utilize
multiple protocols like DisplayPort, HDMI and
Thunderbolt? Handling all these different proto-
cols, requirements and signal integrity across one
small cable and connector is the biggest challenge
designers are currently struggling with. Making
this ecosystem work requires domain experts in
all the areas of data, power and video.
EECatalog: What else should we be aware of and
watching for on the USB Type-C front?
Fong, Synopsys: Traditional chip design before
IP ever came about meant, for example, that
designing a USB interface for a hard disk drive
involved dealing with the specific configurations
needed to do that. Now, as an IP provider, we
need to know how to design [a USB interface] for
a hard disk drive, a smartphone, a laptop, a digital
TV, a WiFi dongle—there is a whole host of more
system-level experience that we, as an IP provider,
must have. Our experience and investment in
supporting USB customers for more than 15 years
gives us a deep and broad reservoir of knowledge.
Srikrishna, Cypress: Speaking from an end user
perspective, things could be greatly simplified if
manufacturers had the same solution in both the
devices you are trying to connect, as well as
the cable, adapter and dongle you are using
to do so. What we are seeing is the market
wanting USB Type-C to quickly replace
many different parts of the communication
ecosystem. Even though the adoption of
Type-C is happening quickly, there will still
be a period of overlap where older devices co-
exist with Type-C. Adapters and dongles are
the key pieces that interface between the new
and the legacy standards, making the transi-
tion easier for consumers.
201514
engineers’ guide to USB
Is Glass Losing Its Touch?Here’s what’s set to shrink the role glass touch screen displays will have—in digital signage,
in automobiles, in games, or in anyplace where screens are bending the old rules.
By Sri Peruvemba, Cambrios Technologies Corp.
Industry analysts across the globe expect the market for trans-
parent conductor film used in touch screens to grow at a rapid pace,
replacing their glass counterparts as well as enabling new applications.
According to industry research firm IDTechEx, worldwide shipments
of touch screen panels are set to take twice as much surface area in 10
years as they did in 2014 (Figure 2).
Helping drive this anticipated growth are greater touch sensitivity,
enhanced luminance, bendable touch screens, wraparound screens
and dramatically lower overall cost. The ability to perform environ-
mentally sustainable manufacturing of silver nanowire-based touch
screens is also a growth factor, which along with those just named
is pushing indium tin oxide (ITO) to the side. Like dial up modems,
manual transmissions and wired LANs, ITO’s limitations don’t work
for ‘what’s next.’
While there seems to be a constant stream of
technical breakthroughs in computing systems,
particularly in processors, memory and faster inter-
faces, revolutionary changes are also occurring in
display and touch technology.
HIGHLY INTEGRATED MCUSNew materials are triggering a wave of innovation
in personal electronics. Driving these changes are
incredibly small, highly integrated and far easier to
program microcontrollers and flexible circuit boards
combined with silver nanowire-based touch screen
technology.
And now touch screen displays no longer have to be
flat. Flat and rigid are out. Curved and flexible are
in. Additionally, most touch screens require high-
quality transparent conductors to provide a rich
user experience. These features are being applied
to products that will make today’s tablet computers
appear as dated as desktops and help push portable
computing into entirely new sectors and price
points. Kiosks, gaming machines, point-of-sale
devices, automobile displays and medical devices
are a few key categories ripe for adoption.
Flexible displays definitely equate to improved ergo-
nomics. Imagine unbreakable phone screens that flex
instead of shattering when dropped. Consider folding
a tablet so it slips into your pocket like a mobile phone.
How about a display that wraps around your wrist, or
a huge public display wrapping around a pillar or the
corner of a building like a huge cloth banner does? We
are driving toward products like these. And they are
creating increasing demand for flexible, bendable and
rollable displays using silver nanowires.
SIGNAGE, GAMING & MORESome digital signage applications require touch func-
tionality. For example, interactive kiosks use touch
Figure 1: Likely products that will take advantage of new touch screen technology include but aren’t limited to, curved, shaped smartphones and flexible tablets as well as wearable smart bracelets and watches. Such products are specifically enabled by flexible device technology.
15
engineers’ guide to USB
www.eecatalog.com/usb
functionality to allow users to navigate the menu while providing
input. Traditional touch technologies did not have the electrical con-
ductivity to provide a good experience. And forget about 10-finger
touch or a sleek design that isn’t hampered by heavy sheets of glass or
other bulky technologies. Silver nanowire-based touch screens leave
all these problems behind.
Hand-held and desk top gaming demands excellent touch func-
tionality paired with thin, light, and aesthetically pleasing designs.
Examples of leading-edge touch-enabled products can be found in
the range of tablets from consumer electronics firm Fuhu, Inc.These
demonstrate what’s now possible with touch-enabled products. The
casino gaming industry is also rapidly adopting new touch technology
to differentiate their products and make them more attractive.
SILVER NANOWIRES: WRISTWATCH TO LARGE DISPLAYSilver nanowires are highly conductive single crystal silver nanowires
suspended in a fluid/ink. These silver nanowires have diameters of
a few tens of nanometers and lengths of a few tens of micrometers,
giving them a high (1000:1) aspect ratio. The ink is a mixture of highly
conductive silver nanowires and other materials to enable the ink to
be coated on all kinds of surfaces particularly plastic film. Using this
ink to cover a screen creates a touch surface that is the most respon-
sive, drawing on silver’s excellent conductivity.
Silver nanowire ink is also particularly transparent, has
very good clarity and very little haze, making it ideal
for displays requiring sharp, crisp images. Also, screen
resistance can be customized to suit the specifications
of individual OEMs and designers, which allows for
variable response times. Touch screens can be used for
devices, such as phones and tablets or big touch screen
TVs or even exterior electronic signage. Perhaps most
interestingly they can also be used in applications
requiring round surfaces or conformity to angles,
giving them a clear edge over conventional material
that cannot bend.
As reported in “MIT Technology Review” and else-
where, silver nanowire inks are being used in all-in-one
computers and monitors made by LG, Lenovo, Dell, HP
and others. The material is also found in mobile phones
and tablets made by NEC in Japan, Karbonn in India
and Huawei in China. Silver nanowires are also being
adopted as the transparent-conductor-of-choice by
leading industry heavyweights including Hitachi, LG,
TPK, Nissha, 3M, Okura, CNI and others.
For emerging touch screen applications, including
large-area signage and monitors, as well as miniature,
flexible, wearable displays, silver nanowires offer sig-
nificant advantages both in cost and performance. The
material is already being used in several consumer elec-
tronics products. Roll-to-roll processed silver nanowire
transparent conductors are the clear choice for new
factories needing high throughput, fewer consumables
and easy processing. They’re also on target for CE OEMs
needing a thin, light, bright, flexible material delivering
high performance for their next killer application.
Sri Peruvemba is vice president at Cambrios Technologies
Corp.
Figure 2: Touch screen growth by surface area. Data courtesy Dr. Khasha Ghaffarzadeh, IDTechEx Research.
201516 Hardware
CONTACT INFORMATION
engineers’ guide to USBBoard
sBoards
ACCES I/O Products, IncRugged, Industrial Strength USB Embedded I/O Solutions
Linux (including Mac OSX) and Windows
ACCES I/O Products offers USB-based data acquisition and con-trol in both standard packaging and embedded OEM USB/104 board only options. These USB DAQ devices are perfect for a variety of applications requiring monitoring, control and indus-trial serial communications. Add the features you need in your application in hours, not days. Choose from over 100 different models and options (including extended temperature) encom-passing analog I/O, digital I/O, counter/timer, and serial I/O configurations.
All of our USB DAQ products feature Plug-and-Play, hot swap-pable installation for quick connect or disconnect in mobile, embedded, or stationary systems. These boards are excellent for easy installation into OEM equipment and eliminate the labor required with traditional plug-in boards. No screws, reboots, I/O addresses, DIP switches, DMA channels or IRQ settings.
Call us today and start your application tomorrow. And remember, if you don’t see what you need, ask us and we will make it for you.
FEATURES & BENEFITS
◆ Multifunction Analog Input/Output USB DAQ Products provide
16 (up to 128) channels of multifunction analog I/O with signal
conditioning, single-ended or differential inputs, real-time
software calibration, and extended temperature.
◆ Analog Output USB DAQ. Select from an assortment of 12 and
16-bit models with 4, 8, or 16 analog outputs, full Arbitrary
Waveform Generator functionality (AWG/ARB), and up to 125K
conversions simultaneously per channel.
◆ Digital Input / Output USB DAQ Products for compact control and
monitoring applications. Choose from 4 to 96 channels offering
various voltage, isolation, speed, and counter/timer options.
◆ Serial Communication USB Products. Simply install the
included software and connect our product to your USB port
and transform it into asynchronous serial ports for commu-
nication with serial instruments. 1, 2, and 4-port models are
available.
◆ Custom USB I/O Products. 23 years of product development,
350 COTS products, over 750 specials and options. If you don’t
see what you need, ask us and we will make it for you.
TECHNICAL SPECS
◆ All USB products are available packaged in a rugged, steel
enclosure with an attractive black powder coat finish, anti-skid
bottom, and a DIN rail mounting provision. This enclosure is
useful in industrial environments.
◆ The OEM USB/104 product line PCB size measures just 90mm
x 96mm and the mounting holes match the PC/104 form factor.
This ensures easy installation using standard standoffs inside
most enclosures or systems.
◆ The USB/PICO line was created for our customers which
demand an even smaller footprint and certain specific I/O
configurations. The size of these modules is exactly half
that of PC/104 (72mm x 60mm) and can be mounted virtually
anywhere.
◆ High Retention USB Connector. A type B USB connector is used
on all ACCES USB products which features a high retention
design that complies with the class 1, Div II minimum with-
drawal requirement of over 3 pounds of force (15 Newtons)
◆ For embedded OEM type applications, an additional micro-fit USB
input header is provided in parallel with the type B connector.
AVAILABILITY
Now
APPLICATION AREAS
Monitoring and Control, Embedded OEM, Energy Management and Conservation, Gaming Systems, Industrial Automation, Kiosks, Machine Control, Manufacturing Test, Medical, POS, Precision Measurement, Process Monitoring, Retail, Robotics, Security, UAVs
ACCES I/O Products, Inc. 10623 Roselle Street San Diego, CA 92121 USA1-800-326-1649 Toll Free858-550-9559 Telephone858-550-7322 [email protected] http://acces.io
17www.eecatalog.com/usb Hardware
engineers’ guide to USB
Voyager™ M310C
◆ – The Voyager features 16GB recording memory plus USB and Gbe links for uploading recorded traffic to the host PC. Use pre-capture filtering to extend capacity further – or use spool-to-disk capture to record bus events for hours or even days.
◆ – Designed from the start to address compliance, a fully automated test suite allows users to verify conformance for USB 3.1 and Power Delivery
◆ – Monitor and display vBus power graphically in a time-line format synchro-nized to state changes and protocol events.
◆ – Analyzer and exerciser can analyze and emulate baseband Power Delivery signals over Type-C connectors
USB 3.1, Type-C, & Power Delivery Protocol Analyzer Exerciser
The Teledyne LeCroy Voyager M310C brings Type-C connectors and Power Delivery 2.0 support to the industry’s leading USB 3.1 validation protocol analyzer family. This multifunction validation platform is available with an integrated exerciser capable of both 2.0, 3.0, and 3.1 host and device emulation. In addition to compliance verification and error injection, the exerciser can emulate a USB endpoint and intelligently respond to enumeration requests. The ability to transmit custom packets with low-level control of headers, payloads, timing, and link states allows users to mimic real devices and test error recovery. Featuring Type-C connectors, the power delivery exerciser can act as source or sink; as well as negotiate valid and invalid power delivery contracts.
The Voyager M310C system leverages Teledyne LeCroy’s T.A.P.3 non-intrusive probing technology to provide 100% accurate protocol capture, fast locking and very low signal loss. The system includes all the cables and adapters to work with the new Type-C or legacy USB devices. With 16GB of recording memory, intelligent triggering, real-time filtering, automatic error detection, the M310C is the all-in-one solution for the next decade of USB test and verification.
FEATURES & BENEFITS◆ – Captured traffic is displayed using the
legendary CATC Trace which has become the indus-try’s de facto standard for USB protocol analysis.
◆ – The Voyager provides fast-locking on the SuperSpeed 10Gbps signal and is the only analyzer that records every symbol for uncompromised visibility to problems on the bus.
◆ – While inline, the analyzer seamlessly monitors low power states while accurately showing all link transitions and power delivery transactions time-stamped within the display.
◆ – Concurrent high-speed and SuperSpeed recording allows end-to-end viewing of data transfers across a USB 3.1 hub.
Teledyne LeCroy700 Chestnut Ridge RdChestnut Ridge, NY, 10977USAtoll-free: 1-800 909-7211 or408 [email protected]. www.teledynelecroy.com
Board
sBoards
CONTACT INFORMATION
201518 Hardware
CONTACT INFORMATION
engineers’ guide to USB
Mercury™ T2C
Teledyne LeCroy700 Chestnut Ridge RdChestnut Ridge, NY, 10977USAtoll-free: 1-800 909-7211 or408 [email protected]. www.teledynelecroy.com
CONTACT INFORMATION
USB Type C and Power Delivery 2.0 Protocol Analyzer
The Mercury T2C is the industry’s smallest and most affordable hardware-based USB protocol analyzer that supports the USB Type-C and Power Delivery 2.0 standards. Designed to allow quick identification of protocol issues, the Mercury T2C is fully compatible with the new Type C connectors and includes all the adapters needed to interface with legacy USB Type A & B devices as well.
U
The Mercury T2C can capture and decode USB Power Delivery 2.0 packets over the Type-C Configuration Channel (CC) in addition to USB 2.0 data packets. Users can view the CC packets including cable detection, power negotiation, role swaps, entrance to / exit from Alternate Modes and other Type-C Power Delivery events.
Featuring the industry-leading CATC Trace™ expert analysis software, the Mercury T2C system provides an easy-to-use display that graphically decodes logical protocol events. With the Standard or Advanced edition, all protocol layers can be expanded to show the underlying transactions and packets. Tooltips help explain protocol events making it easier for non-experts to identify errors.
Isolating specific protocol events with real time triggering is essential to capture intermittent problems. The Mercury T2C provides sophisticated triggering with drag-and-drop selections for PID type, data patterns, standard requests, errors, and all PD bus events. The Mercury features 256MB of on-board memory and also supports spool-to-disk capture for extended recording.
U
Comprehensive USB device class decoding is included in every model of the Mercury T2. This allows users to see upper-level mapped protocol events within the trace eliminating the tedious process of manually decoding device specific commands.
FEATURES◆
Compact, bus powered system measures 3 1/2” x 3.0”◆
Capable of capturing all USB 2.0 speeds including Power Delivery and OTG (On-The-Go)
◆
Extend capture time with spool-to-disk recording◆
Non-intrusive probe preserves real world signal andtiming conditions
◆
Isolates important traffic, specific errors or data patterns
◆
Packet Identifiers, Token Pattern, Frame Pattern, Device Request, Data Pattern, Bus Conditions, Errors, Transactions, Data Length, Splits
◆ Mass Storage, Bluetooth HCI, Hub, PTP/Still Image, Printer, Human Interface Devices (HID), Audio, Video and Communication
◆
Automatically exclude non-essential traffic◆
Quickly identify and track error rates, abnormal bus or timing conditions
COMPATIBLE OPERATING SYSTEMS:
Microsoft Windows 7, 8, & 10
USB Support: USB 1.0, 1.1, 2.0, 3.0, 3.1, OTG & Power Delivery (BMC)
AVAILABILITY:
The Mercury T2C is available in USB 2.0 configurations; the Voyager M310C is available in both USB 3.1 Gen 1 & Gen 2 configurations.
Boards
19www.eecatalog.com/usb Hardware
engineers’ guide to USB
Microchip Technology
TECHNICAL SPECS
◆ USB hub with four downstream ports◆ On-chip microcontroller manages I/Os, VBUS, and
other signals ◆ 8 KB RAM, 64 KB ROM ◆ 8 KB One-Time Programmable (OTP) ROM ◆ Includes on-chip charge pump
◆ Certified USB product, TID 30000058◆ 64-pin (9 x 9 mm) SQFN, RoHS-compliant package◆ A USB5734 Evaluation Board (part # EVB-USB5734,
$399.00)
APPLICATION AREAS
Point-of-sale systems, automotive break-out-box, automotive head unit, LCD monitors and TVs, multi-function USB peripherals, PC motherboards, set-top boxes, DVRs/PVRs, printers and scanners, monitor docking stations, mobile PC docking, industrial embedded systems and medical embedded systems
AVAILABILITY
The USB5734/44 USB 3.1 Gen1 Smart Hub Controller is available now.
USB5734
Windows®, Linux®, QNX®
The Microchip USB5734 hub is a low-power, OEM-configurable, USB 3.1 Gen1 hub feature controller with four downstream ports and advanced features for embedded USB applications. The USB5734 is fully compliant with the USB Revision 3.1 Specification and USB 2.0 Link Power Management Addendum. The USB5734 supports the legacy USB speeds (HS/FS/LS) through a dedicated USB 2.0 hub feature controller. The SuperSpeed “Smart Hub” Controller operates in parallel with the USB 2.0 controller, decoupling the 5 Gbps SS data transfers from bottlenecks due to the slower USB 2.0 traffic. A smart hub is a USB hub that integrates system-level functions typically associated with a separate MCU or processor. Microchip’s USB5734/44 Smart Hubs enable communication to other peripherals in addition to USB. This I/O bridging capability allows the host to seamlessly interface to peripherals via I2C, SPI, GPIOs or a UART over USB. Microchip’s smart hubs also feature FlexConnect, which enables a downstream device to take control of the system by either swapping roles and becoming the host port, or by switching roles and alternating as the host port. The USB5734 also enables system configuration using “configuration straps”, which simplify the process by assigning default values to USB 3.1 Gen1 ports and GPIOs. You can disable ports, enable battery charging and define GPIO functions as default assignments on power up removing the need for OTP or external SPI ROM.
FEATURES & BENEFITS
◆ USB smart hub controller with four USB 3.1 Gen1/USB 2.0 downstream ports
◆ FlexConnect: downstream port able to swap with upstream port, allowing master capable devices to control other devices on the hub
◆ I/O bridging: USB to I2C/UART/SPI/GPIO bridge endpoint support
◆ Configuration straps: predefined configuration of system-level functions including GPIOs
◆ USB-IF battery charger revision 1.2 support on up and downstream ports (DCP, CDP, SDP) Microchip Technology
2355 West Chandler Blvd.ChandlerAZ - Arizona85224United States480-792-7200888-MCU-MCHP480-792-7277here2help@microchip.comwww.microchip.com
CONTACT INFORMATION
Hubs
201520 Hardware
engineers’ guide to USB
Microchip Technology
TECHNICAL SPECS
◆ Certified USB product, TID 30000064◆ USB hub with four downstream ports◆ Flexible power rail support
◆ VBUS or VBAT only operation◆ 3.3V only operation◆ VBAT +1.8V operation ◆ 3.3V +1.8V operation
◆ 48-pin (7 x 7 mm) SQFN, RoHS-compliant package◆ A USB4604 Evaluation Board (part # EVB, USB4604,
$399.99)
APPLICATION AREAS
Point-of-sale systems, automotive break-out-box, automotive head unit, LCD monitors and TVs, multi-function USB peripherals, PC motherboards, set-top boxes, DVRs/PVRs, printers and scanners, monitor docking stations, mobile PC docking, industrial embedded systems and medical embedded systems
AVAILABILITY
The USB4604 Smart Hub is available now.
USB4604
Windows®, Linux®, QNX®
The 4-port USB4604 Smart Hub can attach to an upstream port as a full-speed hub or as a full-/high-speed hub. When connected to a high-speed host, the four downstream-facing ports can operate at low speed (1.5 Mbps), full speed (12 Mbps) or high speed (480 Mbps). Smart hub features add key system functionality for embedded applications, providing you with more features in a single chip. By integrating an on-chip microcontroller, the USB4604 can seamlessly communicate via multiple protocols and methods including I2C, SPI, UART and general-purpose I/O. This enhanced functionality provides added system control and communication as well as USB port expandability of the hub. Microchip’s FlexConnect technology allows for “role swapping“.. The USB4604 device’s downstream port 1 is able to swap with the upstream host port, transferring the host capability to the device on that port, such as smartphones and tablets. For example, smartphone ecosystems of software and applications can be connected to an automobile infotainment system. Other key features of the USB4604 include integrated battery-charger capabilities, Microchip’s VariSense™ and PHYBoost technologies which ensure optimized signal strengths and robust operation in the harsh Electromagnetic Interference (EMI) environments, and an HSIC interface which enables USB circuit board connections and results in dramatically lower power consumption.
FEATURES & BENEFITS
◆ FlexConnect technology for USB host and device swapping or to enable dual-host switching. FlexConnect expands USB topology alternatives providing greater flexibility for embedded USB hub applications.
◆ Integrated microcontroller for I/O bridiging including I2C, GPIO, UART and SPI adds improved embedded system control and communication.
◆ Hard-wired support for BCD 1.2, Apple® and China profiles eliminates the need for software develop-ment and shortens time to market.
◆ HSIC interface for board-level USB connections dramatically reduces power consumption.
Microchip Technology2355 West Chandler Blvd.ChandlerAZ - Arizona85224United States480-792-7200888-MCU-MCHP480-792-7277here2help@microchip.comwww.microchip.com
CONTACT INFORMATION
Hubs
21www.eecatalog.com/usb Software
CONTACT INFORMATION
engineers’ guide to USBMiddlew
are
HCC Embedded
TECHNICAL SPECS
◆ Extensive Class Driver Support - External Hub - Mass Stor-
age - Remote NDIS (RNDIS) - CDC Abstract Control Model
(CDC_ACM) - CDC Ethernet Control Model (CDCECM) - CDC
Ethernet Emulation Module (CDC-EEM) - OBEX devices -
FTDI USB serial devices - Audio - Midi - Human Interface
Device (HID) - Media Transfer Protocol - Printers - PICT-
BRIDGE - Personal Healthcare Device (PHCD)
◆ HCC’s unique position as a middleware developer means
that we can offer tight integration of file systems, serial and
Ethernet interfaces to support communications between
different protocols. Connecting different devices to a PC
used to involve many hardware inter- faces and protocols
– e.g. Ethernet ports, serial ports, ATA/IDE interfaces, audio
ports, video adapters etc. HCC USB provides the capability
to share a single high- speed bus between many peripheral
types - connecting TCP/IP networks over USB interfaces
either as local or remote network adapters.
AVAILABILITY
Immediately for Cortex-M0/M1/M3/M4/R4/A8, ARM7/9/11;
Atmel AVR32, SAM3/4/7/9; Cold- Fire, Kinetis, PowerPC,
i.MX, Vybrid, QorIQ; C164, XMC1000, XMC4000;
PIC24, PIC32; NXP LPC1300/1700/1800/2000/3 000/4000;
SuperH, RX, RL, 78k; EFM32, SIM3; FM0/
FM3/FM4; STM32; MSP430,
Stellaris, C2000, Hercules, DaVinci, Sitara, Tiva; TMP M0/M3
APPLICATION AREAS
Any embedded application requiring USB Connectivity.
Embedded USB
FreeRTOS, Keil RTX, MQX, Nucleus, Quadros RTXC, ThreadX, u-velOSity, uC/OS-II, CMX RTX, eCOS, emBOS, EUROS, ‘no-RTOS’, custom schedulers & super loops.
USB Host, Device & OTG
Embedded USB for ProfessionalsHCC has invested millions of dollars developing software using
an advanced embedded framework (AEF). This means we can
supply USB peripheral software for any embedded processor with
seamless support for any RTOS or scheduler. HCC middleware was
designed to be truly target independent and portable - it simply
drops-in, even if you use ‘no RTOS’ or a scheduler you developed
yourself. If you need a complete, integrated solution HCC supplies
eTaskSync, a highly efficient RTOS which is available with a full
software verification suite including a static analysis report, MC-DC
testing, and 100% statement and object code coverage. Why lock
your USB development to a single RTOS, MCU or compiler?
FEATURES & BENEFITS
◆ HCC’s USB Host stack is a scalable suite that
enables an embedded host to control a variety of USB devices
including pen-drives, printers, audio devices, joysticks, virtual
serial ports and network interfaces. The embedded USB host
stack supports EHCI, OHCI and non-standard USB controllers.
◆ HCC’s USB device stack allows developers to
integrate USB device functionality into their embedded
devices. It is available with a comprehensive suite of class
drivers that gives the device many functional possibilities,
including operating as a pen-drive, virtual serial port, joystick,
audio system or a network card.
◆ On-the go acts as a switch between the USB host
and device stacks, determined by the state of the ID pin. In
many cases, OTG software is not required. HCC provides the
hooks for this configuration as standard with the EUSB host
and device stacks. HCC also provides a full software OTG
stack that supports the SRP and HNP protocols for negotiat-
ing between two connected devices in order to decide
which one shall operate as the host.
◆ HCC USB comprehensively
supports all USB End-point/Transfer Types and Interface
Speeds including Low (1.5Mbs), Full (12Mbs) and High
Speed (480Mbps). Transfer types include Control, Interrupt,
Bulk, and Isochronous, providing the base for the widest
possible range of class drivers.
◆ HCC provides
support for multiple USB functions to be used on the same
device.
HCC Embedded7500 Rialto Blvd., Suite 250Austin TX 78735USATel: 1-512- [email protected]
Chips
201522
engineers’ guide to PCIe
Brick by Brick: Q&A with PCI-SIG President and Chairman Al Yanes and PCI-SIG Board Member Ramin NeshatiPCI Express is a low-cost I/O technology contender that supports a range of applications,
from high performance computing to low-power, mobile devices and anything
in between—significant for developers in the embedded and IoT era.
By Anne Fisher, Managing Editor
EECatalog: What are some recent activities of PCI-SIG
that have direct bearing on capturing IoT opportunities?
Ramin Neshati, Board Member, PCI-SIG: PCI-SIG is
interested in ensuring that its flagship I/O PCI Express
(PCIe®) technology is adopted across the breadth of the
industry and communications technology (ICT) industry.
To increase PCIe support in IoT, embedded and mobile/
low-power usage models, PCI-SIG is taking steps to
educate its members and the industry at large on the
many attractive features of this technology that have
direct relevance to these emerging and growing market
segments.
For instance, PCIe technology is natively supported by all
major operating systems with its robust device discovery
and configuration mechanism; a rich set of power
management and error reporting features; and dynamic,
hardware-autonomous or software-driven link width
negotiation procedures to increase/decrease interconnect
lanes as the need arises. For I/O expansion beyond the
chip-to-chip implementations, PCIe architecture supports
a plethora of card, module and cabling solutions across the
compute continuum.
EECatalog: Say you are an engineer thinking about the
ways to make optics cost-effective: What questions should
you ask?
Al Yanes, President, PCI-SIG: While there is no current
work group for optics within PCI-SIG, if I were to say
something [to your readers] I would say, “Develop cost-
effective optics that the industry could potentially use in
the future.” And, right in line with that, any questions
posed to the subject matter experts who serve on PCI-SIG
technical work groups would center on two concerns.
One, cost. We are very sensitive to cost. PCIe technologies
are broadly adopted primarily because low cost is one of
our founding principles. Anybody who uses PCI Express
technology in their implementations must be able to do
it in the least expensive manner possible.
The other concern is power. In addition to considering
the cost of implementation and the cost of optics-ready,
photonics-ready components, one must consider how
much power is being consumed. Whether it be an HPC
application, PC platform or low-power mobile device
that draws power, computes and communicates, we
want it integrate PCI Express technology. Nowadays,
users are mobile and want their devices to go with them,
Ramin Neshati,
Board Member,
PCI-SIG
Al Yanes,
President,
PCI-SIG:
For the range of applications that spans everything from mobile to high performance computing (HPC), the PCI-SIG believes PCI Express can serve as the I/O architecture. Courtesy commons.wikimedia.org
23
engineers’ guide to PCIe
www.eecatalog.com/PCIe
which goes hand-in-hand with requirements for
long battery life. For that reason, we insist that
PCI Express technology be a globally recognized
low-cost I/O architecture that can support
a breadth of computing devices, from those
requiring high performance computing power to
low-power mobile applications.
EECatalog: Would it be fair to add security to
that list of concerns?
Ramin Neshati, Board Member, PCI-SIG: Yes,
but since security is such an expansive topic let
us narrow it down a bit. For instance, we won’t
touch on data encryption or authentication/
access control in this context. Given that a
platform can be envisioned as having a hardware
layer, a firmware or virtual management layer, a
layer with the software/OS and then applications
stacked above that, security mostly comes into
play around the middle to top layer—that is
where it is relevant today and that is where most
security-related solutions live.
In today’s platform architectures [Security]
features don’t emanate from the hardware layer
as much, and that is part of the problem (the
other part being exposed or unprotected attack
vectors). That is one of the reasons why we have
growing threats from viruses, phishing and the
like, because there is no hardware-autonomous
way to detect and neutralize malicious intent
and malicious code—whether they originate
from sophisticated hackers or from enterprising
“Nigerian royalty.”
The wave of the future may be that security should be embedded in the
hardware. We may be headed in that direction, a move that the question,
“How is PCIe technology going to provide security features or enable a secure
I/O interconnect or link?” anticipates. Today, the PCI-SIG is not developing
“Secure PCIe” and perhaps there should be a vetting of requirements and
careful analysis of potential solutions. The PCI-SIG is responsive to the
needs of its members and when such a request picks up steam and the
ecosystem pushes for it then the PCI-SIG will surely respond.
In today’s world, though, security is primarily concerned with the
aforementioned firmware and software layers. However, having said that,
for a structure in which cost is the first brick and power is the second brick,
I can easily see that security will be the third brick.
201524
engineers’ guide to PCIe
RAS Data Protection Considerations for PCI Express DesignsUsers in the PCI Express storage sector and the military, aerospace, enterprise and other data-critical
markets can’t make do with less than high reliability—SoC designers have novel approaches to consider
for keeping these users happy as enterprise-grade storage morphs to direct-attach PCI Express.
By Richard Solomon, Synopsys
T he PCI Express® protocol includes a robust set of Reliability,
Availability, Serviceability (RAS) features, but it is up to the SoC
designer to ensure this protection is maintained throughout the SoC.
For the past few years, most design teams have considered the bus
itself to be the primary source of data transmission errors. However,
with the advent of teen-nanometer FinFET processes and the migra-
tion of enterprise-grade storage to direct-attach PCI Express, more
and more attention is turning to on-chip data protection.
ERROR DETECTION SCHEME SUITABILITYPCI Express transmitters add a 32-bit Link Cyclic Redundancy Check
(LCRC) to every data packet they send, and the receiver is required
to recalculate the received packet’s CRC and check it against the
incoming LCRC to confirm good receipt (Figure 1). Any bad packets
are negative acknowledged (NAK’d) and retransmitted automatically.
What happens to the data after receipt, however, is up to the PCI
Express controller and SoC designers.
CRC is an error detection scheme that is well suited to serial data
streams, but its overhead has generally left it unused for parallel
data—such as the received and de-serialized PCI Express packets in a
PCI Express controller.
PARITY PROTECTION AND PARALLEL DATAOne fairly simple technique for error detection, which lends itself well
to such parallel data, is parity protection (Figure 2). One parity bit is
appended to the datapath for each n bits (usually 8) of actual data,
such that the total count of ones in the binary field is either even or
odd—depending on the variation chosen. For example, in an 8-bit
even parity system, the parity bit for the value 255 (1111_1111 in
binary) is 0—as there are 8 ones in the binary representation of 255.
In that same system, the parity bit for the value 254 (1111_1110 in
binary) would be 1, as there are only 7 ones in the binary representa-
tion of 254, so an additional one is needed in the parity
to make the total count even. (As a historical note, back
in parallel bus days, even parity was preferred because
the pull-up resistors common to many busses meant an
undriven bus would be read as 1111_1111 with parity
1, for 9 ones and thus an even parity error.)
Parity, however, is only capable of detecting errors, and
it doesn’t always do that very well when multiple bits
are in error. In the 255 example, consider if two bits
were both in error: both 1111_1111 (the correct value)
and 1110_1110 (bits 0 and 4 inverted) have 0 for their
parity bit, therefore the 2-bit error case would go unde-
tected (Figure 3).
The solution is to use more bits of protection informa-
tion per chunk of data. Whole volumes can be (and
have been) written about the mathematics behind such
codes, but with some number of extra bits, it is possible
not only to detect that the data has been corrupted,
but also to identify which specific bit(s) are in error.
These techniques are generally referred to as Error Cor-
recting Codes (ECC) because they invert the bad bit(s)
to recover good data from bad.
Figure 1: PCIe® LCRC covers packet header and data payload
Figure 2: Even parity examples for binary data
Figure 3: Two-bit errors going undetected
25
engineers’ guide to PCIe
www.eecatalog.com/PCIe
TRADEOFFSThere are tradeoffs in the number of bits used for ECC. For example,
the protection code could soon become larger than the data it protects!
For this reason, the industry has largely settled on ECC that can detect
and correct a single erroneous bit, but only detect when two bits are in
error. Some ECC codes in current use require 7 bits to cover 32 bits of
data, or 8 bits for 64 bits of data.
HOW MUCH PROTECTION IS ENOUGH?So how much protection is enough? As mentioned earlier, the answer
to this question depends heavily on the SoC’s application and silicon
technology.
For something like a display controller, an error in the datapath may
only cause a screen flicker or momentary artifact. For a consumer
application, this may be an acceptable outcome and not worth addi-
tional design effort and cost. For an aerospace application however,
the same may not be true! Likewise, storage controllers place a very
high emphasis on data integrity as most end users consider their disk
or SSD to be reliable media and have the expectation that their data
is written and read correctly. The enterprise space, where the data
in question might be bank account balances or financial transaction
records, also requires high levels of reliability. In more error-sensitive
applications, parity is certainly valuable for detecting an error before
it can lead to further corruption, but ECC holds a high appeal for its
ability to allow the SoC to continue operating correctly and without
loss of data.
RAS FOR SMALL PROCESS GEOMETRIESOver time, the robustness (real and perceived) of on-chip memories
has shifted. In the very early days of multi-micron NMOS processes,
on-chip RAM was considered only mostly reliable and therefore
almost always protected by parity. As the industry moved to CMOS
and sub-micron technologies, RAM reliability improved to the point
that many designers neglected any sort of data protection. Now as we
find ourselves amidst a shift to FinFET technologies in 16nm, 14nm,
and even smaller geometries, questions are again rising about the reli-
ability of on-chip RAMs.
With large capacity RAM taking up a good portion of the area of a
small die, the likelihood of an external disturbance from a cosmic
ray strike or similar becomes even higher. With on-chip CPUs in SoCs
now routinely having 64-bit data paths, the data overhead for ECC
compared to parity rapidly disappears. Notice that for our example
byte-parity (1 parity bit for 8 bits of data), a 64-bit datapath requires 8
protection bits—the same number as can be used by an ECC to provide
single-bit correction with double-bit detection.
ECC ON RAMThe on-chip RAM is of greatest concern, so many SoC designers are
moving to utilize the simpler option of parity protection on the
actual datapaths and the more capable option of ECC on their RAM.
The RAM accesses that occur over multiple clock cycles lend well
to the correction aspect of ECC—as at high frequencies, ECC logic
may need more than one clock cycle to handle a correctable error.
Because the errors require more than a single clock cycle for correc-
tion, many design teams are finding that ECC is best implemented in
the control logic rather than inside the RAM itself. In the case of a
PCI Express controller, natural internal pipelining can accommodate
the correction phase of ECC without loss of throughput and without
forcing complex logic onto the on-chip RAM subsystem trying to meet
ever-smaller access time requirements.
SUMMARYAs designers look to implement PCI Express in today’s design and
application environments, they should ensure that their PCI Express
controller supports at least byte parity (in their choice of odd or even
variations) on its entire datapath, and at least some type of ECC on
its RAM. Some designers may even want to consider using ECC on the
datapath instead of parity—accepting slightly more complex imple-
mentation as a tradeoff for the higher reliability demanded in PCIe
storage and other data-critical markets.
Richard Solomon is the technical marketing manager for Synopsys’ Design-
Ware PCI Express Controller IP. He has been involved in the development
of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the
PCI spec. Prior to joining Synopsys, Solomon architected and led the devel-
opment of the PCI Express and PCI-X interface cores used in LSI’s line
of storage RAID controller chips. He has served on the PCI-SIG Board of
Directors for over 10 years, and is currently Vice-President of the PCI-SIG.
Solomon holds a BSEE from Rice University and 26 US Patents, many of
which relate to PCI technology.
Figure 4: Using ECC for multi-bit error detection
201526
engineers’ guide to PCIe
GHz Timing Giving You the Jitters? Three Things You Need to KnowClock jitter can adversely affect high-speed protocols such as Ethernet, PCI Express and
USB 3.0. You can calm your system down knowing these three simple points.
By Chris A. Ciufo, Editor-in-Chief, Embedded Systems Engineering
T iming is everything, which is why jitter skews everything up.
Jitter is the difference between expected and actual timing edges
in a system; the worse it becomes—the more adversely it affects your
system (Figure 1). Jitter is proportional to lower voltage thresholds,
directly proportional to clock frequency, and a major source of bit
error rate (BER) in high-frequency GHz systems.
In this short primer we’ll:
1. Show how jitter affects signals at the receiver
2. Describe the simplest way to reduce source jitter
3. Show some examples of systems designed with low-jitter components.
POINT #1: HIGH-PERFORMANCE SIGNALS REQUIRE LOW JITTER AT RECEIVERS.Digital systems require high precision clock sources from either
crystals or crystal oscillators. 40 Gb Ethernet, for example, requires a
clock source with under 0.3ps of jitter. When there’s jitter in the refer-
ence clock, it’s amplified by clock timers and PLLs in the PHY (Figure
2), since the phase lock loop responds to the clock edges.
An out-of-phase clock can often skew a GHz signal beyond an accept-
able spec at the receiving end. The higher the data rate, the more
accurate the source timing source must be. That is: as data rates
increase, the jitter requirements tighten.
Lower jitter means lower BER, and lower BER is better. Improving
jitter lowers BER because at the receiving end, the Rx circuitry must
recover the transmitted clock from the bit stream by: 1)
knowing when to sample the bit stream; and 2) deter-
mining if the data represents a “0” or a “1.” The encoded
bit clock determines when the receiving data is to be
sampled; if the clock is phase-shifted due to jitter, the
receiver may sample the bit stream at the wrong time,
which results in bit errors.
POINT #2: START WITH A LOW-JITTER CLOCK SOURCE AT THE TRANSMITTER.If GHz signals like HDMI (~ 10 Gbits/s) or USB 3.0 (5
Gbits/s) require low jitter at the transmitter, the best way
to reduce source jitter is to start with an ultra “clean,” low-
jitter clock source.
While jitter has many possible sources at the transmit-
ting end, the biggest “bang for the buck” can be achieved
through the source clock. A high-quality clock source may
widen the jitter margin of the system (“system” = source,
Tx, link, Rx), reducing the need for extended and excruci-
atingly complex engineering effort to reduce second- and
third-order jitter sources like cross-coupled traces or
inducted skin effect in PCBs.
Figure 3 shows a crystal oscillator demo board from Per-
icom Semiconductor with a 156.25 MHz XO source. The
XO populated on this board is spec’d having a maximum
RMS jitter of 0.2ps—30 percent lower than that required
by 40 Gb Ethernet, giving a comfortable Rx margin on an
Ethernet link.
Figure 1: Jitter as the clock phase shifted from its expected position.
Figure 2: Jitter is amplified by clock timers and PLLs, compounding the problem.
27
engineers’ guide to PCIe
www.eecatalog.com/PCIe
Figure 4: Using a phase noise analyzer by Agilent (top) and a LeCroy 6 GHz scope (bottom), the jitter of the demo board from Figure 3 is shown to be 0.111 ps (shown as 111.949 fs).
Figure 5: A typical low-jitter system starts with an ultra-low-jitter XO. (Courtesy: Pericom Semiconductor.)
How about in actual practice? Using an
Agilent phase noise analyzer and a LeCroy
6 GHz scope, the XO exhibits a real-world
jitter of 0.11 ps, which is well below that
required by 40 Gbits/s Ethernet (Figure
4). This low-jitter clock source means that
other components in the system can inject
nearly 0.2ps additional jitter before the
link jitter becomes out of spec (and out of
an acceptable BER range). Clearly, starting
with a low-jitter clock source gives a GHz
system designer more breathing room in a
design.
POINT #3: KNOW HOW TO USE THE XO IN A SYSTEM.A typical GHz system is shown in Figure
5. Here, an ultra-low jitter XO feeds a clock
buffer that provides multiple clocks for a
variety of GHz devices, including a 40 GbE
PHY, an Ethernet switch and a ternary
content addressable memory (TCAM), part
of a layer 3 router. Pericom’s UX7 series XO
is the heart of the low-jitter system, and is
capable of approximately 0.1ps (RMS) jitter
between 12K – 20 MHz as Figure 4 shows.
To avoid using multiple XOs in a system,
the PI6C49S1510 clock buffer can provide
up to 10 output clocks (three are shown in
Figure 5), with a very low additive jitter of
0.03ps—essentially replicating the XO’s
low jitter to all of the outputs. Figure 6 is a
screenshot of the same bench test as Figure
4 but at an output downstream of the clock
buffer. Note the total RMS jitter of the XO
plus buffer is only 0.15 ps RMS. For conve-
nience, both the XO and the clock buffer
run on 2.5 or 3.3VDC, further simplifying
designs.
XO AND BUFFER ALL-IN-ONEAnother way to create low-jitter systems
besides what’s depicted in Figure 5 is to
use. Pericom’s FlexOut clock generator,
which combines an XO and clock buffer
into a single package. The frequencies
involved and the need for ultra clean (low-
jitter) clocks, are the reasons the FlexOut
PI6CXG05F62a has an even lower jitter
spec than the previously described XO
(~0.1ps [typical]/0.15ps [max] from 12K –
20 MHz) and supports up to six outputs in
LVPECL and LVDS configurations.
Figure 3: The UX704 demo board from Pericom Semiconductor is useful for demonstrating a low-jitter clock source. (Courtesy: Pericom Semiconductor.)
Figure 6: The total jitter of the notional system shown in Figure 5 using Pericom demo boards in the same bench set-up as Figure 4. Total additive jitter is a mere 0.15 ps (RMS).
No external XO is needed (that’s the whole
point!), and neither XO trace terminations
nor XO power filters are required. This
device uses Pericom’s proprietary quartz
timing source with a special clock IC
shrunk into a small LQFP package that’s
smaller than the two devices it replaces.
Regardless of which architecture a designer
uses—XO alone, XO plus clock buffer, or
a fancy combo device like the FlexOut—
low BER GHz systems require low jitter.
Starting at the transmitter, right at the
clock source.
This article was sponsored by Pericom
Semiconductor.
201528
engineers’ guide to PCIe
Application Solutions
ACCES I/O Products, Inc
TECHNICAL SPECS
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◆ For embedded OEM type applications, an additional micro-fit USB input header is provided in parallel with the type B connector.
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◆ Digital Input / Output USB DAQ Products for com-pact control and monitoring applications. Choose from 4 to 96 channels offering various voltage, isolation, speed, and counter/timer options.
◆ Serial Communication USB Products. Simply install the included software and connect our product to your USB port and transform it into asynchronous serial ports for communication with serial instru-ments. 1, 2, and 4-port models are available.
◆ Custom USB I/O Products. 23 years of product development, 350 COTS products, over 750 specials and options. If you don’t see what you need, ask us and we will make it for you.
ACCES I/O Products, Inc. 10623 Roselle Street San Diego, CA 92121 USA1-800-326-1649 Toll Free858-550-9559 Telephone858-550-7322 [email protected] http://acces.io
Boa
rds
CONTACT INFORMATION
29www.eecatalog.com/PCIe Hardware
engineers’ guide to PCIe
General Standards Corporation
APPLICATION AREAS
Precision Voltage Array Servo Control Waveform Synthesis High Density Outputs Process Control Industrial Robotics
AVAILABILITY
Off the Shelf to 4 weeks ARO
Analog, Digital and Serial I/O Boards
1 lane and 4 lane
Window, Linux, LabView, VX Works
PCIe, PCI, PMC, VME, PC104P, and PC104-Express
General Standards Corporation develops and manu-factures the highest-performance Analog, Digital and Serial I/O products based upon a variety of buses such as PMC, PCIe, PC104Plus, VME, and cPCI. Our extensive product line (over 100 products) includes I/O boards, cables and software drivers.
FEATURES & BENEFITS
◆ Precision 16-Bit analog outputs: DAC per Channel◆ 256K-Sample output data FIFO buffer; Configurable
as open or closed (circular) ◆ High accuracy ensured by on-demand Autocalibra
tion of all channels, with outputs forced to zeroduring autocalibration.
◆ Multiboard synchronization supported◆ Output clocking rates to 500K samples per second
per channel with all channels active
TECHNICAL SPECS
◆ Up to 64 Input Channels per Board◆ Programmable Sampling Rates to 50M SPS◆ GPS Synchronization◆ Auto-Calibration◆ Multi-Board Synchronization◆ Sigma-Delta and Delta-Sigma Analog I/O◆ Resolutions from 12 bits to 24 bits◆ IEPE Compatibility
Free Drivers for Windows, Linux and LabView
Free Loaner Boards
General Standards Corporation8302 Whitesburg Dr.Huntsville, AL 35802 USA256-880-8787 Telephone1800-653-9970 Toll Free256-880-8788 [email protected]
CONTACT INFORMATION
Boards
201530 Hardware
engineers’ guide to PCIeB
oardsDev
elopment
Teledyne LeCroy
◆ l with Teledyne LeCroy’s Interposer technology. Prevents loosing the trace when the system goes into electri-cal idle.
◆ Tel shows only the necessary protocol handshaking ack/naks so you don’t have to be a protocol expert to understand if root complexes and endpoints are communicating properly.
Teledyne LeCroy’s PCI Express®Protocol Analysis and Test Tools
PCI Express Standards: 1.1, 2.0, and 3.0
Whether you are a test engineer or firmware developer, Teledyne LeCroy’s Protocol Analyzers will help you measure performance and quickly identify, troubleshoot and solve your protocol problems.
Teledyne LeCroy’s products include a wide range of probe connections to support XMC, AMC, VPX, ATCA, microTCA, Express Card, MiniCard, Express Module, CompactPCI Serial, MidBus connectors and flexible mult-lead probes for PCIeR 1.0a, 1.1 (“Gen1” at 2.5GT/s), PCIe 2.0 (“Gen2” at 5 GT/s) and PCIe 3.0 (“Gen3” at 8 GT/s).
The high performance Summit™ Protocol Analyzers feature the new PCIe virtualization extensions for SR-IOV and MR-IOV and in-band logic analysis. Decoding and test for SSD drive/devices that use NVM Express, SCSI Express and SATA Express are also supported.
Teledyne LeCroy offers a complete range of protocol test solutions, including analyzers, exercisers, protocol test cards, and physical layer testing tools that are certified by the PCI-SIG for ensuring compliance and compatibility with PCI Express specifications, including PCIe 3.0.
FEATURES & BENEFITS
◆ Lists all protocol errors found in a trace. Great starting point for beginning a debug session.
◆ o that quickly shows credit bal-ances for root complex and endpoint performance bottlenecks. Easily find out why your add-in card is underperforming on its benchmarks.
◆ that accurately shows power state transitions with hyperlinks to drill down to more detail. Helps identify issues when endpoints go into and out of low power states.
31www.eecatalog.com/PCIe Hardware
engineers’ guide to PCIe
CONTACT INFORMATION
Teledyne LeCroy3385 Scott Blvd.Santa Clara, CA, 95054USA1 800 909-7211 Toll Free1 408 727-6622 Faxpsgsales @teledynelecroy.comwww.teledynelecroy.com
◆ a puts the analyzer into a monitoring mode showing rates for any user term chosen. Good for showing performance and bus utilization of the DUT.
◆ provides a fast way to search large traces for specific protocol terms.
◆ Co can be displayed in its entirety so that driver registers can be verified.
TECHNICAL SPECS
◆ a X1,x2,x4,x8,x16
2.5GT/s, 5GT/s and 8GTs active and passive PCIe
slot,XMC, AMC, VPX, Express card, Express Module,Minicard, Mid-Bus, Multi-lead, External PCIe cable,CompactPCI, Serial U.2/SFF-8639, M.2/NGFF and
others Card, Chassis
◆ X1,x2,x4,x8,x16 2.5GT/s, 5GT/s, 8GT/s
root complex and endpoint emulation
◆ 2/5/8 GT/s operation
Test PCIe 2.0/ 3.0 compliance(Certified by PCI
SIG for Link/Transaction layer tests) Test NVMe Conformance (Required by UNH- IOL for NVMe Conformance Integrators List) Corner Case Testing LTSSM Testing Dynamic Equalization Testing Speed/link Test Arcs G2 Validation tests PTM Testing L1 Substate Testing
APPLICATION AREAS
SSD, Switches, Servers, Storage, Add-in Cards, Chips
Boa
rds
Deve
lopment
201532
engineers’ guide to ETHERNET
What’s Promising to Widen Ethernet AVB’s Scope?Automotive design is adopting a collection of IEEE standards for real-time audio.
Can the standards succeed in industrial automation and robotics, too?
By Caroline Hayes, Senior Editor
Ethernet Audio Video Bridging (AVB) takes the same
ease of connectivity that the Ethernet affords com-
puter networks to connect A/V products, running on the
same network within a vehicle.
Ethernet AVB is a set of international standards designed
for developers to set up and manage networks. The exten-
sions add timing, bandwidth reservation and rules for
forwarding and queuing to provide wireless, synchro-
nized and low-latency streaming to a vehicle’s screens and
speakers.
Each endpoint, such as a speaker, has its own unique
address and connects to the network via an Ethernet
switch. If there are several switches, and the signal travels
a long distance between endpoints, timing delays and
mismatched or out-of-sync A/V can result.
JITTER-FREE TRANSPORTEthernet AVB makes A/V traffic a priority. It reserves as
much as 75 percent of the available Ethernet bandwidth
for AVB traffic. One of the protocols is the Stream Reser-
vation Protocol (IEEE 802.1Qat). It allocates bandwidth
and splits traffic into real-time and non-real-time packets.
Real-time traffic is scheduled every 125μs at 8 Hz. Other
packets are transmitted in the intervals to allow the traffic
to be sent endpoint to endpoint in a 2ms window.
The Precision Time Protocol (PTP) synchronizes the
traffic, using clocks to synch, delay and manage signals.
PTP nodes are connected using Ethernet cables. Another
protocol used is the Discovery Protocol, IEEE 1722.1.
This Layer 2 transport protocol discovers, catalogs and
controls attached devices, allowing the host to configure
the system.
UK-based XMOS, a fabless semiconductor company,
advances Ethernet AVB’s synchronization further, with
the xCORE multicore microcontroller family, which places
the input and output into separate tracks, for predictable
operation. Cores manage the “talker” endpoint input (for
example, a media player) and the “listener” endpoint output (for example,
a speaker), using a global clock. The event-driven, deterministic architec-
ture results in jitter-free transport of data, says the company, as it uses
time-stamped inputs and output-on-request. The Stream Reservation
Protocol guarantees the real-time flow of data is not disrupted or dropped.
The xCORE microcontroller is programmed in a C-based, high-level
language allowing it to be reconfigured during development and even
configured when it has been deployed, as standards evolve.
Ethernet AVB enjoys success chiefly in the professional audio market at
present. According to Paul Neil, vice president marketing and business
development, XMOS, companies in this market are not likely to move
their Ethernet AVB offerings into other areas. He believes the professional
audio industry has cultivated a closed system with no interoperability and
no ecosystem. This makes it impractical for it to spread to, for example,
automotive, the next largest market. “No automotive vendor is going to
go single-source,” he reasons.
A broader application Neil does envisage is time-sensitive networking.
Precise timing means that things happen on a network at identi-
fied times. A sensor could be built into the AVB. Information can be
Figure 1: The xCORE-200 is a microcontroller from fabless semiconductor company XMOS that offers up to 32 logical cores and 4000MIPS processing power. With an Ethernet AVB stack, it can be used in consumer and automotive applications.
33
engineers’ guide to ETHERNET
www.eecatalog.com/ethernet
The Microchip name and logo and the Microchip logo are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. All other trademarks are the property of their registered owners. © 2015 Microchip Technology Inc. All rights reserved. /15DS00001918A
www.microchip.com/ethercat
Next Generation EtherCAT® Slave
Controller
The future of industrial networking is here! Introducing the next
generation of EtherCAT® slave controller. This highly integrated
Dual integrated Ethernet PHYs with
transceiver
201534
engineers’ guide to ETHERNET
Figure 2: Paul Neil, XMOS, believes the company’s early adopter status is paying dividends in Ethernet AVB design wins.
Figure 3: Marc Serughetti, Synopsys, believes newer microcontrollers and SoCs need to be supported in simulation to prepare for an increase in Ethernet AVB in automotive, consumer and industrial applications.
transmitted across a network, with time
stamping, to build a view of what is hap-
pening across the network.
INTEROPERABILITY EFFORTSFor Neil, the automotive market is the
most promising. The company has just
secured a design win in a major automo-
tive OEM (Neil elected not to name the
OEM during our interview). The win, in a
vehicle’s audio distribution system, vali-
dates what Neil describes as XMOS’s early
adopter position. The company has been
running the stack for six years, he notes.
However, unlike professional audio, where
there is no ecosystem or interoperability,
the automotive market is working towards
uniting vendors to work together and for
AVB system interoperability.
The AVnu Alliance is one body that
is working to get equipment vendors
together to interoperate, Neil points out.
“It is working to make the plug-and-play
promise offered by AVB a reality,” he says.
Vendors offer configuration and control
software to set up AVB networks. For this
reason, believes Neil, the AVB market will
“explode” in 2018/19, as widespread adop-
tion in the automotive market takes place.
This will far exceed the A/V Pro space, he
predicts, anticipating multiple automotive
AVB standards that will drive new silicon.
A natural progression will be for AVB
to support Gigabit Ethernet (GbE). The
support will allow transmission of more
compressed video than the 10/100 net-
works currently allow. Applications outside
of the automotive market will also benefit.
In business use, the ability to aggregate is
in AVB’s favor, says Neil. Multiple High-
Definition (HD) video screens could be
used in conferencing systems, for example.
Another use in enterprise would be in con-
ferencing to coordinate microphones and
speakers.
SUPPORT FOR TIMING-CRITICAL APPSMarc Serughetti, director business
development protoyping, automotive,
Synopsys, confirms “Ethernet AVB is
growing in importance.” Serughetti adds
that this growth “ impacts the software
used in the automotive system. There is a
need to expand the support for software
to be tested . . . and to adapt it to automo-
tive requirements.” Among these areas
are infotainment, Advanced Driver Assis-
tance System (ADAS), video information
within the car and, more recently, safety-
critical powertrain.
Synopsys works with semiconductor
partners like Infineon and Freescale to
create Virtual Development Kits (VDKs)
to enable Ethernet AVB.
Earlier this year, it released a VDK for the
Renesas RH850 microcontroller with Eth-
ernet AVB and Controlled Area Network
– Flexible Data (CAN-FD). Its role is to
develop and improve software quality to
support the RH850-based processor, core
and peripherals in automotive systems.
In addition to the automotive market and
the professional A/V market, Serughetti
believes that the industrial space will
also employ Ethernet AVB. “The timing-
critical applications will benefit,” he says,
as systems will leverage Ethernet com-
munications with constraints. This will
guarantee the messages sent and received
within the time constraints,” he explains,
for precision automation. Serughetti can
see using Ethernet AVB to adjust the
movement of a robot arm based on video
data processed.
For Neil, however, AVB protocol is likely
to be just another set of standards in the
industrial space, which he describes as
already “deeply fragmented.” It is because
of this that he believes adoption in the
industrial space will be slower than in
other areas. Although he does see timing
applications, as a superset for data acqui-
sition and monitoring, perhaps within
five years.
As for when Ethernet AVB will be included
in robotics, Neil’s answer is “maybe never.”
He goes on to say, “It’s not just about using
time stamp information to determine the
state of a system at any given time—some
of the neural path networking standards
in the robotic space do that already. It is
the ability to close the control loop, so you
can send a command to the arm of the
robot and know that the robot has to be
able to respond within a certain amount
of time.” He cites the example of changing
an operation within a robotic system: “[It]
will need to close a control loop, sense
where the robotic arm is and provide
adjustment within 100s of kHz—I am not
convinced AVB can do that.”
Wherever Ethernet AVB progresses, it is
reassuring to know there is silicon and
software support to help it along its way.
Author. Caroline Hayes has been a journalist,
covering the electronics sector for over 20
years. She has worked on many titles, most
recently the pan-European magazine, EPN.
Now a freelance journalist, she contributes
news, features, interviews and profiles for
electronics journals in Europe and the U.S.
201536
engineers’ guide to ETHERNET
Analog High Speed Communication Devices for 40G/100GB Ethernet Require a Totally New Approach to TestAnalog high speed communication devices are far from fitting into a standard, high volume
manufacturing test process with a well-established set of best-known practices.
Cédric Mayor, Chief Technical Officer, Presto Engineering, Inc., Caen, France
Analog high speed communication devices are far
from fitting into a standard, high volume manu-
facturing test process with a well-established set of
best-known practices.
The Internet of Things (IoT) is going to be the next
booming RF wireless market as it pushes the growth of
the cloud infrastructure driven by consumer demand
for ubiquitous and instantaneous access to informa-
tion. We often focus, for very good reason, on how
those billons of sensors and chips will be connected to
the premise and access of the infrastructure, but we
forget quite consistently that those data streams must
also be backhauled to the core network and routed to
the appropriate data-center. Bandwidth in the optical
network and datacenter is already starting to catch-up
with the ever growing demand in mobile and video data.
The Cisco IP traffic survey (Figure 1) shows bandwidth
demand rising at the infernal pace of 48% CAGR.
To avoid being overwhelmed by this data tsunami, the
industry has answered with aggregating more band-
width. Both the infrastructure and service providers
have started to deploy Ethernet high speed links at
40Gbps and 100Gbps mainly at the top of their network
for aggregation routers and switches and long haul transponders. The
100G Ethernet, based on optical components, is rapidly displacing the
10G workhorse of the last decade in the telecom and datacom industry.
Figure 2 from a recent IHS-Infonetics Research report does put a spot-
light on the inevitable arising of the 100G era in the network.
ANALOG NO LONGER MEANS SLOWTechnologically, analog means more wireless spectrum in the radio-
frequency, and more optical wavelengths and higher modulation
bandwidth in the optical transport network (OTN).
On one hand, RF telecom backhaul transceiver devices do move pro-
gressively to the 60 GHz (V-band), and the 70-80-90 GHz (E-bands)
and their respectively 7 GHz and 10 GHz of available spectrum to
be compared with 80 MHz in 802.11ac and maximum 20 MHz LTE
channels occupied bandwidth in the cellular space. Millimeter wave
backhaul transceivers do aggregate link of capacity above 1 Gbps,
reducing then the necessary need of a fiber to each radio head on the
tower sites.
On the other hand, 100G Ethernet optical ports do need optoelec-
tronic devices in optical module and telecom line cards, such as
Trans-impedance amplifiers (TIA) and Mach-Zehnder Modulator
drivers (MzMD). Those devices have to enable a 40 GHz signal band-Figure 1. IP Traffic trend and usage ratio.
Figure 2. Transmitted capacity per link data-rate.
37
engineers’ guide to ETHERNET
www.eecatalog.com/ethernet
width amplification and modulation with key linearity constraints
either for short or long reach OTN applications.
From an electrical test perspective, those analog high-speed commu-
nication devices are very different from their digital high-speed serial
devices and 40Gbps SerDes macros also included into the CFPx optical
module as illustrated by the Figure 3.
ANALOG HIGH SPEED IS A DIFFERENT TEST PARADIGMDigital high speed serial devices benefit from the CMOS integration
of test features, such as BIST and DFT enabling functional testing in
loopback, eye-monitoring embedded features inside the same piece
of silicon. As a test engineering work it is mostly a digital macro go/
no go testing with loopbacks on the test load board or even on-chip
TX/RX. During chip characterization, Automatic Test Equipment
(ATE) does answer that need with specific digital BER testing options.
Intrinsically the wafer level test does not actually differ from the SoC
mainstream test flow, and is exclusively a time domain testing (TD) at
package level (on large fan-out BGA). This final test implies short test
time helped by the parallelism offered by the mainstream ATE.
It is a totally different paradigm with the high speed analog chips in
the optical network serving as the analog front-end of the CFP client
module. TIA devices exhibit 4 analog differential channels/lanes
at 25Gbps and MzM Drivers 4 quadrature channels both over a 40
GHz bandwidth. The former is directly associated to the photodiode
detector (one diode per Lambda) and, the latter is directly associ-
ated to the optical modulator still in III-V hybrid substrate. Figure 4
illustrates the RX/TX optical module interface on a long haul coherent
optical CFP.
The
TIAs and MzM Drivers integration requires thus to be carefully
assembled into the multichip module still maintaining cutting-edge
40 GHz bandwidth stable gain, and insertion and return loss. If CMOS
silicon analog performance is always getting better, those high-speed
analog devices are manufactured mainly in III-V and BiCMOS process,
still 8 inch wafers. Indeed if RF-CMOS manufacturing
process can still promise acceptable 1/f noise, Noise
Figure (NF), and even better quality passive or trans-
mission line on HR substrate, it cannot sustain both
a crucial NF at 50 Ohms over 40 GHz bandwidth and
provide a FMIN and associated sufficient Gain as a
function of a low bias current compared with BICMOS
SiGe and InP HBT.
Therefore a Known Good Die RF Wafer Level Test (WLT)
is an imperative to maintain the complex module per-
formance, and hence, the assembly line module yield.
The semiconductor test manufacturing is used to
performing RF wafer level tests of billions of power
amplifiers, low noise amplifiers, cellular or connectivity
transceivers below the 6 GHz carrier frequency, and most
critically, a measurement bandwidth of less than 250
MHz. However, above this frequency, very few industrial
ATE are available in high volume manufacturing. It is also
true because RF ATE means high throughput and low test
time in narrow band, single tone scalar measurement.
However, quad channel 32Gbps TIAs testing requires
measuring the s-parameters, namely Gain and Output
Return Loss from 100MHz up to 40 GHz, to calculate out
the trans-impedance, but also group delay and in some
particular application the Total Harmonic Distortion
(THD) to evaluate the linearity of the devices. On top
of this frequency domain testing, parametric test of the
power supply is extremely important to reduce the impact
of the Input Referred Noise on the RF measurement.
All in one, it is far from a traditional production test
practice, and very close to a characterization set of fre-
quency tests using a highly automated rack of discrete
instruments. Indeed, ATE capital cost per unit cannot be
reduced with parallel testing and test times are way above
traditional RF connectivity or cellular devices ones. This
observation poses the question of the millimeter wave
radiofrequency test challenges to sustain such a volume
test operation.
Figure 3. Block diagram of a 100GB Ethernet client CFP to linecard interface.
Figure 4a. Optical Transmitter (TX) with MzM Driver IC in blue.
Figure 4b. Optical Receiver (RX) with MzM Driver IC in blue.
Figure 5. Overview of the automated RF WLT.
201538
engineers’ guide to ETHERNET
BRIEF INTRODUCTION TO MMW TEST CHALLENGES: A 25G QUAD-TIA CASE STUDY
Challenge 1: the traditional 3 rules of measurement.
Each measurement performed in the production RF
wafer level test suffers from the well known system-
atic, random and drifting errors. Regarding RF 40 GHz
WLT, the systematic measurement errors in forward
and reverse testing of our 25G 4-channels TIA has a lot
to do with the test cell mechanical and electrical design.
Among others, the directivity and cross-talk errors due
to the cabling custom set-up for the GSG probe and
supplies. The source and load impedance mismatches as
well as reflection and transmission tracking errors can
then only be limited by a very thorough Short-Open-
Load-Through (SOLT) calibration and this at every
incoming lot to avoid lot to lot variation over time.
The random error component is directly related to the
capability of managing very long test time and multiple
touch-downs over a single wafer. In our case of the 25G
4-channel TIA, the device can remain tested over min-
utes at hot and cold temperature insertion. In this case
device self-heating while probing as well as two neces-
sary touch-downs per die to measure the s-parameter
of the 4 differential channels are clearly the first detrac-
tors. They are followed by the VNA internal thermal
noise in time. Trade-off are always possible to mitigate
the random error, such as decreasing the IF bandwidth
to enhance accuracy or averaging on different sweeps,
with both solutions causing a longer test time.
The drifting error in our 40 GHz WLT is mainly depen-
dent upon the strict calibration process and mechanical
stability, thermal control at -/+ 5°C of the test cell.
Challenge 2: A key thorough probing and over travel control.
As already explained, two touch-downs with the RF GSG and DC
probes are necessary along the whole device testing. It mainly requires
carefully monitoring the contact resistance along the test, but also
between insertions to avoid offset in RF measurements. In addition,
DC probe pads are probed twice which increases the impact of the die
pad scrub form or bump tip mark on bonding yield, but also affects
the input referred noise injected between insertions, hence the TIA
channel to channel performance correlation and matching.
Such a two insertion per die approach could be mitigated by per-
forming a single touch-down on the 4 channel. If the capital cost
increased by adding equipments can be discussed, the probing would
have to move from wedge probes to membrane probe card well known
for their RF performances to improve isolation and probe congestion.
However, the inter-channel cross-talk when simultaneously sourcing
the 4 inputs is a fairly complex issue to handle and cause very difficult
repeatable tests.
CONCLUSIONIn a nutshell, analog high speed communication devices are far from
fitting into a standard, high volume manufacturing test process with
a well-established set of best-known practices. However the volume
of 100G optical ports is surging in long haul and metro aggregation
routers and transponders. This surge is not likely to abate with the
booming of the IoT, and within the supply chain semiconductor
manufacturing test has to bridge the gap between what was consid-
ered as a bench top characterization and what volume test production
worthy demands at the appropriate cost. This is the challenge Presto
Engineering has taken up by becoming the leader in the optical com-
munication electronics device production testing for the 40G/100GB
Ethernet market. It required a thorough learning curve and develop-
ment of dedicated methods, and it is now a fully sustainable production
operation, ready to support the rapid growth at the eve of the 400G
Ethernet ratification and the silicon photonic roll-out.
39
engineers’ guide to ETHERNET
www.eecatalog.com/ethernet ICs
Microchip Technology
TECHNICAL SPECS
◆ Fully compliant to the EtherCAT specifications◆ Four SynchManagers and three Fieldbus Memory
Management Units◆ 64-bit distributed clock◆ 4 KB of dual-port process memory◆ 100Base-Tx/100Base-FX
APPLICATION AREAS
Motor motion control, process/factory automation, communication modules and interface cards, sensors, power grids, building automation, hydraulic and pneumatic valve systems and operator interfaces.
AVAILABILITY
The LAN9252 is available in commercial, industrial and extended industrial temperature ranges and comes in either a 64-pin QFN or a 64-pin QFP-EP.
LAN9252
EtherCAT® Industrial Protocol
LAN9252 EtherCAT SDK for EtherCAT Slave Stack Code v5.11
The LAN9252 includes a 3-port EtherCAT® slave controller with 4 KB of dual-port memory (DPRAM), four SyncManagers, three Fieldbus Memory Management Units (FMMUs) and a 64-bit distributed clock. It supports four process data interfaces, including SPI/SQI, HBI and a 16-bit digital I/O. SPI and SQI (high-speed SPI) provide a low-pin-count synchronous slave interface that facilitates communication between the device and a host system. Whereas, the host bus interface facilitates the same via a high-speed asynchronous slave interface. For simple digital modules without microcontrollers, the LAN9252 can also operate in digital I/O mode where 16 digital signals can be controlled or monitored by the EtherCAT master. The LAN9252 can also be configured to operate via a single 3.3V supply utilizing an integrated 3.3V to 1.2V linear regulator. The internal linear regulator may also be disabled, allowing usage of a high-efficiency external regulator for lower system power dissipation.
FEATURES & BENEFITS
◆ Dual-integrated 10/100 Ethernet physical layer devices which reduce BOM cost, decrease board size and increase reliability by being integrated in the LAN9252.
◆ Cable diagnostics for ease of implementation time and network “up” time. Allows detection of open, short, distance to fault and cable length.
◆ Support for 100Base-FX fiber. Gives system devel-opers the flexibility of selecting their preferred media.
◆ Extended temperature range for harsh factor floor environments.
◆ Optional third port for network topology flexibility.
Microchip Technology2355 West Chandler Blvd.ChandlerAZ - Arizona85224United States480-792-7200888-MCU-MCHP480-792-7277here2help@microchip.comwww.microchip.com
ChipsC
hips
CONTACT INFORMATION
201540
engineers’ guide to ETHERNET
ICs
Microchip Technology
TECHNICAL SPECS
◆ EEPROM-less operation◆ Implements NetDetatch technology◆ Industrial temperature range◆ 56-pin QFN (8 x 8 mm), RoHS-compliant package
APPLICATION AREAS
Embedded systems, consumer electronics devices, netbooks/smartbooks/MIDs, docking stations, digital TVs, set-top boxes, Personal Video Recorders (PVRs), network printers, USB port replicators, standalone USB to Ethernet dongles and industrial designs.
AVAILABILITY
The LAN7500 is available now.
LAN7500 Hi-Speed USB 2.0 10/100/1000 Gigabit Ethernet Controller
802.3/802.3u/802.3ab Standards
Linux®, Mac®, Windows®, UEFI PXE
The LAN7500 contains an integrated 10/100/1000 Gigabit Ethernet PHY, USB PHY, Hi-Speed USB 2.0 device controller, 10/100/1000 Gigabit Ethernet MAC, TAP controller, EEPROM controller and a FIFO controller with a total of 32 KB internal packet buffering. The device supports 10Base-T, 100Base-TX and 1000Base-T Ethernet and implements control, interrupt, bulk-in and bulk-out USB endpoints. The Ethernet controller supports auto-negotiation, auto-polarity correction, HP Auto-MDIX support and is compliant with IEEE 802.3/802.3u/802.3ab standards. USB-based networking provides flexibility for the routing and placement of network connections anywhere in the system. USB-based solutions leverage the existing USB stack for the Ethernet driver. The LAN7500 is also available with a wide range of drivers including Windows®, Mac® and Linux®.
FEATURES & BENEFITS
◆ NetDetacth™technology: allows CPU to enter a low-power state when Ethernet is inactive
◆ UniClock technology utilizing a single 25 MHz crystal reduces BOM component cost and count
◆ Multiple operating systems support for diverse applications
◆ PME pin wake-up support reduces system power requirements
◆ Supports TCP segmentation offload and full hard-ware Tx/Rx which reduces loading
Microchip Technology2355 West Chandler Blvd.ChandlerAZ - Arizona85224United States480-792-7200888-MCU-MCHP480-792-7277here2help@microchip.comwww.microchip.com
sSubCatC
hips
CONTACT INFORMATION
20
engineers’ guide to USB
The Microchip name and logo the Microchip logo and IC are registered trademarks and Mi i is a trademark of Microchip Technology Incorporated in the U.S.A. and other countries. All other trademarks are the property of their registered owners. © 2015 Microchip Technology Inc. All rights reserved. 1/15DS000017 2B
Adding Connectivityto Your Design
www.microchip.com/connectivity
Microchip offers support for a variety of wired and wireless communication
protocols, including peripheral devices and solutions that are integrated with a
PIC® Microcontroller (MCU).
Wireless connectivity options include: Wi-Fi®, Bluetooth®, 802.15.4/ZigBee® and
our proprietary MiWi™ wireless networking protocol. Other connectivity protocols
supported include USB (device, host, OTG and hubs), Ethernet, CAN, LIN, IrDA®
and RS-485.
All of these protocols are supported with free software libraries, low-cost
development platforms and free samples.
August 201538
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www.generalstandards.com8302A Whitesburg Drive SE
Huntsville, AL 35802 PH: (800) 653-9970 PH: (256) 880-8787
Fax: (256) 880-8788 [email protected]
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