1. Draw the logic diagram of 74X74 IC and explain the operation.

A commonly desired function in D flip-flops is the ability to hold the last value stored, rather

than load a new value, at the clock edge. This is accomplished by adding an enable input,

called EN or CE (clock enable). While the name "clock enable" is descriptive, the extra

input's function is not obtained by controlling the clock in any way whatsoever If EN is

asserted, the external D input is selected; if EN is negated, the flip-flop's current output is

used.

5.Discuss the logic circuit of 74X377 register. Write a VHDL program using structural.

2. Design a 8 bit SISO shift register with flip flop . Write Data flow Program for it

A serial-in/serial-out shift register has a clock input, a data input, and a data output from

the last stage. In general, the other stage outputs are not available Otherwise, it would be a

serial-in, parallel-out shift register..

The waveforms below are applicable to either one of the preceding two versions of the

serial-in, serial-out shift register. The three pairs of arrows show that a three stage shift

register temporarily stores 8-bits of data and delays it by eight clock periods from input to

output.

At clock time t1 a “data in” of 0 is clocked from D to Q of all three stages. In

particular, D of stage 0 sees a logic 0, which is clocked to QA where it remains until time t2.

At clock time t2 a “data in” of 1 is clocked from D to Q0. At stages 1 and 2, a 0, fed from

preceding stages is clocked to Q1, Q2 and so on.

At clock time t3 a “data in” of 0 is clocked from D to Q0. Q0 goes low and stays low for the

remaining clocks due to “data in” being 0. QB goes high at t3 due to a 1 from the previous

stage. Q2 is still low after t3 due to a low from the previous stage.

Q2 finally goes high at clock t4 due to the high fed to D from the previous stage Q1. All

earlier stages have 0s shifted into them. And, after the next clock pulse at t5, all logic 1s

will have been shifted out, replaced by 0s and so on.

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity siso is

port(

din : in STD_LOGIC;

clk : in STD_LOGIC;

Q : BUFFER STD_LOGIC_VECTOR (7 downto 0)

);

end siso_behavior;

architecture siso_data_arc of siso is

begin

WAIT UNTIL clock ‘EVENT AND clock =’1’;

Q(7)=Q(6);

Q(6)=Q(5);

Q(5)=Q(4);

Q(4)=Q(3);

Q(3)=Q(2);

Q(2)=Q(1);

Q(1)=Q(0);

Q(0)=din;

end siso_data_arc;

3. Design a 8 bit PIPO shift register with flip flop and explain.

This type of shift register also acts as a temporary storage device or as a time delay device

similar to the SISO configuration above. The data is presented in a parallel format to the

parallel input pins PA to PD and then transferred together directly to their respective output

pins QA to QA by the same clock pulse. Then one clock pulse loads and unloads the register.

This arrangement for parallel loading and unloading is shown below.

The PIPO shift register is the simplest of the four configurations as it has only three

connections, the parallel input (PI) which determines what enters the flip-flop, the parallel

output (PO) and the sequencing clock signal (Clk).

Similar to the Serial-in to Serial-out shift register, this type of register also acts as a

temporary storage device or as a time delay device, with the amount of time delay being

varied by the frequency of the clock pulses. Also, in this type of register there are no

interconnections between the individual flip-flops since no serial shifting of the data is

required.

4. Design a 8 bit SIPO shift register with flip flop . explain its operation with timing

wave form.

A serial-in/parallel-out shift register is similar to the serial-in/ serial-out shift register in that it

shifts data into internal storage elements and shifts data out at the serial-out, data-out, pin. It

is different in that it makes all the internal stages available as outputs. Therefore, a serial-

in/parallel-out shift register converts data from serial format to parallel format. If four data

bits are shifted in by four clock pulses via a single wire at data-in, below, the data becomes

available simultaneously on the eight Outputs QA to QH after the fourth clock pulse.

The above details of the serial-in/parallel-out shift register are fairly simple. It looks like a

serial-in/ serial-out shift register with taps added to each stage output. Serial data shifts in

at SI (Serial Input). After a number of clocks equal to the number of stages, the first data

bit in appears at SO (QH) in the above figure. In general, there is no SO pin. The last stage

(QH above) serves as SO and is cascaded to the next package if it exists.

5. Design a 8 bit PISO shift register with flip flop . explain its operation with timing

wave form.

Parallel-in/ serial-out shift registers do everything that the previous serial-in/ serial-out shift

registers do plus input data to all stages simultaneously. The parallel-in/ serial-out shift

register stores data, shifts it on a clock by clock basis, and delays it by the number of stages

times the clock period. In addition, parallel-in/ serial-out really means that we can load data

in parallel into all stages before any shifting ever begins. This is a way to convert data from

a parallel format to a serial format. By parallel format we mean that the data bits are present

simultaneously on individual wires, one for each data bit as shown below. By serial format

we mean that the data bits are presented sequentially in time on a single wire or circuit as in

the case of the “data out” on the block diagram below

Below we take a close look at the internal details of a 8-stage parallel-in/ serial-out shift

register. A stage consists of a type D Flip-Flop for storage, and an AND-OR selector to

determine whether data will load in parallel, or shift stored data to the right. In general, these

elements will be replicated for the number of stages required

6. Draw logic diagram of 74x194 and explain the operation? Write VHDL code using

data flow.

entity Vshftreg is

port (

) ;

CLK, CLR, Dsr, Dsl: in STD_LOGIC;

S: in STD_LOGIC_VECTOR (2 down.to O); -- function select

D: in STD_LOGIC_VECTOR (3 down.to O); -- data in

Q: out STD_LOGIC_VECTOR (3 down.to 0) -- data out

end Vshftreg;

architecture Vshftreg_arch of Vshftreg is

signal IQ: STD_LOGIC_VECTOR (3 down.to O);

begin

process (CLK, CLR, IQ)

begin

if (CLR='l') then IQ<= (others=>'O'); -- Asynchronous clear

elsif (CLK'event and CLK='l') then

case CONV_INTEGER(S) is

when 0 => null; -----------------------------------------HOLD

when 1 => IQ <= Dsr & IQ(7 down.to 1); --------SHIFT RIGHT

when 2 => IQ <= IQ(2 down.to 0) & Dsl; --------SHIFT LEFT

when 3 => IQ <= D ------------------------------------LOAD(Parallel load)

when others=> null;

end case;

end if;

Q <= IQ;

end Vshftreg_arch;

7. Write VHDL code for 4bit up down counter with synchronous reset and clear inputs

8. Distinguish between synchronous and asynchronous counter

9. Design an 8 bit synchronous binary counter with serial enable control.

10. DESIGN 4 BIT BINARY SYNCHRONOUS COUNTER USNIG 74X74 AND

WRITE VHDL CODE.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity count is

port(rst,clk: in std_logic;

q: inout std_logic_vector (0 to 3));

end dff;

architecture data of count is

signal d: std_logic_vector(3 downto 0);

begin

if(clk='1' and clk' event) then

d0 <= not q0;

d1 <= q0 xor q1;

d2 <= Q2and notQ0 or Q2 and notQ1 or notQ2 and Q1 and Q0;

d3 <= Q3 and notQ2 + Q3 and notQ0 + Q3 and notQ1 + notQ3 and Q2 and Q1 and Q0;

end if;

q <= d;

end data

11. Design od 10 counter and write the VHDL CODE

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_signed.all;

entity counter is

port(CLK, CLR : in std_logic;

output : inout std_logic_vector(3 downto 0));

end counter;

architecture archi of counter is

signal tmp: std_logic_vector(3 downto 0);

begin

process (CLK, CLR)

variable i: integer:=0;

begin

if (CLR='1') then

tmp <= "0000";

elsif (clk = '1') then

for i in 0 to 9 loop

tmp <= tmp + 1;

end loop;

end if;

end process;

output <= tmp;

end architecture;

D-flipflop

Library ieee; use ieee. std_logic_1164.all; use ieee. std_logic_arith.all; use ieee. std_logic_unsigned.all;

entity D_FF is PORT( D,CLOCK: in std_logic; Q: out std_logic); End D_FF; Architecture behavioral of D_FF is begin process(CLOCK) begin if(CLOCK='1'andCLOCK'EVENT) then Q <= D; End if; End process; End behavioral;

D-latch:

Library ieee; use ieee. std_logic_1164.all;

use ieee. std_logic_arith.all; use ieee. std_logic_unsigned.all;

entity D_FF is PORT( D,en: in std_logic; Q: out std_logic); End D_FF; Architecture behavioral of D_FF is begin process(en) begin if(en='1') then Q <= D; End if; End process; End behavioral;

Follow the below given procedure to solve this problem and write a VHDL program for the simplified expressions.

Example

Follow the above given procedure to solve this problem and write a VHDL program for the simplified expressions.

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SRAM operation

An SRAM cell has three different states: standby (the circuit is idle), reading (the data has been requested) or writing (updating the contents). SRAM operating in read mode and write modes should have "readability" and "write stability", respectively. The three different states work as follows:

Standby

If the word line is not asserted, the access transistors M5 and M6 disconnect the cell from the bit lines. The two cross-coupled inverters formed by M1 – M4 will continue to reinforce each other as long as they are connected to the supply.

Reading

In theory, reading only requires asserting the word line WL and reading the SRAM cell state by a single access transistor and bit line, e.g. M6, BL. However, bit lines are relatively long and have large parasitic capacitance. To speed up reading, a more complex process is used in practice:

The read cycle is started by precharging both bit lines BL and BL, i.e., driving the bit lines to a threshold voltage (midrange voltage between logical 1 and 0) by an external module (not shown in the figures). Then asserting the word line WL enables both the access transistors M5 and M6, which causes the bit line BL voltage to either slightly drop (bottom NMOS transistor M3 is ON and top PMOS transistor M4 is off) or rise (top PMOS transistor M4 is on). If the BL voltage rises, the BL voltage drops, and vice versa. Then the BL and BL lines will have a small voltage difference between them. A sense amplifier will sense which line has the higher voltage and thus determine whether there was 1 or 0 stored. The higher the sensitivity of the sense amplifier, the faster the read operation.

Writing

The write cycle begins by applying the value to be written to the bit lines. If we wish to write a 0, we would apply a 0 to the bit lines, i.e. setting BL to 1 and BL to 0. This is similar to applying a reset pulse to an SR-latch, which causes the flip flop to change state. A 1 is written by inverting the values of the bit lines. WL is then asserted and the value that is to be stored is latched in. This works because the bit line input-drivers are designed to be much stronger than the relatively weak transistors in the cell itself so they can easily override the previous state of the cross-coupled inverters. In practice, access NMOS transistors M5 and M6 have to be stronger than either bottom NMOS (M1, M3) or top PMOS (M2, M4) transistors. This is easily obtained as PMOS transistors are much weaker than NMOS when same sized. Consequently, when one transistor pair (e.g. M3 and M4) is only slightly overridden by the write process, the opposite transistors pair (M1 and M2) gate voltage is also changed. This means that the M1 and M2 transistors can be easier overridden, and so on. Thus, cross-coupled inverters magnify the writing process.

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