1 - 1

DRAMs

Undoubtedly the most interesting development for us during the past year was the scarcity of

64 Mb parts and the continued upgrading of 16 Mb devices. In fact, as mentioned in the

general overview, we've found out that fourth generation 16 Mb devices are now being

implemented.

We analyzed only two 64 Mb devices, the Mitsubishi and Hitachi parts (but Mitsubishi would

not allow publication). Samsung although again supposedly the first available obviously did

not produce enough to get parts to more than a few users. As a matter of interest, die and cell

sizes so far reported are:

Die Size Cell Size

Hitachi 230mm2 1.6 micron2

Mitsubishi 217mm2 1.6 micron2

Micron 175mm2 1.5 micron2

NEC 162mm2 ?

Fujitsu 232mm2 ?

Minimum feature sizes for all are approximately 0.35 micron (except for some 0.25 micron

poly). It will be interesting to see what happens in 1995.

We did get a look at the most advanced 16 Mb devices including two that had small enough die

sizes to allow assembly in 300 mil packages and one with a cell size below 3 microns2.

Significant variations in processes are represented in the devices reported on here. This

typically was in the juggling of types of interconnect. For example, Hitachi's 64 Mb device

used only one aluminum layer and three tungsten layers (counting the tungsten under

aluminum), used no polycides, and employed poly plugs instead of the much more common

tungsten plugs. On their latest 16 Mb part they used a polycide instead of one of the tungsten

layers, and no plugs at all.

Samsung's 16 Mb device retained the aluminum reflow technique while Hyundai remained the

most traditional with two aluminum and one polycide layer.

1 - 2

Capacitor structures were all in the form of stacked cells and the three most advanced designs

all used finned capacitors.

Cell sizes varied from 1.6 micron2 to 4.0 microns2 and minimum gate lengths were 0.35

micron.

Indications from mask revision markings on the die are that the 64 Mb parts use about thirty mask

levels!

*Polycide †Physical gate length +Plugs TABLE 1 - 1

HORIZONTAL DIMENSIONS (DESIGN RULES)

DRAMs HitachiHM51W64800J-764Mb 9351

HitachiHM51W17400ALTS-716Mb (3.3V) 9419

HyundaiHY5117400JC-7016Mb 9442

SamsungKM44C4100AJ-716Mb 9435

Die size 11.3 x 20.32

6.5 x 15 mm2

7.5 x 16.5 mm2

6.1 x 15.0 mm2

Min M3 width 0.4µm NA NA NA

Min M2 width 0.4µm 0.7µm 1.0µm 1.1µm

Min M1 width 0.3µm 0.6µm 0.55µm 0.45µm

Min M3 space 0.5µm NA NA NA

Min M2 space 0.5µm 0.6µm 1.0µm 1.1µm

Min M1 space 0.45µm 0.8µm 0.7µm 0.75µm

Min via (Met. to Met.) 0.7µm 0.6µm 0.9µm 1.0µm

Min cntct (Met. to Si) 0.7µm+ 0.6µm+ 0.9µm 0.65µm

Min Poly 4 NA 0.5µm* >5µm 0.6µm*

Min Poly 3 0.6µm 1.4µm 1.0µm 1.0µm

Min Poly 2 0.8µm 1.0µm 0.4µm* 1.4µm

Min Poly 1 0.25µm 0.45µm* 0.4µm 0.25µm

Min gate - (N)† 0.35µm 0.5µm 0.5µm 0.45µm

Min gate - (P)† 0.55µm 0.5µm 0.9µm 0.6µm

Cell pitch 0.9 x 1.8µm 1.2 x 2.7µm 1.4 x 2.7µm 1.1 x 2.5µm

Cell area 1.6µm2 3.2µm2 4.0µm2 2.75µm2

*Polycide TABLE 1 - 2

VERTICAL DIMENSIONS

DRAMs HitachiHM51W64800J-764Mb 9351

HitachiHM51W17400ALTS-716Mb (3.3V) 9419

HyundaiHY5117400JC-7016Mb 9442

SamsungKM44C4100AJ-716Mb 9435

Final passivation 2µm 1.9µm 0.7µm 1.0µm

Metal 3 0.65µm NA NA NA

Metal 2 0.3µm 1.0µm 1.0µm 0.9µm

Metal 1 0.3µm 0.4µm 0.65µm 0.75µm

Intermetal dielectric 0.5µm 0.7µm 1.0µm 0.9µm

Poly 4 NA 0.25µm* 0.1µm 0.25µm*

Poly 3 0.06µm 0.1µm 0.05 to 0.3µm 0.1µm

Poly 2 0.07µm 0.1µm 0.3µm* 0.1 to 0.2µm

Poly 1 0.15µm 0.1µm* 0.25µm 0.15µm

Recessed oxide 0.35µm 0.3µm 0.35µm 0.35µm

N-well 8.5µm 8µm 4.5µm 3µm

P-well 6.5µm 6µm NA 2.5µm

Epi None None None None

TABLE 1 - 3

DIE MATERIALS

DRAMs HitachiHM51W64800J-764Mb 9351

HitachiHM51W17400ALTS-716Mb (3.3V) 9419

HyundaiHY5117400JC-7016Mb 9442

SamsungKM44C4100AJ-716Mb 9435

Final passivation Nitride on glass Nitride on glass Nitride on glass Nitride on glass

Metal 3 AluminumTungsten

NA NA NA

Metal 2 Tungsten Titanium-tungstenAluminumTitanium-tungsten

Titanium-nitrideAluminum

Aluminum

Metal 1 Tungsten Tungsten Titanium-nitrideAluminumTitanium-nitride

Titanium-nitrideAluminumTitanium-nitrideTitanium

Plugs Poly (see text) NA NA NA (aluminum reflow)

Intermetal dielectric Glass Glass Glass Glass

Reflow glass BPSG BPSG BPSG BPSG

Polycide metal NA Tungsten Tungsten Tungsten

1 - 3

TECHNOLOGY DESCRIPTION

HITACHI/T.I. HM51W64800J-764 Mbit CMOS DRAM

Introduction Ref. report SUB 9407-04

These parts were packaged in 34-pin, plastic SOJ packages date coded week 51 of 1993. Theywere reported to be fully functional production parts and were not marked as engineering samples.Memory organization was 8 M words x 8 bits and includes a fast-page mode. The devices operatefrom a 3.3V power source. These parts were fabbed by Hitachi not T.I.

See tables for specific dimensions and materials identification and see figures for examples ofphysical structures.

Unusual/Unique Features

- Very aggressive feature sizes.

- Unique finned-capacitor memory cell structure.

- Poly plugs at contacts in cell array.

Quality

Quality of process implementation was normal. Metal 3 step coverage at via contacts showedsignificant thinning of the aluminum, but solid contact was maintained by the titanium-tungstenbarrier.

In the area of layer patterning, etch definition and control (depth) were normal.

Alignment/registration was good.

Packaging/assembly quality was good.

Technology

These devices were made by a twin (multiple)-well CMOS process, employing a P substrate. Noevidence of an epi layer was detected. Three levels of metal and three levels of polysilicon wereemployed (no polycides). A recessed-oxide isolation with fairly short birdsbeaks was used.

1 - 4

Final passivation consisted of a thick layer of nitride over two layers of glass. Metal 3 wasaluminum on a thick titanium-tungsten, while both metals 1 and 2 were tungsten only. The use oftungsten by itself as a metal interconnect is unusual in general, but not for Hitachi and T.I.

Standard vias and contacts (no plugs) were employed everywhere except in the array where polyplugs were used (see below).

Planarization of the intermetal dielectric was by deposited glass and planarizing etch. It included aSpin-On-Glass (SOG). The dielectric under metal 1 was planarized by a reflow process. Thiswas probably done twice, once before poly 2 deposition, and once before metal 1 deposition. Noevidence of chemical-mechanical planarization (CMP) was present.

All gates were made with poly 1 and all used oxide sidewall spacers that were left in place. Nosilicide metallization treatment (salicide process) was employed on diffusions. Poly 2 and 3 wereused only in the cell array area.

Direct (buried) contacts were employed between poly 2 and N+ only (in the cell array).

No evidence of special gate oxide materials was present but capacitor dielectric material may havebeen tantalum-pentoxide as it did not appear to be a standard oxide-nitride combination.

The most unique features found were the memory cell capacitor design and the use of poly plugsat contacts in the array (see below).

Overall minimum feature measured anywhere on these dice was the 0.25 micron poly 1 width.This is equal to the minimum width of any lines seen in 1994 (see Samsung 16 Mb DRAM).

Minimum physical gate lengths measured were 0.35 micron for N-channel and 0.55 micron forP-channel. The 0.35 micron length is just barely longer than the absolute minimum we saw in1994 (0.3 micron on the NEC VR4400MC).

Memory Cell Structures

These parts used a stacked cell implemented in a fairly standard design except for the capacitorstructure itself (see figures). In this design the individual poly 2 capacitors had three fins stackedvertically. These were completely surrounded by the poly 3 (common capacitor plate) thusproviding a relatively large surface (capacitor) area. The capacitor dielectric may have been atantalum-pentoxide as mentioned above since Hitachi has published articles referring to its use.

Except for this, the design was really quite standard.

The individual poly 2 capacitor plates were connected to the drains of the select transistors by direct(buried) contacts in the normal manner. Poly 3 in the form of a sheet provided the common

1 - 5

capacitor plate. Metal 1 provided the bit lines using deep poly plugs to reach the N+ sources of theselect gates. These plugs were used only in the cell array area and are obviously employed becausethe height of the capacitor structures creates a very high step between metal 1 and substrate. Thestandard contact structures used elsewhere could probably not be used, although why poly insteadof tungsten plugs were chosen was surprising considering the extensive use of tungsten in theprocess.

The resulting cell size was a very aggressive 1.6 microns2, the smallest we've seen to date.

Packaging/Assembly

Devices were packaged in standard 400 mil, 34-pin, plastic, SOJ packages using the Lead On ChipCenter Bond (LOCCB) internal design. Pins 6, 10, and 26 were not connected. Internally theleadframe was spot-plated with silver, while external leads were plated with lead-tin solder. Dieattach was by doublebacked adhesive Kapton-type tape to the top of the die. Standard thermosonicwirebonds using gold wire were used.

A patterned (to clear bond pads) polyimide type die coat was used to provide protection againstalpha particle induced leakage and against packaging induced stresses.

Portion of the Hitachi HM51W64800J7 64 Mb DRAM circuit die. Mag. 16x.

®®

Remaining portion of the Hitachi HM51W64800J7 64 Mb DRAM circuit die.Mag. 16x.

®

Hitachi HM51W64800J-7. SEM views illustrating device structures.

section,Mag. 20,000x

Mag. 10,000x, 60°

Mag. 25,000x, 60°

®

POLY 2OXIDE

METAL 2

METAL 1

POLY 1

POLY PLUG

POLY 1

METAL 1

METAL 2

Hitachi HM51W64800J-7. SEM views of the cell area.

Mag. 24,000x, 0°

Mag. 25,000x, 60°

section,Mag. 40,000x

®

BIT LINECONTACT

(POLY PLUG)

POLY 2

METAL 1BIT LINE

POLY 1SELECT GATE

CAPACITORDIELECTRIC

Hitachi HM51W64800J-7. Cross section drawing illustrating cell array structure.

Orange = Nitride, Blue = Metal, Yellow = Oxide, Green = Poly,Red = Diffusion, and Gray = Substrate

®

����������������������

POLY 1

POLY PLUG

METAL 1

CAPACITOR DIELECTRIC

POLY 2

INTERPOLY DIELECTRICPOLY 3

INTERLEVEL DIELECTRIC LAYERS

BARRIER

ALUMINUM 3

PASSIVATION 1

PASSIVATION 2

PASSIVATION 3

P SUBSTRATE

P-WELL

N+ S/D

1 - 6

TECHNOLOGY DESCRIPTION

HITACHI HM51W17400ALTS-716 Mbit (3.3V) CMOS DRAM

Introduction Ref. report SCA 9409-350

These parts were packaged in 300 mil wide, 26-pin format (24-pin), plastic TSOP packages datecoded week 19 of 1994. They were fully functional production parts. Memory organization was4 M words x 4 bits and included a fast-page mode. These devices operate from a 3.3V powersource and they use memory cell structures similar to the 64 Mb device made by thismanufacturer. They were the first 16 Mb parts in 300 mil packages we analyzed in 1994.

See tables for specific dimensions and materials identification and see figures for examples ofphysical structures.

Unusual/Unique Features

- Technology appeared to be a transition step to that used for 64 Mb devices.

Quality

Quality of process implementation was normal except for a very high degree of metal 2 thinning.Only a very thin film of the tungsten barrier maintained contact.

In the area of layer patterning, etch definition was good and control (depth) was normal. Noevidence of significant overetching was found.

Alignment/registration was good.

Packaging/assembly quality was normal. The packages used the LOCCB package design.

Technology

These devices were made by a twin (multiple)-well CMOS process, employing a P substrate. Noevidence of an epi layer was detected. Two levels of metal and four levels of polysilicon, one ofwhich used a tungsten silicide (polycide), were employed. A recessed-oxide isolation with shortbirdsbeaks was used.

Final passivation was similar to that used on the 64 Mb part - thick nitride over two layers of glass.

1 - 7

Metal 2 consisted of aluminum with titanium-tungsten cap and barrier layers. Metal one wastungsten only. We could detect no evidence of an adhesion layer under either metal.Polycide 4 was used as a metal substitute in place of the extra metal layer used on the 64M device.

Metal 2 to metal 1 vias and metal to silicon contacts were standard. No plugs were used in theperiphery or memory array. Metal 2 contacted metal 1 and polycide 4. Metal 1 contacted polycide4, poly 1, and both N+ and P+ diffusions. Polycide 4 made contact to N+ diffusions in both theperiphery and memory array.

Planarization of the intermetal dielectric was by deposited glass and planarizing etch. It included aSpin-On-Glass (SOG). The dielectric under metal 1 was planarized by a reflow process. Thedielectric under polycide 4 was also planarized by reflow and capped with a thin layer of depositedundoped glass before polycide deposition. In the memory array area this material is as flat as ifchemical-mechanical planarization (CMP) was used, but in the periphery topology variations werepresent.

All gates were made with poly 1 and all used oxide sidewall spacers that were left in place. Nosilicide metallization treatment (salicide process) was employed on diffusions. Poly 2 and poly 3were only used for memory cells in the array.

Direct (buried) contacts were employed between poly 2 and N+, and between polycide 4 and N+.

No evidence of special gate oxide materials was found, but in this case also, tantalum-pentoxidemay have been used as a capacitor dielectric.

The most unique feature of this product is the level of technology used. It appears to be either aprototype 64 Mb technology or an adaptation of the 64 Mb technology for use on 16 Mb devices.The major differences are that these 16 Mb parts do not use plugs at all, use a polycide as a pseudometal 1 (instead of tungsten on the 64 Mb) and use cell capacitors that are larger in areahorizontally but have only two fins instead of the three fins present on the 64 Mb part.

Overall minimum feature measured anywhere on these dice was the 0.45 micron poly 1 width.

Minimum physical gate lengths measured were 0.5 micron for both N-channel and P-channel.

Memory Cell Structures

These parts used a stacked cell design implemented in a similar way to that used on the 64 Mbdevices.

In this design the poly 2 individual capacitor plates had two fins stacked vertically. These werecompletely surrounded by the poly 3 common plate thus providing a relatively large surface

1 - 8

(capacitor) area. The capacitor dielectric may have been a tantalum-pentoxide (TaO5) since Hitachihas published articles referring to its use.

The individual poly 2 plates were connected to the drains of the select transistors by direct (buried)contacts in the normal manner. Polycide 4 provided the bit lines using standard (buried) contactsto reach the N+ sources of the select gates. (These connections use poly plugs in the 64 Mb parts).

Resulting cell size was 3.2 microns2, twice the size of the 64 Mb.

Packaging/Assembly

Devices were packaged in 300 mil, 26-pin format (24-pin) plastic, TSOP packages using theLOCCB internal design. These were the first 16 Mb DRAMs in 300 mil packages we saw in1994. Internally the iron-nickel leadframe was spot-plated with silver, while external leads wereplated with lead-tin solder. Die attach was by doublebacked adhesive Kapton type-tape to the topof the die. Standard thermosonic wirebonds using gold wire were used.

A patterned (to clear bond pads) polyimide type die coat was used to provide protection againstalpha particle induced leakage and against packaging induced stresses.

Mag. 5000x, 60°

section, Mag. 20,000x

Hitachi HM51W17400ALTS-7 16Mb DRAM. SEM views illustratingdevice structures.

®

SOG

GLASS

OXIDE

METAL 1

Hitachi HM51W17400ALTS-7. Topological SEM views of cell area.

Mag. 17,000x, 0°

Mag. 17,000x, 0°

Mag. 10,000x, 60°

®

POLYCIDE BIT LINE

POLY 3 SHEET(MEMORY ENABLE)

BIT CONTACT

POLY 2(UNDER POLY 3)

BIT CONTACT

POLY SHEETPOLY 2 CAPACITOR PLATES (UNDER POLY 3)

Hitachi HM51W17400ALTS-7. SEM section views of the cell area.

section (X),Mag. 10,000x

section (X),Mag. 30,000x

section (Y),Mag. 16,000x

®

POLY 3SHEET

POLY 2CAPACITOR PLATES POLY 1 SELECT GATE

REFLOW GLASS

CAPACITORDIELECTRIC

POLY 1 SELECT GATE

METAL 2

METAL 1

POLYCIDE BIT LINE

POLY 1SELECT GATE OXIDE

POLY 2

POLYCIDE BIT LINE

1 - 9

TECHNOLOGY DESCRIPTION

HYUNDAI HY5117400JC-7016 Mbit CMOS DRAM

Introduction Ref. report SCA 9503-399

These parts were packaged in 28-pin format (24-pin), plastic SOJ packages date coded week 42of 1994. They were fully functional parts. Memory organization was 4 M words x 4 bits andincluded a fast-page mode. These devices operate from a standard 5V power source. Theyrepresent the first version of this product from Hyundai evaluated by ICE.

See tables for specific dimensions and materials identification and see figures for examples ofphysical structures.

Unusual/Unique Features

- None.

Quality

Quality of process implementation was normal except for metal 1 step coverage which showedsignificant lack of control.

In the area of layer patterning, etch definition was good and control (depth) was normal. Noevidence of significant overetching was found.

Alignment/registration was good.

Packaging/assembly quality was normal.

Technology

These devices were made by an N-well CMOS process, employing a P substrate. No evidence ofa P-well was found, but that does not eliminate the possibility of its existence (e.g., the memoryarray). No epi layer was detected. Two levels of metal and four levels of polysilicon, one ofwhich used a tungsten silicide (polycide), were employed. A standard recessed-oxide isolationwas used and showed no serious attempts to shorten birdsbeak areas.

Both metal levels consisted of aluminum. Metal 2 had a cap of titanium-nitride (no barrier) whilemetal 1 had a titanium-nitride cap and barrier on a thin titanium adhesion layer. Polycide 2 wasused as a metal substitute, both in the cell array and peripheral circuitry.

1 - 10

All vias and contacts were standard, no plugs were used anywhere.

Planarization of the intermetal dielectric was by deposited glass. It included a Spin-On-Glass(SOG). Under metal 1, there were at least three layers of reflow glass, separated by an undopeddeposited glass. They were located respectively: under poly 2 (polycide); under poly 3 (cellcapacitor plate); and under metal 1.

No evidence of chemo-mechanical planarization (CMP) was present.

All gates were made with poly 1 and all used oxide sidewall spacers that were left in place. Nosilicide metallization treatment (salicide process) was employed on diffusions. Polycide 2 wasused as a metal substitute to provide interconnects (primarily bit lines in the memory), and poly 3and 4 were used for the capacitors in the cell array only.

Direct (buried) contacts were employed between polycide 2 and N+, between polycide 2 and poly1, and between the poly 3 capacitor-plates and N+.

No evidence of special gate oxide materials was found, but here also a new capacitor dielectricmaterial such as tantalum-pentoxide may have been used.

Overall minimum feature measured anywhere on these dice was the 0.4 micron poly 1 andpolycide 2 width.

Minimum physical gate lengths measured were 0.5 micron for N-channel and 0.9 micron forP-channel.

Memory Cell Structures

These parts used a stacked cell design, implemented in a slightly unusual way.

The active plate of the cell capacitor (poly 3) was thick on top, but thin at the vertical step createdby the buried contact to the N+ drain of the select gate. This allowed the poly 4 to drop down intothe remaining "well" in the poly 3, providing significant added capacitor area at these points. Inaddition, the thick horizontal layer of poly 3 at the top created high edges at its perimeter which,being covered by poly 4, also added significant area. A rough calculation indicated the totalcapacitance provided by the vertical components to be about 50 percent larger than that provided bythe horizontal area (approximately 3 micron2 out of 5 microns2). No attempt was made to etchunder poly 3 so as to fill this with poly 4 to obtain additional capacitor area as is done by somemanufacturers. The poly 3 plates were connected to the drains of the select transistors by direct(buried) contacts in the normal manner. Poly 2 (polycide) was used as a metal substitute andprovided the bit lines (under the capacitor structures) while poly 1 was used for all the gates.

1 - 11

Capacitor dielectric appeared to be unusual although we say this with considerable caution. Etchcharacteristics usually allow us to determine if a standard oxide-nitride combination is used. Inthis case, we were unable to find enough oxide to allow this delineation. We thus speculate that adifferent material such as tantalum-pentoxide (TaO5) may have been used.

Memory cell size was measured to be 4 microns2, not particularly aggressive.

Packaging/Assembly

Devices were packaged in standard 400 mil, 28-pin format (24-pin) plastic, SOJ packages. Allpins except pin 6 were connected. Internally the leadframe was spot-plated with silver, whileexternal leads were plated with lead-tin solder. The die paddle/header was dimpled and had a largecutout in the center. Die attach was by a silver-epoxy. Standard thermosonic wirebonds usinggold wire were used.

No evidence of a die coat was found.

Portion of the Hyundai HY5117400JC-70 16Mb DRAM circuit die. Mag. 23x.

®

Remaining portion of the Hyundai HY5117400JC-70 16Mb DRAM circuit die.Mag. 23x.

®

Hyundai HY5117400JC-70. SEM views illustrating device structures.

section,Mag. 6500x

Mag. 5000x, 60°

section,Mag. 40,000x

®

POLY 1 POLY 1

OXIDE

POLYCIDE 2

PASSIVATION

POLYCIDE 2

POLY 1

GATE

POLY 1GATE

METAL 1

GATE OXIDE

Hyundai HY5117400JC-70. SEM views of the cell area.

Mag. 10,000x, 0°

Mag. 10,000x, 0°

section,Mag. 13,000x

®

POLY 3 CAPACITORPLATES

POLYCIDE 2 BIT LINE

POLY 3 CAPACITOR CONTACT

POLY 1 WORD LINE

WORD(POLY 1)

1 - 12

TECHNOLOGY DESCRIPTION

SAMSUNG KM44C4100AJ-716 Mbit CMOS DRAM

Introduction Ref. report SCA 9503-397

These parts were packaged in standard 400 mil, 28-pin format (24-pin), plastic SOJ packagesdate coded week 35 of 1994. They were fully functional production samples. Memoryorganization was 4 M words x 4 bits and included a fast-page mode. They operate from astandard 5V power source and were the latest 16 Mb parts from Samsung evaluated by ICE.

See tables for specific dimensions and materials identification and see figures for examples ofphysical structures.

Unusual/Unique Features

- Smallest 16 Mb cell size (2.75 microns2).

- Die small enough to fit a 300 mil package.

- Aluminum reflow in contacts.

Quality

Quality of process implementation was normal. Metal 2 exhibited some significant thinning, butdid not appear to be dangerous.

In the area of layer patterning, both etch definition and control (depth) were good. No evidence ofoveretching, or poor definition was found.

Alignment/registration was also good.

Packaging/assembly quality was normal.

Technology

These devices were made by a twin (multiple)-well CMOS process, employing a P substrate. Noepi was detected. Two levels of metal, one level of polycide (tungsten on polysilicon) and threelevels of polysilicon were employed. A standard recessed oxide isolation was used.

1 - 13

Metal 2 consisted of aluminum and did not make use of either a cap or barrier layer. Metal 1 wasalso aluminum and used a titanium-nitride cap and a titanium-nitride on titanium barrier.

Planarization of the intermetal dielectric was by deposited glass. It included a Spin-On-Glass(SOG), but no evidence of a planarizing etch was found. The dielectric under metal 1 wasplanarized by a standard reflow process as was the dielectric under the polycide 4 metal substitute.No evidence of chemo-mechanical planarization (CMP) was present.

No plugs were used at vias or contacts, instead metal 2 to metal 1 connections employed standardvia contacts (except that they were square), while contacts between metal 1 and silicon usedaluminum reflow to completely fill the contact holes. This is a process we've only seen used bySamsung. It results in absolute elimination of step coverage problems at these contacts and yetappears to be less complex than tungsten plugs used by some manufacturers.

All gates were made with poly 1 and all used oxide sidewall spacers that were left in place. Nosilicide metallization treatment (salicide process) was employed on diffusions.

Poly 4 (polycide) was used as a metal substitute to provide interconnects, primarily bit lines in thememory, but also interconnect in peripheral circuits.

Direct (buried) contacts were employed between poly 4 (polycide) and poly 1, and N+. Alsobetween the poly 2 capacitor-plates and N+.

No evidence of special gate oxide materials was found but capacitor dielectric material may havebeen special (see below).

Overall minimum features measured on these dice were the 0.25 micron poly 1 word lines (notgates) which equaled the smallest we've seen (see Hitachi 64 Mb DRAM).

Minimum physical gate lengths measured were 0.45 micron for N-channel and 0.6 micron forP-channel.

Note: As mentioned, these dice were narrow enough to fit in 300 mil wide packages and in fact,these devices were the smallest 16 Mb dice analyzed in 1994.

Memory Cell Structures

These parts used a stacked cell design implemented in a special new way (for Samsung).

The active plate of the cell capacitor (poly 2) basically has two fins, the top one of which was inlarge part "surrounded" by the passive plate (poly 3), on top and bottom. This is a newmodification on the previous version of this product (date code 9313) which only had one poly 2

1 - 14

layer. This new change makes this capacitor design very similar to the Hitachi 16 Mb DRAMalthough Hitachi surrounds the top fin much more than Samsung does.

As usual, the poly 2 makes direct contact to the N+ drains of the select-gates, and poly 3 in theform of a sheet (with cutouts for bit connects) is tied to a reference voltage. Poly 4 (polycide)provided the bit lines, and as mentioned, had a reflow glass both below and above it as the onlyplanarization method detected under metal 1.

Poly 1 formed the word lines and select gates.

Capacitor dielectric may have been an extremely thin Oxide-Nitride-Oxide (ONO) or Oxide-Nitride (ON) layer, or something else (tantalum pentoxide?). We could not clearly delineate anitride layer.

Cell size was measured to be 2.75 microns2. This is the smallest 16 Mb cell we've seen.

Packaging/Assembly

Devices were packaged in standard 400 mil, 28-pin format (24-pin) plastic, SOJ packages. Allpins were connected and a wirebond was made from die to header/paddle. Internally the iron-nickel leadframe was spot-plated with silver, while external leads were plated with lead-tin solder.Die attach was by a silver-epoxy and standard thermosonic wirebonds using gold wire were used.

No die coat was detected.

Samsung KM44C4100AJ-7 16Mb DRAM. SEM views illustrating device structures.

section,Mag. 8400x

section,Mag. 40,000x

section,Mag. 10,000x

®

METAL 1CONTACT

OXIDE

REFLOWGLASS

POLY GATE

GATE OXIDE

SOGVIA

POLYCIDECONTACT

Samsung KM44C4100AJ-7. SEM views of the cell area.

Mag. 10,000x, 0°

Mag. 10,000x, 0°

section,Mag. 35,000x

®

POLYCIDE BIT LINE

POLY 3 OVER POLY 2

BIT CONTACT

POLY 2(UNDER POLY 3)

POLY 1 SELECT GATE

N+ S/D N+

OXIDE

POLY 1