DRAM Pricing Trends—The IT Rule M. P. Lepselter and S. M. Sze

Since the introduction of one-kilobit dynamic ran­dom-access memory chips (IK DRAM) in 1971, semi­conductor memories have had an explosive growth and have virtually supplanted core memories [1]. The advantages of semiconductor memories include their high density, fast access time, and high reliability. However, the key factor for the rapid growth of the semiconductor-memory industry is the low cost of packaged memory chips. We have monitored the pric­ing trends of DRAM chips in the past 14 years and observed a surprisingly regular behavior in the rate of price reduction and in the time interval of introduc­ing a new DRAM with a 4:1 density improvement.

The illustration shows the average price of pack­aged DRAM chips as a function of time in the past 14 years (solid curves) [2,3]. We notice that the initial high price of a new DRAM declines rapidly with a rate |dP/dr| much larger than $l/year, where Ρ is the average price per packaged DRAM chip in dollars and t is the time in years. The rate approches $l/year at a price level of about $3. This price level is of critical importance because it corresponds to the peak vol­ume of DRAM shipment as well as the maximum re­

turn on investment of the DRAM project [4]. We shall designate this important price level the π level [5] be­cause the transcendental number ττ has a value fairly close to 3. Beyond the IT level, the price continues to decline and eventually settles at a level correspond­ing to about one-half the price at the ττ level, i.e., $π/2. The state-of-the-art large-volume DRAM is the 64K chip. The price of 64K DRAMs is now at the $ττ range, plus or minus 30% depending on memory access time, quantity of purchase, and package specifications.

We also note from the illustration that the time in­terval between successive generations of DRAMs is almost a constant—three to four years. Therefore, there is a fairly narrow window for a semiconductor-memory manufacturer to design, fabricate, and mar­ket each new generation of DRAMs.

Based on the trends in the past 14 years, we project the pricing behavior of DRAMs for the next 14 years. They are also illustrated in the figure below (dashed curves). The critical ττ level will be reached in 1988 for 256K, in 1991 for 1M, in 1995 for 4M, and around year 2000 for 16M DRAMs. The cost per bit of memory

JANUARY 1985 8755-3996/85/0100-0053$01.00 © 1985 IEEE 53

chips will be halved every two years. By 1990, the cost per bit is expected to be about 1 millicent (10~5 dollar), and by 2000, the cost per bit may drop to 10 microcent (ΙΟ"7 dollar).

For successive generations of DRAMs, the device dimensions must be scaled down [6]. If the present trends of chip design continue [7,8], we expect that the minimum feature length of the 16M DRAM will be the order of 0.2 μιη, with a chip size of the order of 100 mm2. Since MOSFETs with feature lengths as small as 0.15 μιη have been fabricated with good de­vice characteristics, we do not have to contend with the fundamental limit of VLSI technology [9] even at the 16M DRAM level.

The illustration may also be used as a reference for the pricing trends of static random-access memories (SRAM). A SRAM with a given number of bits is ap­proximately four times more complex than a DRAM having the same number of bits. Therefore, for SRAMs, the pricing curves will be shifted by one gen­eration. For example, the curve for 64K DRAM corre­sponds to the curve for 16K SRAM.

If the future pricing of DRAMs and other VLSI chips follows the projected trends as shown in the illustration, an IC manufacturer must allocate suffi­cient resources in this endeavor so that he will not miss the pricing windows. On the other hand, an IC user may anticipate the availability of new ICs at com­petitive prices so that he can optimize the overall sys­tem cost.

References [1] The Semiconductor Memory Book, New York: Wiley Interscience,

1978. [2] R. N. Noyce, "Microelectronics," in Microelectronics, San Fran­

cisco: W. H. Freeman, 1977. [3] R. Bambrick, "64K DRAM Prices Quoted Under $2," Electronic

News, vol. 30, no. 1517, Oct. 1, 1984. [4] "World Dynamic RAM Market," Electronic News, vol. 30, no.

1513, Sept. 3, 1984. [5] M. P. Lepselter, "Submicron Si Technology, Present, Future

and Impacts on Electronic Age," International Conference on Solid-State Devices and Materials, Kobe, 1984.

[6] For a discussion on DRAM processing and related VLSI fab­rication technology, see for example, S. M. Sze, Ed., VLSI Technology, New York: McGraw-Hill, 1983.

[7] C. A. Benerit, et al., "256K Dynamic Random Access Mem­ory," Digest of IEEE International Solid-State Circuits Conference, p. 76, 1982.

[8] S. Suzuki, et al., "A 128 World x8b DRAM," Digest of IEEE International Solid-State Circuit Conference, p. 106, 1984.

[9] M. P. Lepselter, et al., "A System Approach to 1 - μπ\ NMOS," Proc. IEEE, vol. 71, no. 640, 1983.

M. P. Lepselter and S. M. Sze are with AT&T Bell Laboratories, Murray Hill, N. J. Both authors are members of the IEEE.

The University of Louisville

28TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS

August 19-20,1985 The Gait House

Louisville, Kentucky

CALL FOR PAPERS

The 1985 Midwest Symposium will be devoted to all facets of the theory, design, and applications of circuits and systems. A partial list of topics of interest is:

• Analog/Digital Signal Processing

• Communications and

Modulation Systems

• Digital Systems Design

• Large Scale Networks

• Network and Filter

Theory

• Optical Systems

• Robotics • System Theory

• Analog/Digital Fault Diagnosis

• Computer-Aided Analysis

and Design

• Graph Theory

• Microwave Circuits

• Nonlinear Circuit

Theory

• Power Systems

• Switched Capacitor Systems

• VLSI Circuits

Prospective authors are invited to submit three copies of a summary limited to 300 words and headed by the title, authors' names, addresses, affiliations, and telephone numbers, as well as a brief biography, limited to approximately 100 words, to:

Dr. Joseph D. Cole Dept. of Electrical Engineering

University of Louisville Louisville, Kentucky 40292

Paper summaries must be received by April 2,1985. Notification of acceptance and authors' kits will be sent by May 15. Proposals for special sessions, short courses, and tutorials are solicited. These may be submitted to:

Dr. W. Lee Ko Dept. of Electrical Engineering

University of Louisville Louisville, Kentucky 40292

54 IEEE CIRCUITS AND DEVICES MAGAZINE