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Section 4: Component Section 4: Component Interfacing (I/O) Interfacing (I/O)

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Section 4: Component Interfacing Section 4: Component Interfacing (I/O) (I/O)

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Embedded Real-Time Systems 2

OutlineOutline

• Interface Timing

• Synchronous vs. Asynchronous Interface

• Polling, Interrupts, and DMA

• Busses

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Interface TimingInterface Timing

• Two types of CPU-Component interfacing– Memory Interface: Read/Write– Peripheral Interface: Memory-Mapped I/O or Separate I/O

• Modeling– Timing Diagram and Parameter Table– Protocol Flowchart

• Challenges in interface design– Fixed external behavior of off-the-shelf components

• Synchronous/Asynchronous/Semi-Synchronous• Limited availability of control pins, speed requirement, etc.

– Min/max timing separations– Inter-Operational Compatibility– Optimization for area, delay, and power consumption

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Interface Timing (cont’d)Interface Timing (cont’d)

• Typical timing problems– Interfacing fast and slow devices– Interfacing synchronous and asynchronous devices – Bus contention– Avoid indefinite waiting– Meta-stability

• Timing Verification– Test whether all the timing requirements are satisfied– Typically, event ordering, event timing separation and data

setup/hold time are checked.– to be discussed later in more detail

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Timing Diagram & Protocol FlowchartTiming Diagram & Protocol Flowchart

• Timing Diagram– Shows the relationship between the signals

• Ordering, Min/Max separation• Cause and Effect• Parameter table for show min/max timing relationships

– Principal design tool to enable an engineer to match components of different characteristics to work together

– Supplemented by protocol flowchart • Protocol Flowchart

– Abstraction of the timing diagram– provides only the most essential information w/o all detail

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An Example Timing Diagram (D-F/F)An Example Timing Diagram (D-F/F)

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An Example Protocol Diagram (Memory An Example Protocol Diagram (Memory Read)Read)

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Parameter Table (68K memory read)Parameter Table (68K memory read)

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Processor & Memory/Peripheral Processor & Memory/Peripheral InterfaceInterface

• Address bus– 23-bit -> 223 16-bit words to be addressed, interrupt (A01-A03)– can be driven when DMA, multiprocessor system

• Data bus– 8-bit or 16-bit data transfer (bidirectional)– interrupt vector number on D00 to D07

• Asynchronous Bus Control Pins in 68000– AS*: the address (on addr bus) is valid– R/W*: Read or Write

• normally high to avoid unintentional write– UDS*/LDS*: upper, lower data strobe for byte transfer

• when both asserted: word transfer– DTACK*: data transfer acknowledge

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Processor Mem/Peri Interface (cont’d)Processor Mem/Peri Interface (cont’d)

• Synchronous Control Pins in 68000– used largely for older (8-bit) peripheral– VPA* (Valid Peripheral Addr): request for synchronous bus

cycle– VMA* (Valid Memory Addr): 68K informs per. device of valid

addr – E (enable): required by all 6800 series peripheral, E clock

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Synchronous vs. AsynchronousSynchronous vs. Asynchronous

Synchronous

Asynchronous (handshake)

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Memory Mapped I/O vs. Dedicated I/OMemory Mapped I/O vs. Dedicated I/O• Memory mapped I/O

– Motorola style. – No distinction between memory space and I/O space (R/W*)

• Dedicated (Separate) I/O– Intel style– Separate memory space (MemR/MemW) and I/O space (IN/OUT)

• Pros and Cons (of MM IO)– Pros

• Rich set of addressing modes for I/O operation (e.g. bit manipulation)• No overhead on special instructions

– Cons• Processor’s address space is allocated to I/O devices (64KB in i486)• Risk of errors due to spurious accesses (elaborated address decoding)• Lack of special purpose I/O signals to control the I/O operation

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Basic I/O TechniquesBasic I/O Techniques

• Programmed I/O (timed I/O, CPU-initiated I/O)– CPU examines the status of the I/O device to see if it’s ready.– CPU exchanges data with I/O devices via CPU register. – Polled I/O

• CPU checks the status on a regular basis. • CPU time is wasted for status check.

– Direct I/O: very simple device, no status checking (e.g. LED)

• Interrupt-driven I/O– Same data transfer mechanism as in PIO (I/O device reg.)– Data transfers are initiated by the I/O device thru interrupt.

• DMA (Direct Memory Access)– Problem of Interrupt-driven I/O: slow I/O device speed– Removes CPU involvement in the data transfer (I/O dev. Mem)

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Basic I/O Techniques (cont’d)Basic I/O Techniques (cont’d)

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Sequence of Actions in Interrupt ResponseSequence of Actions in Interrupt Response

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Identification of Interrupting DeviceIdentification of Interrupting Device• Polled Interrupt

– have a common interrupt service routine for all devices– the interrupt service routine checks the status of each device in turn

(high software overhead)

• Vectored Interrupt– CPU obtains a vector number from the interrupting device.– Device responds to an IACK by providing a vector number on D00-D07

and asserting DTACK*.

• Autovectored Interrupt– Older devices for 8-bit processor cannot provide vector numbers.– If VPA* is asserted at IACK cycle, the 68000 carries out autovectored

interrupt.– Internally, the 68000 generates the appropriate vector number. – 19h-1Fh reserved for autovectored interrupt

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Vectored vs. AutovectoredVectored vs. Autovectored

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DMADMA• Removes CPU-I/O device bottleneck• Data transfer rate: the order of 10-50Mbytes/s.• DMAC: A coprocessor for DMA process (third party DMA)

– Register set: address reg., count reg., status & control reg.– Bus request (BR*) & Bus grant (BG*)

• Burst mode vs. Cycle stealing– Burst mode: keep the bus until the whole block is transferred (for

fast I/O device)– Cycle stealing: steals a CPU cycle, and transfer a word at a time.

• Bus mastering (first party DMA)– An enhancement of DMA– I/O device not only can send the data to the memory, but also can

take the control of the bus (w/o DMAC)

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A DMA Transaction FlowA DMA Transaction Flow

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BussesBusses• Bus Types: Control bus, Data bus, PC bus• Bus Hierarchy (In modern PC’s)

– Processor bus: chipset processor– Cache bus: cache and processor (e.g. PentiumPro)– Memory bus: memory subsystem chipset and processor – Local I/O bus: high-speed bus to connect performance critical

devices to the memory, chipset, and processor (e.g. PCI, VLB) – Standard I/O bus: for slower devices like mice, modems, soundcard,

low-speed networking (e.g. ISA)

• Data Bus Width– PCI, VLB, EISA: 32bit– ISA: 8 or 16 bit– VMEbus: 8/16/32/64 (VME64) bit– FutureBus: 64/256 bit

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Busses (cont’d)Busses (cont’d)

• Bus Speed– ISA, EISA: 8.33Mhz– VLB, PCI: 33Mhz– Memory and Processor bus: 66Mhz

• Bus Bandwidth– ISA: 4.2-8.3MB/s– VLB, PCI: 133.3MB/s – VMEbus: 40MB/s– VME64: 80MB/s– FutureBus+: 100MB/s (32), 3.2GB (256)

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Electrical Characteristics of BussesElectrical Characteristics of Busses

• Desirable characters– high speed– good noise immunity– minimal bus loading

• Driver/Receiver• Bus loading• Reflection/Termination• Crosstalk/Distortion

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Bus Drivers and ReceiversBus Drivers and Receivers

• Multiple types of devices attached to the bus– NMOS, CMOS, TTL, Low power Schottky TTL, ECL

• Advantage of bus drivers and receivers– The characteristics or behavior of the bus are made independent of

the electrical properties of the modules connected to the bus. (propagation of signals depend on the transmission-line behavior)

• Disadvantage– signal delay incurred by the drivers and receivers

• Bus Sharing by Multiple Devices– Connecting two TTL output stages will not work.– Two solutions

• Open-Collector configuration (Wired logic): active pull-down, passive-pull-up

• Tristate buffer

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Transmission Media CharacteristicsTransmission Media Characteristics

• Main concern– How long can a bus be?– How fast the system can transmit information through it?

• Characteristics of typical transmission media

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Bus ArbitrationBus Arbitration

• Necessary when– more than one bus master contend for bus mastership

• Serial (daisy-chain) vs. Parallel

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VMEbusVMEbus• General features

– Intended to support the 68000 series and is a backplane bus– Semi-asynchronous (like 68000 bus cycle)– Widely used bus for RT system ($2billion in ‘98, War against PCI)– Main purpose: to allow the systems designer to put together a

microprocessor system by buying off-the-shelf component

• Electrical Characteristics– No more than 21 slots, no longer than 19.68in

• VMEbus Mechanics– single height or double height, 96 pins

• Advantages– Configurable & Flexible (scalable, modular, Good OS support)– Withstands harsh environment (reliable and stable)– Faster development cycle

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Other busesOther buses

• STD(simple to design): 2MB/s• Multibus (Intel 8086, 16bit, IEEE796), Multibus II

(32bit)• NuBus (Apple Mac II, SE) • CardBus (Portable)• I2O (Intelligent IO)• I2C • SCSI• USB• AGP

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Section 5: Communication SystemsSection 5: Communication Systems

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OverviewOverview

• Parallel vs. Serial I/O

• Synchronous vs. Asynchronous I/O

• Analog vs. Digital Transmission

• Encoding and Transmission Controls

• Data Communication for Embedded Systems

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Parallel vs. Serial I/OParallel vs. Serial I/O

• Parallel– Fast– Typically for heavy data transmissions like printer, scanner

• Serial – Parallel wiring: expensive, hard to control – Wires may not exist (e.g. wireless).– Better efficiency: a single powerful driver may be cheaper

than many drivers– Reliability– Very widely used for keyboard, modem, mice, and many

more

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Buffering & HandshakingBuffering & Handshaking

Non-buffered

Single-buffered

Double-buffered

Open-loop Transfer

Closed-loop Transfer

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Case study: 68230 Parallel Interface/TimerCase study: 68230 Parallel Interface/Timer

• A general-purpose peripheral, whose functions include– an 8- or 16-bit parallel interface between a CPU and an

external system– a programmable timer– has many user-programmable facilities

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68230 Internal Structure68230 Internal Structure• supports vectored interrupt

and DMA• two independent 8-bit

programmable I/O ports (A&B)• dual function C port (simple

I/O port, timer)• Handshake lines:

– H1(In), H2(Out) for A– H3(In), H4(Out) for B

• Timer (24bit counter,5bit input-prescaler)– TIN : clock pulse or other

– TOUT: single/periodic pulse

– TIACK* : Interrupt ACK

• 23 internal registers

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Serial I/OSerial I/O

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• Major concern (Protocol)– How to split the incoming data stream into individual units (bits)– How the receiver know where a data word starts and where it

stops?

• Point-to-point vs. Multidrop (1 master, N slave)

• Simplex (unidirectional), Half-Duplex (cab driver’s radio), Full-Duplex (phone)

• DTE (Digital Termination Equipment) and DCE (Digital Communication Equipment)

Serial I/O BasicsSerial I/O Basics

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Serial I/O (cont’d)Serial I/O (cont’d)

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Asynchronous vs. SynchronousAsynchronous vs. Synchronous• Asynchronous

– Transmitted data and received data are not synchronized.– Very old (slow) transmission system (telephone,Morse code,

etc.)– Time interval between successive data may vary.– Character oriented (ASCII: 7 bit, Baudot: 5 bit, Unicode: 16bit) – Receiver’s clock > x16 of data rate

• Synchronous– More efficient (w/o start and stop bits)– Clocks between transmitter and receive needs to be

synchronized• Digital signal: biphase encoding• Analog signal: carrier frequency• Either character-oriented or bit-oriented frame

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Asynchronous vs Synchronous (cont’d)Asynchronous vs Synchronous (cont’d)

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Asynchronous TransmissionAsynchronous Transmission

• idle state (mark level)• start bit (space level)• parity bit (optional)• stop bit at a mark level for one or two bits (not strictly required)

(even)

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Receiver Clock TimingReceiver Clock Timing

When N=9, (7-bit character+a parity bit+1 stop bit) the maximum permissible error = 100/19 = 5%Overall effieciency?

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Asynchronous Communications Asynchronous Communications Interface Adapter (ACIA)Interface Adapter (ACIA)

• Taking care of serial-to-parallel (or vice versa) conversion• 6850 ACIA

– old but still popular– Synchronous bus cycle (E,VPA,VMA)– Autovectored interrupt

• 68681 DUART – Dual Universal Asynchronous Receiver Transmitter– Two 6850 + a baud-rate generator– Asynchronous data transfers, Vectored interrupt– Programmable baud-rate generator– Quadruple buffered input, double-buffered output– Several operating (testing) mode 16550 UART, 8250 UART for Intel-based machines

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6850 ACIA6850 ACIA

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COP vs. BOPCOP vs. BOP

HDLC (High-level Data Link Control)

BISYNC

Boundaries of the frame

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Bit StuffingBit Stuffing

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Digital Encoding TechniquesDigital Encoding Techniques

Self Clocking? Or not?

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Digital Data Analog Signal Digital Data Analog Signal

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Flow Control & Error ControlFlow Control & Error Control• Flow Control

– Software flow control (XON/XOFF)– Hardware flow control (CTS/RTS)

• Error Checking– Parity– CRC (Cyclic Redundancy Check)

• Error Control: ARQ (Automatic Repeat Request)– When an error is detected, the receiver requests that the frame be

retransmitted.– Stop-and-wait ARQ– Go-back-N continuous ARQ– Selective-repeat continuous ARQ

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Overview of Data CommunicationOverview of Data Communication

• Data and Signals– Digital Data/Digital Signal: NRZ, Manchester– Digital Data/Analog Signal: ASK, FSK, PSK – Analog Data/Digital Signal: PCM, PAM, PWM, Delta modulation– Analog Data/Analog Signal: Amplitude modulation, Freq. Mod.

• Transmission medium– Twisted pair– Coaxial cable– Fiber Optics– Microwave link

• Multiplexing– TDM– FDM

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Overview of Data Communication (cont’d)Overview of Data Communication (cont’d)• Topology

– Ring– Star– Mesh

• Transmission Access Control– CSMA/CD– Token Ring– Reservation– Round-Robin

• Switching– Circuit– Packet

• Networking: LAN, MAN, WAN

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Communication Protocols for Embedded Communication Protocols for Embedded Systems Systems [Embbed Systems Programming, 7 Nov. [Embbed Systems Programming, 7 Nov. 1994]1994]

• Special Considerations– Protocol efficiency: low overhead bits (in ES, most of the messages are

short, periodic)– Reduced media access overhead: worst-case behavior is important.

(CSMA/CD: good at light load, but poor at heavy load)– Deterministic latency: prioritization– Robustness: quickly detect and recover from errors– Configuration flexibility

• Media Access Protocols– Connection oriented (modem, SNA, X.25)– TDMA– Token Ring– Token Bus– Binary Countdown (CAN)– CSMA/CD

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Communication Protocols for ES Communication Protocols for ES (cont’d)(cont’d)• Media Access protocols - Tradeoffs

– Polling, TDMA, Connection-based• Simple, may not be sufficiently flexible for advanced systems

– Token-based protocols• predictable, but high overhead, and complex software to

maintain robustness– CSMA/CD

• a poor choice for hard real-time systems with heavy traffic– Reservation-based protocol is a good choice for embedded

systems