1858 IEEETRANSACI'IONS ON NUCLEAR SCIENCE, VOL. 36, NO. 6, DECEMBER 1989

DOSE DEPENDENCE OF INTERFACE TRAPS IN GATE OXIDES AT HIGH LEVELS OF TOTAL DOSE

M. P. Baze, R. E. Plaag, and A. H. Johnston High Technology Center

Boeing Aerospace and Electronics Seattle, Washington 98124

Abstract

Interface traps in gate oxides were found to saturate at high total dose levels. An empirical model was developed to describe the nonlinear dependence and saturation characteristics. Three different processes were studied including CMOS/SOS, hardened bulk CMOS and unhardened bulk CMOS using several combinations of dose rate and bias. An evaluation was made of the model's accuracy in extrapolating the effect of interface traps to very high doses. A possible application of the model in characterizing devices for space environments is discussed along with implications for a physical model of radiation induced interface trap buildup.

INTRODUCTION

In order to predict the total dose radiation response of MOS devices, the dose, bias, and time dependence of the two primary charge components, trapped holes and interface traps, must be understood at a level where practical mathematical models describing these effects can be developed and applied. For the case of trapped holes, Not, detailed models have been developed which include effects of electric field, oxide thickness, time, nonlinear buildup, nonuniform buildup, annealing, and saturation.[ 1-41 Similarly for interface trap density, Dit, models have been developed which at least in qualitative fashion describe the effects of time delayed buildup, dependence on electric field, and sublinear buildup with dose at low dose levels.[5-8] However the effects of sublinear buildup and saturation of interface traps at high dose levels are not as well understood. Early studies on gate oxide capacitors revealed an empirical dose2p dependence with no saturation at levels up to 20 Mrad(Si).[Sl The oxides used in these studies were approximately 100 nm thick. Later studies found that a linear interface trap buildup is more typical at doses between 100 krad and 1 Mrad(Si).[9,10]

In recent work Bennedetto, et al.@] have measured ADit at dose levels up to lo8 rad(%) and reported a sublinear buildup at high doses that does not obey a simple power law, but can be fit by the hyperbolic form,

where ADit represents the change in interface trap density, is the radiation dose, and a and b are fitting parameters. Their work, which emphasized the low dose rather than high dose environment, also presented evidence that interface traps saturate at very high dose levels and suggested a physical interpretation of saturation.

In this paper, a different model for radiation-induced interface trap buildup is developed from data obtained using bulk CMOS and CMOS/SOS test structures from several different processes that were irradiated over a wide range of dose rates. While this model is different from the hyperbolic form, it implies the same physical interpretation of Dit saturation and also provides a better fit to the nonlinear behavior of the devices in our study.

Interface trap buildup was measured on transistor test structures using the subthreshold slope technique. Three different processes were investigated, with oxide thicknesses ranging from 20 to 36 nm. Note that these gate oxides are much thinner than the older structures for which the D2I3 power dependence was observed for interface traps. Data were obtained for several combinations of dose rate and bias at dose levels up to 50 Mrad(Si). Emphasis was placed on the sub- linear and saturation aspects of Dit buildup. The results of this study confirm that interface traps saturate at high dose levels. The model closely agrees with experimental results for the three processes and also provides an accurate description of the data of Benedetto, et a1.[8] This model is useful in extrapolating data at intermediate dose levels to high doses, and bears a physical analog that may help describe the mechanisms of interface trap formation. Experimental results of this study indicate that the model may be of value in an approach for using high dose rate data to characterize devices for space applications.

EXPERIMENTAL APPROACH

Test chips were obtained from three vendors, designated here as A, B, and C. Vendor A's process was a hardened commercial CMOS, vendor B's an unhardened CMOS and vendor C's a commercial SOS. Gate oxide thicknesses were 23 nm for A, 20 nm for B and 36 nm for C . The test chips

58$01.00 0 1989 IEEE 0018-9499/89/1200- 18

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contained test transistors with various geometries that were bonded out in ceramic packages without lids to allow testing with a low-energy X-ray source. While both n- and p-channel devices were measured, this study focuses on n-channel transistors because under normal operating bias conditions the interface trap buildup in these devices is greater. On vendor As chip closed geometry transistors were used to avoid the effects of field oxide inversion leakage. Closed geometry devices were not present on devices from the other two vendors.

Subthreshold slope measurements on transistors were made using a Hewlett-Packard Hp4 145 parameter analyzer. N- channel transistors were swept from accumulation to inversion at a rate of 0.5 V/s. Comparisons were made with data obtained by sweeping from inversion to accumulation and by sweeping at different rates. For the devices in this study no differences due to the direction of sweep were found. Sweep rates faster than 0.5V/s resulted in increased noise. Slower rates gave no improvement in noise and no differences in results. The 0.5 V/s rate was chosen to minimize noise and measurement time.

Most irradiations were performed using 10 keV (nominal) X-rays from an Aracor Semiconductor Radiation System. X- ray dose rates ranged from 10 krad(Si)/min to 300 krad(Si)/min. Some additional tests using Co-60 gamma rays were performed at a dose rate of 13 rad/min. Each device was exposed in successive irradiations at levels from 100 krad(Si) to doses well into the sublinear region of interface-trap buildup, typically 10 Mrad(Si). To correct for energy dependent differences between the X-ray and gamma sources, a lead-aluminum equilibrium shield was used for the CO-60 exposures. A description of this shield can be found in previous studies which obtained good comparisons between the two sources when using this type of shield. [9, 11-14]

In tests to evaluate Dit. buildup, transistors were biased during and between irradianons with bias removed only during the time required to take measurements. Measurements were made as soon as possible after each exposure, usually within one minute. The effect of delayed buildup is discussed further in a later section that compares model paramters.

Additional tests were performed to detect the influence of lateral nonuniformities or field-oxide inversion on the the subthreshold slope of transistors. In one method, described by Freitag et a1.,[15] bias was switched midway through irradia- tion to produce photoannealing of lateral nonuniformities. Measurements were also made at times up to several days after irradiation to investigate annealing, since lateral nonunifor- mities anneal at room temperature. Results of these tests are discussed below in the analysis section.

ANALYSIS

DelQQ from Subthreshold Slope

To calculate changes in Dit from the subthreshold slope parameter, S, one can use the following equation (from Brews, [ l a )

where B =(kT/@h(lO) k = Boltzmann's constant q = electron charge T = temperature S = subthreshold slope c d = depletion layer capacitance Cox = oxide capacitance a = 2 (ESi/ESi02)(b~/Ld) tox = oxide thickness

and Ld = diffusion length.

By substituting cit+cd for c d according to Sze [17], one can solve for ACit to obtain

ACit = Cox( Kj - KO ) (3)

and

(4)

a2( -B +JB2 - 8 Si (B - Si)' )

4 s j

Cit = interface trap capacitance Dit = interface trap density (cm-2 eV1) A = gate area (cm2) S, = subthreshold slope at the jth radiation level So = subthreshold slope prior to irradiation. and

Equation 2 differs from that used by Winokur et al. [lS] by the factor

which becomes more significant as Cit increases at high doses.

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Subthreshold slopes for vendors A and B were measured from currents approximately two decades above the noise floor of the Hp4145 to two decades &low threshold. this region the subthreshold curves were straight for two or more decades of Current and corresponded to the maximum slope (minimum S). Examples of pre-hadiation and post-irradiation subthres- hold Curves for vendor A are shown in figures 1 and 2. Note that the slopes are constant over a wide range of currents.

Lateral Nonuniformities and Leakape

Lateral nonuniformities in fixed charge can influence subthreshold Slope measurements, altering the calculated Dit results.[l5,19] Errors will occur when either nonuniformities or, in open geometry devices, field oxide leakage, distort and stretch Out the subthreshold Slope. These effects Will Cause the calculated values of Dit to be erroneously high. However,

h z E

E n

m Y

C .- - 5 = 106 mVldecade

-0.5 0 0.5 1 .o 1.5 2.0

VGS (volts)

Figure 1. I-V charactersitics of a hardened bulk CMOS transistor before and after irradiation.

10-3 c -

C

10-4 1

an-10 . I/ , I

0.0 0.5 1 .o 1.5 I U -1.0 -0.5

vgs (volts)

Figure 3. I-V characteristics of a commercial CMOS/SOS transistor before and after irradiation.

Dose rate = 300 krad/min unlike interface traps, both lateral nonuniformities and field oxide leakage are subject to annealing at room temperature. In a technique used by Freitag et a1.[15] the presence of nonuniform Not effects on subthreshold slope can be detected by allowing Not to anneal at room temperature, and testing to see if there is any increase in subthreshold slope. To verify that nonuniformities and oxide leakage were not significant factors in the data presented here, separate annealing tests were performed on samples from each vendor. These tests showed that lateral nonuniformities and leakage current were only important at very high levels, typically above 50 Mrad(Si) for the hardened bulk CMOS and CMOS/SOS devices. However, for the unhardened CMOS devices these effects limited the data to below 5 Mrad(Si). For all data reported in this study, annealing of the subthreshold slope was less than 5

2*o percent of the radiation-induced change. vgs (volts)

Figure 2. I-V Characteristics of a hardened bulk CMOS transistor after 50 Mrad(Si).

However, the subthreshold slope for vendor C displayed the double-slope characteristic of open-geometry SOS devices, as shown in figure 3. The lower slope of this curve is caused by the more lightly doped side channel while the upper portion is the top channel gate. Since the region of most concern is the top channel, subthreshold slope for these devices was measured approximately one decade below threshold.

Oxide Field

Previous studies have noted that radiation-induced changes in the gate oxide field can affect the buildup of interface traps.[20] This is particularly important near OV gate bias where the buildup of trapped holes can cause reversal of the oxide field. To evaluate this possibility the pre- and post- radiation oxide fields were calculated by solving Poisson's equation for the appropriate gate structures using the measured values of interface traps and trapped charge. For the +5V gate

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bias cases our calculations show initial oxide fields of 1.4 to 2.5 MV/cm. These values changed less than two percent after irradiation. In the -2V gate bias case for vendor A the initial field was -0.4 MV/cm and decreased to -0.45MV/cm after irradiation. For the OV bias cases vendors B and C had initial fields of 0.12 and 0.07 MV/cm respectively and showed less than 10 percent decrease in field after irradiation. Vendor A did show a decrease from 0.15 to 0.10 MV/cm at OV bias but, as discussed below, results obtained on this process showed that the interface-trap buildup was relatively insensitive to dif- ferences in field. As a result of these calculations none of the above changes in oxide field would be expected to significantly influence interface-trap buildup in our results.

EXPERIMENTAL RESULTS

Plots of ADit versus dose from transistor subthreshold data for each of the three processes are shown in figure 4. All transistors were irradiated with +5 volts gate bias. Transistors from vendors A and C were exposed at a rate of 10 krad/min and transistors from vendor B were exposed at 20 krad/min. Points on this graph represent the actual data while the lines represent least-square fits to the model described in the next section. Note that at low doses the interface density is approximately linear with dose, and that it gradually saturates for all three processes as the dose increases.

..................... I ......._.......... D' .....-........ I ...... ......... h""" "" ...9.'" + ,,4 .i _,:.-.- 1)'

- --- + - B. unhardened CMOS, tox = 2Onm ........ A - C, CMOS SOS, tox = 36nm

Gate bias = + 5V

- A, hardened CMOS, tox = 23nm

I I I I I I I I 0 2 4 6 a 10

Dose [Mrad (Si)]

Figure 4. Change in Dit from subthreshold slope data for n- channel transistors from three processes (points indicate data, lines show fits to model).

Figure 4 shows that from one process to another there is wide variation in both the initial buildup of Dit and the level at which the damage saturates. The experimental results for processes A and C extend out to high total dose levels, and clearly show saturation. Note that the deviations from the fitted curve are less than 5%. Devices for process B were tested over a more limited dose range. While the last two data

points for process B appear to indicate saturation at about 5 Mrad(Si), the line, which is a least squares fit of the model to all eight data points shows that this device has not yet reached Saturation.

Figure 5 shows similar data for vendor A taken at three different dose rates. In this graph the initial buildup rates vary by an order of magnitude but the saturation levels are similar. This demonstrates that the saturation behavior does not depend strongly on dose rate.

Hardened CMOS n -channel y4+.-++ , . A . . . . w - A . . 4

Gate bias I + 5V tox = 23nm ...'d.

...''''.

> P E Y 10' l- - - 6 a

- 0 - 13 rad (Si)/min CO-60 -- + - 10 krad(Si)/min X-ray ..... A - 300 krad(Si)/min X-ra)

38

Figure 5. Change in Dit from subthreshold slope data for three different dose rates (points indicate data, lines show fits to model).

Figure 6 compares data for vendor A taken at different bias conditions. In this case there was surprisingly little dependence on bias. Possible reasons for this are discussed in more detail in the next section.

Although the main emphasis of the study was n-channel devices, we also measured interface-state buildup for p-channel devices. Figure 7 shows representative data for p-channel devices from vendor A. Note that for normal operating bias conditions the p-channel devices have far less Dit buildup than their n-channel counterparts in figure 6. Similar results were obtained for p-channel devices from the other processes.

The plots in figure 2 show the subthreshold slope data at 50 Mrad(Si) for each of the devices in figure 6. Note that the slope is consistent, even at low currents. In all cases (see figures 4 through 7), Dit shows a rapid buildup which is roughly linear to about 1 Mrad of dose, becomes sublinear somewhere between 1 Mrad and 10 Mrad, and then nears saturation at 10 to 30 Mrad. Thus, modeling or prediction of total dose behavior above 1 Mrad requires a nonlinear description of interface trap dose dependence.

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10 Hardened CMOS

- n-channel - = 23nm

Dose rate = 300 kradlrnin

- 7 5

e ? 6

-- 5

' = 4 I 5 a 3

5 0 r

Dose [Mrad (Si)]

Figure 6. Change in Dit from subthreshold slope data for three values of gate bias (points indicate data, lines show fits to model).

2o IHardened CMOS p - channel

1 5 c ,+/ + + i tox = 23nm Dose rate = 300 kradlm5- _____--_-___

I 'TF

- 0 - vgs = - 5v vgs= ov

10 20 30 40 50 Dose [Mrad (Si)]

Figure 7. Change in Dit from subthreshold slope data for two values of gate bias (points indicate data, lines show fits to model).

DISCUSS ION

Model

which is present prior to irradiation in fixed density and determines the saturation level of Dit. It is known that many of the interactions of radiation with matter can be described as random Poisson processes in which the Poisson parameter, h, is the probability per unit dose that the given interaction will take place. If Pit(D) is the density of precursors present after a radiation dose, D, and h is the probability per unit dose that any given precursor will complete the transformation to an interface trap, then the rate of interface trap production will be

a Pi@)

aa Pit(D)l [ k 1 (3 ----------- =

in units of [l/(cm2 - eV- rad)]. Integrating from 0 to a given dose value yields

Since the initial precursor concentration, Pit(0) and h are constants, equation 6 describes the precursor concentration as a function of dose. To obtain ADit from this equation we note that the change in interface traps will equal the change in precursors,

and that the saturation level of interface traps, ADsat is equal to the available pre-irradiation precursor concentration, Pit(0). Then substituting these into equation 6 we obtain the equation for our model,

Note that at low dose levels this equation reduces to the linear form*

which not only agrees with our data below 1 Mrad(Si), but also with data reported by other workers in this dose range.[8- 101 The reciprocal of the Poisson parameter, X, corresponds to an approximate dose level where ADit departs from linearity.

As discussed earlier, fits of this model to the data obtained in this study are shown in Figures 4 through 7, and are in good agreement. Figure 8 shows a similar comparison using the data of Benedetto et al.[81 for a hardened process from two

Examination of the data indicates that interface-trap buildup due to radiation approaches a saturation level in an asymptotic

*The linear dependence between dose and Dit was used by Brown, Jenkins and Johnston in developing a methodology for hardness

manner with increasing dose. In noting the apparent aSSUfanCe h Space applications.[21] This k a reasonable assumption

a more complex dependence is required for applications at higher total dose

saturation of Dit at high dose levels, Bendetto et a1.[8] for as shown by the present work%

speculated that there may be an "interface trap precursor"

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Dose Rate (rad/ min)

different vendors. As seen in these figures, there is good ComDarisons Of Parameters

Gate Bias (V)

agreement between experimental results and the model for a wide range of device technologies -- five different manufacturers are represented -- and test conditions.

10’41 Commercial Hardened NMOS I t~~ = 20nm

1013 -

E Y c

1 o4 i o 5 106 1 o7 108

Dose [rad (Si)]

Table 1 is a summary of results showing the parameters obtained when applying this model to data for different processes and bias conditions. There are three points worth noting here. First, the saturation trap density Dsat is quite process dependent but does not seem to be a strong function of dose rate or bias, except for the SOS process (vendor C). Second, h depends on dose rate, increasing as the dose rate is reduced. Third, h is only weakly affected by bias for the two bulk devices, but is strongly affected by bias for the CMOS/SOS process.

That h is a function of dose rate can be explained by the delayed buildup of Dit. Since tests performed at a high dose rate do not allow as much time for Dit buildup, the measured Dit at a given dose will be lower during high-rate tests than it will for low-rate tests. Then, as pointed out by Fleetwood et a1.,[21] the apparent dose rate dependence is really just an artifact of the delayed buildup in Dit. In this case, the apparently lower rate in Dit buildup at high dose rates will result in a lower value for h.

Figure 8. Fit of the empirical model to data on hardened processes from two vendors. The observation that Dsat is not a function of bias agrees

with the model of a Poisson process for which the Poisson

Table 1. Analysis constants from subthreshold slope data.

Process Dsat Estimated

A

B

300k + 5 1 -; y 2Ok + 5 1.1 ~1012 3 . 6 ~ l o 7 1.1 x 10l2

1.2~1012 5 . 7 ~ 1 0 . ~ 9 . 0 ~ 1 0 ” f 2.9~1011 1.51~10-7 2 . 4 ~ 1 0 ” 1 .16x 1012 1.27 x 106 8.7 x 1 0

interval is dose and hence independent of dose rate.

That neither Dsat nor h are strong functions of bias for vendors A and B is unexpected. Based on previous reports [6,7] one would expect that either the number of available precursor states, Pit(0) or Dsat, or the probability of transformation, h, would be strong functions of bias. One difference between this and the previous studies is that the gate oxides for vendors A and B were much thinner. Oxide thicknesses in the previous work were 40 and 100 nm whereas A and B were 23 and 20 nm respectively. The oxide thickness of vendor C was 36 nm, and it shows a strong dependence on bias with changes in both Dsat and h, similar to the response of the thicker oxide devices in earlier studies. Thus, oxide thickness may play a role in bias dependence of both the interface trap density and the saturation dose.

A m

To test the ability of this model to predict interface trap buildup we performed parametric fits of our data at low dose levels and compared the Dsat values obtained in this manner with those calculated using the full range of data. The results are shown in the right column of table 1, and are in reasonable agreement. These results show that it is possible to extrapolate from doses on the order of l /h to obtain an estimate of Dsat, which determines the interface state density at much higher levels.

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A more useful application of this model follows if D,,t is 191 independent of dose rate as suggested by our data. In this&se one could characterize devices for space applications by using high dose rate data to determine &at, and low dose rate data in the linear region of Dit buildup together with equation (9) to derive h, thus avoiding the need for very long term, low dose- rate testing. A likely test sequence on a single device would be a series of low rate exposures in the linear region of buildup followed by high rate exposures to a Dit level near

101

111

[121 saturation. Although our data indicates that the saturation characteristics of bulk CMOS devices with thin oxides are independent of dose rate, further tests are needed to establish this for a wider range of device technologies.

~ 3 1

CONCLUS IONS

Data were obtained for several device technologies and test conditions that show interface-trap buildup to be linear at low total dose, but sublinear with dose with clear evidence of saturation at high levels. An empirical model was developed which fits this data well at both high and low dose rates. The model allows extrapolation of measured results to higher levels of dose, and may have useful applications in the area of device characterizations for space. A physical analog of the model was discussed which follows the form of other radiation-induced reactions.

1141

tu]

[16]

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