Donmez a. - Wideband PLL System as a Clock Multiplier (2009)

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Master of Science Thesis

Wideband PLL System as a ClockMultiplier

Aylin Donmez

August 17, 2009


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Wideband PLL System as a Clock

Multiplier

Master of Science Thesis

For obtaining the degree of Master of Science in Electrical Engineeringat Delft University of Technology

Aylin Donmez

August 17, 2009

Faculty of Electrical Engineering

Delft University of Technology


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Acknowledgments

The past two years I have spent at TU Delft have been a fabulous journey mostly becauseof the amazing people I have met, who have been a part of it. I feel to have built a greatknowledge and perspective both in my career and social life.

First and foremost, I would like to thank my company supervisors, Gerard Lassche and FransSessink whose support was always available when needed. I am grateful to Gerard Lasschefor his inestimable guidance and interest in the project. His significant contribution duringthe layout design has been a priceless support. I would like to thank Frans Sessink for hisvaluable assistance on system level analysis of PLL, and his trainings on frequency domainloop analyses in Simetrix have been informative.

I would also like to thank Kave Kianush for giving me this opportunity and sponsoring theproject. I am grateful to valuable inputs and reviews of Prof. John Long as a university

supervisor, during the design reviews.

I also wish to thank some of the other excellent engineers of Catena Microelectronics who haveshaped my point of view on various design phases. I am grateful to Koen van Hartingsveldtfor his precious guidance regarding to RF perspective of the system. I am especially thankfulto Nicole Eisenberg, Ivaylo Bakalski and Mattias Wallberg for resolving countless issues andbeing excellent admins during the layout design. I would like to thank Atze van der Goot, forproviding the assistance to get my design processed. I am also thankful to Hans Rosenbergfor his support on test board design.

Words cannot express my gratitude to my dear friend Serpil Sevilay Senturk, for her constantlove, support, and understanding. I can only hope to preserve our heartfelt relationship. My

warmest thanks also go to Tuba Yilmaz, Unal Kocabas, Ibrahim Over for their support, greatfriendship, and many wonderful memories. I am truly lucky to have made great friends suchas Remziye Nasuhoglu, Guner Arici, Burak Sozgen and Cigdem Demirel with whom we haveset up the innovative institution More en de Ruif that basically offers fun activities and moralsupport services.

Finally, I would like to express my enormous thanks to my mother Muruvvet Donmez, myfather Ibrahim Donmez, my sister Pervin Donmez, and the rest of my family. No matterhow far away they may be physically, they are never far from my heart and mind. All myendeavors are to deserve their boundless love and support without which I would never havehad the strength and courage to pursue my dreams, and for that I dedicate this thesis to

them.

M.Sc. thesis Aylin Donmez


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vi Table of Contents

3 PFD & Charge Pump 19

3.1 Phase Frequency Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1.1 Multiplier Phase-Detectors . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1.2 XOR Phase Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213.1.3 Tri State Conventional Phase Detector . . . . . . . . . . . . . . . . . . . 223.1.4 High Frequency Limitations of Conventional Phase Detectors . . . . . . . 22

3.1.5 Dynamic Logic Phase Detectors . . . . . . . . . . . . . . . . . . . . . . 25

3.1.6 Phase Frequency Detector Design . . . . . . . . . . . . . . . . . . . . . 27

3.2 Charge Pumps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.2.1 Current and Pulsewidth Mismatch . . . . . . . . . . . . . . . . . . . . . 313.2.2 Timing Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.2.3 Leakage Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.2.4 Charge Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.2.5 Clock Feedthrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.2.6 Charge Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.2.7 Charge Pump Architectures . . . . . . . . . . . . . . . . . . . . . . . . . 34

Single-ended charge pumps . . . . . . . . . . . . . . . . . . . . . . . . . 34

Differential Charge Pumps . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.2.8 Differential Charge Pump Design . . . . . . . . . . . . . . . . . . . . . . 36

Switch Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Common Mode Feedback Circuit . . . . . . . . . . . . . . . . . . . . . . 38Unity Gain Buffer Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Bias Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Glitch Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4 VCO & Divider 514.1 Ring Oscillator VCOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.1.1 Single Loop Ring Oscillator Design . . . . . . . . . . . . . . . . . . . . . 53

4.1.2 Multi Loop Ring Oscillator Design . . . . . . . . . . . . . . . . . . . . . 55

Odd Number of Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Even Number of Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.1.3 Loop Architecture Decision . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.2 Gain Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594.2.1 CMOS Digital Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4.2.2 Differential Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

4.2.3 Delay Cell with push pull inverters (DC1) [12] . . . . . . . . . . . . . . . 62

4.2.4 Delay Cell with feedback control (DC2) [24] . . . . . . . . . . . . . . . . 64

4.2.5 Delay Cell with common mode noise rejection (DC3) [15] . . . . . . . . . 66

4.3 Delay Cells Performance List . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

4.4 Ring Oscillator Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

4.4.1 VCO Tuning Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4.5 Layout of the VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

4.6 Divider Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

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Table of Contents vii

5 Top Level 77

5.1 Loop Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

5.2 Wideband PLL Characteristics Validation . . . . . . . . . . . . . . . . . . . . . . 85

5.2.1 Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

5.2.2 Phase Noise Measurement and Other Design Metrics . . . . . . . . . . . 85

6 Conclusion and Recommendations 87

6.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

A PLL Basics 89

A.1 PLL Dynamics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

A.1.1 Loop Order and Loop Type . . . . . . . . . . . . . . . . . . . . . . . . . 90

A.1.2 Loop response to a step change in phase . . . . . . . . . . . . . . . . . . 91

A.1.3 Loop response to a step change in frequency . . . . . . . . . . . . . . . 92

Bibliography 95



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x List of Figures

3.4 Output Characteristic of Exor PFD . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.5 Exor Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.6 Tri State Phase Frequency Detector . . . . . . . . . . . . . . . . . . . . . . . . 22

3.7 UPDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.8 UPcharacteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.9 Output Characteristic of a PFD at high frequencies [18] . . . . . . . . . . . . . 24

3.10 Waveforms during blind zone . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.11 Architecture proposed by Johansson . . . . . . . . . . . . . . . . . . . . . . . . 25

3.12 Architecture proposed by Mansuri . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.13 Architecture proposed by Tak . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.14 Output characteristic in [10] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.15 Shorter delay problem in reset path . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.16 Phase Frequency Detector used in this work . . . . . . . . . . . . . . . . . . . . 29

3.17 PFD output for in phase 1GHz square wave inputs . . . . . . . . . . . . . . . . 29

3.18 PFD outputs at 1GHz when the reference signal leads for 300 ps . . . . . . . . . 30

3.19 PFD Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.20 PFD Output Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.21 Phase Frequency Detector Layout . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.22 Charge Pump leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.23 Single ended charge pumps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.24 Single ended charge pump architectures a)with current steering switch b)with ac-tive output buffer c)with NMOS switches only . . . . . . . . . . . . . . . . . . . 36

3.25 CPhigh speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.26 Noise voltage at charge pump output . . . . . . . . . . . . . . . . . . . . . . . . 39

3.27 Switch layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393.28 Common Mode Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.29 Transconductance of common mode loop . . . . . . . . . . . . . . . . . . . . . 41

3.30 Layouts of common mode circuit and unity gain buffer . . . . . . . . . . . . . . 42

3.31 Unity gain buffer used in this work . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.32 AC response for different input levels of UGB . . . . . . . . . . . . . . . . . . . 45

3.33 CP-Bias Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.34 Layout for CP bias block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.35 Transmission gate as a switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47



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List of Figures xi

3.36 Modification for Glitch Suppression . . . . . . . . . . . . . . . . . . . . . . . . 47

3.37 Charge pump Full Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483.38 Complete Charge pump layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.1 Three-stage ring oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

4.2 4 Stage Multi Loop Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.3 3-stage ring oscillator with multi loop architecture . . . . . . . . . . . . . . . . . 55

4.4 3 stage ring oscillator 1st order model . . . . . . . . . . . . . . . . . . . . . . . 56

4.5 4 stage multiple pass ring oscillator architecture . . . . . . . . . . . . . . . . . . 58

4.6 Simple Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4.7 Delay Control in Differential Gain Stages . . . . . . . . . . . . . . . . . . . . . . 61

4.8 (DC1) Delay Cell Proposed by [12] . . . . . . . . . . . . . . . . . . . . . . . . 63

4.9 Phase Noise ofDC1 @ 5.053GHz . . . . . . . . . . . . . . . . . . . . . . . . . . 63

4.10 Small signal equivalent model ofDC1 used to calculate PSRR [12] . . . . . . . 64

4.11 (DC2) Delay Cell [24] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4.12 Phase noise ofDC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4.13 Small Signal Model ofDC2 used to calculate PSRR in [24] . . . . . . . . . . . 65

4.14 Schematic of the DC3 [15] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4.15 Small signal model ofDC3 for PSRR calculation . . . . . . . . . . . . . . . . . 67

4.16 Schematic and block schematic of the delay cell used in this work . . . . . . . . 69

4.17 Phase Noise performance of the delay cell used in this work 5GHz . . . . . . . . 70

4.18 Small Signal Equivalent to half circuit for PSRR calculation . . . . . . . . . . . . 71

4.19 Schematic of VCO delay cell used in this work . . . . . . . . . . . . . . . . . . . 72

4.20 VCO delay cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.21 VCO top level layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.22 Block Schematic of the divider used in this work . . . . . . . . . . . . . . . . . . 75

4.23 Jitter performance of the divider . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.24 Divider phase noise performance . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5.1 Loop Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5.2 Differential loop filter used in this work . . . . . . . . . . . . . . . . . . . . . . . 78

5.3 Simetrix Model of the Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

5.4 Loop AC response in Simetrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

5.5 Noise Behaviour of the loop in Simetrix . . . . . . . . . . . . . . . . . . . . . . 81



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xii List of Figures

5.6 Settling Behavior in Fast Corner . . . . . . . . . . . . . . . . . . . . . . . . . . 81

5.7 Top level Layout - Core Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825.8 Top level layout including the pads . . . . . . . . . . . . . . . . . . . . . . . . . 83

5.9 bonding diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

5.10 Loop bandwidth measurement setup . . . . . . . . . . . . . . . . . . . . . . . . 85

A.1 Basic phase-locked loop block diagram . . . . . . . . . . . . . . . . . . . . . . . 89

A.2 Loop filter with stabilization zero . . . . . . . . . . . . . . . . . . . . . . . . . . 90



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List of Tables

3.1 UGB transistor sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.2 UGB transistor sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.3 Bias Block transistor sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.1 Comparison of performance metrics of delay cells . . . . . . . . . . . . . . . . . 68

4.2 VCO Tuning Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

5.1 PLL Performance Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79



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xiv List of Symbols



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Chapter 1

Introduction

In this work a Wideband PLL system is proposed to reduce the effects of the voltage controlledoscillator, V CO, pulling in zero-IF and low-IF wireless transceiver systems. The system isconsist of a phase frequency detector, PFD and a charge pump, CP, which are capablehigh frequency operation. A differential loop filter, a fixed divide-by-6 divider and a ringoscillator which is implemented with a novel architecture of multipath configuration are othercomponents of the system. Wideband PLL is fabricated in a standard CMOS IBM 65nmprocess, and is efficient with respect to its die area.

1.1 Project Description

In transceiver systems, both zero IF and low IF transceivers, VCO frequency is the same asthe antenna frequency. This causes the generally known problem, VCO pulling [21] due tothe coupling of RF input signal or the power amplifier signal into oscillator. An oscillatorunder injection pulling starts oscillating at the injected signals frequency depending on theinjected amplitude. This effect is strongly dependent on the injected signals amplitude andthe frequency offset from the VCO free running frequency.

Two mechanism can be listed as the cause to VCO pulling a given in Figure 1.1;

Transmitted signal may couple to VCO, through a parasitic path.A similar mechanism occurs when the supply voltage of the oscillator varies. For ex-ample, in a transceiver system where the power amplifier is switched ON & OFF, dueto the finite output impedance of the supply source, supply voltage includes harmonicsfrom the switching frequency of the PA [21].

Receiver signal may include strong inband interferers which are amplified by the LNAand may couple to VCO.

When the interferer frequency is close to the LO frequency coupling through the mixermay pull VCO frequency to interferer frequency. With a buffer between VCO and mixer

would increase the reverse isolation and reduce the pulling effect.



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1.1 Project Description 3

a low pass filter since the information band after mixing is at baseband. However,it is clear that such an architecture is more susceptible to 1/f noise and DC offsets.

Moreover, in such an architecture, since PA frequency and VCO frequency is designed tobe same, any leakage from transmitted signal to VCO is double mixed with the receivedsignal leading to pollution of the information band. This effect is generally regarded ascross talk and it is undesirable.

In some architectures, the local oscillator of the transceiver is designed to operate at2 fLO. It is followed by a quadrature divide by 2 block in order to perform imagerejection. The coupling effect of PA to VCO resonator is then reduced, however 2ndharmonic of transmitted signal still couples to VCO and receiver suffers from pullingeffects.

Another solution would be the implementation of a low frequency VCO followed bya frequency multiplier as given in Figure 1.2. This frequency multiplication can beperformed with an injection locked divider and a mixer as illustrated in Figure 1.3.This configuration allows the usage of an LO frequency that has a non integer relationbetween the PA frequency. However, main draw back of this system is the spuriouscomponents produced after mixing.

Figure 1.3: LO generation with injection locked mixing

Alternatively, a PLL loop could be a candidate for a system. Reference oscillator whichcould be implemented with an LC oscillator runs at a lower frequency and the LO

frequency is generated by a PLL loop. VCO of the PLL loop can be implemented witha simple ring oscillator.

Figure 1.4: LO Generation with a PLL system



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4 Introduction

Response of a PLL system to VCO Pulling

As a negative feedback control system, PLL would try to compensate for the phase error atthe output of the PLL phase detector. Thus, PLL responds to any phase-frequency changes.However, the rate of change in phase-frequency is also important since there exist a limitin phase-frequency change that drives the loop out of stability. Brief explanation on thislimitation is given in Appendix A.

Depending on the frequency offset of the injected signal, PLL sensitivity to the injected signalalso changes. Since the PLL suppresses the effect of the injection within the PLL bandwidth,the injection effects within PLL bandwidth reduce.

A wideband PLL system offers a solution to VCO pulling from two perspectives; Firstly, Thenon integer relation between the reference VCO and the transmitter frequency reduces the

pulling. Secondly, because of the wide loop bandwidth the injection pulling is also suppressed.

1.2 Report Outline

The goal of this thesis is to review the theory, design and analysis of PLL circuits and completea detailed design of a 4.9 5.9 GHz Wideband CMOS PLL Frequency Synthesizer.Chapter 2 presents the noise fundamentals of PLLs and explains how noise is defined bothin time and frequency domains. Transfer functions are derived to calculate the output noisecontribution of the loop components. Relation between time domain and frequency domain

analysis is also given briefly.Chapter 3 concentrates on the phase frequency detector and charge pump design up to theirfinal phase; layout extraction. In this chapter, high frequency operation of these componentsare explained, and techniques that offer a solution to problems that occur from high frequencyoperation, are described.

Chapter 4 discusses the methods of high frequency operation in ring oscillators. Frequencyimprovement in multi loop architectures are investigated and gain stages that can be usedin multiloop configuration are identified. Since the gain of ring VCOs, KV CO , is sufficientlyhigh, techniques to reduce KV CO are derived. Layout limitations on operating frequency ofthe VCO are also given in this chapter.

Chapter 5 is a review of overall performance of the Wideband PLL. It explains how thestability of the loop is satisfied for all the operating range. Top level layout routings are alsoexplained in this chapter.

Chapter 6 is a review of the thesis, conclusions and recommendations are given.



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6 Background

IN =IN =

1N

OUT =

1NOUT

OUT = NIN

Detailed information on loop dynamics can be found in Appendix A.

2.2 Noise

2.2.1 Interference Noise

Interference noise is mainly caused by the undesirable interaction between the circuit blocksin a system-on-chip architecture. In many chips all of the clocks and events are harmonicallyrelated to each other thus interference noise may be regarded as cyclostationary in its nature[3]. Power supply noise or electromagnetic interference between wires are the two most com-mon sources of the interference noise. This kind of noise can be reduced down to a significantextent by a careful layout techniques.

2.2.2 Intrinsic Noise

Intrinsic noise is mainly originated from the elemental properties of devices and circuits. Incontrast to interference noise, intrinsic noise refers to random noise signals that can be reducedbut never eliminated. Here, a brief descriptions of electronic components is given.

Resistors produce a type of noise, called thermal noise. It is originated by kinetic energygained by the free charge carriers [26]. Thermal energy causes carriers to move randomlyinstead of following polarities.

Diodes produce a type of noise called shot noise. The diffusion mechanism in diodes is theorigin of this type of noise. The displacement of individual carriers is a random process, thereoccurs slight fluctuations across the junction. It has a white power spectral density.

MOS Transistor operates as a gate modulated resistance between the source and drain area.Thus its noise is mainly thermal origin.

2.3 Noise in Wideband PLLs

Output spectrum of an oscillator is basically determined by the transfer functions of each blockto output. Thus, PLL response to noise contributions of each block is greatly important. InWideband PLLs, phase noise of oscillators and charge pump are critical issues that basicallydetermine the system performances. PLL inband noise is dominated by charge pump whilethe vco has considerable superiority in the noise outside the loop bandwidth. The responseof a PLL system to abrupt phase changes, non idealities such that spurious peaks, noise etc.shall be well characterized.

Location of various signal noise sources are seen in Figure 2.2. Analysis of PLL noise transferfunctions reveals more insight on the noise shaping effect of PLL loop.



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8 Background

Figure 2.3: Output spectrum of an ideal oscillator

Figure 2.4: Phase noise definition

2.3.2 Frequency Domain Noise Analysis

In the linear noise model of the PLL loop given in Figure 2.2, ref stands for the noise thatappears at the reference input to the PFD and it has the form rad/

Hz. It is comprised of

the noise components such as reference crystal oscillator, crystal buffer and reference dividerif available. div represents the output noise of divider in rad/

Hz. vco is the phase noise

of the free running oscillator, it is also expressed in rad/Hz. pfd is the noise of the phase

frequency detector that appears at PFD output. n,cnt is the noise voltage at VCO controlline in consequence of loop filter noise or any noise sources coupled to control line. n,cntis expressed in V/

Hz. in,cp represents the noise current of charge pump and has a unit

of A/Hz. Noise contribution of each block are studied separately here that other noise

contributions are assumed to be zero while calculating contribution of one block.

Input Reference Noise

Input reference noise is one of dominant noise sources in a PLL loop. For the cases that inputsignal is not a pure sinusoid i.e. input phase varies with time, transfer function of excessphase from reference input to VCO output is given as in Equation-2.2;

Href(s) =out(s)

ref(s)=

F(s) Kpfd Kvcos1 + F(s) Kpfd KvcoNs

(2.2)

For any type of loop filter, F(s), as input phase varies very slowly, i.e. as s 0, Href N,transfer function converges to a constant, N, division ratio. And for infinitely fast changestransfer function converges to 0 indicating that PLL system does not respond to high fre-quency inputs. As a result noise from reference input has a low pass characteristic. Thus,



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2.3 Noise in Wideband PLLs 9

Href corresponds to low pass filtering of the reference noise multiplied by the division ratio,N.

(a) Input reference noise (b) Transfer function of referenceinput

(c) Total reference noise appear-ing at output

Figure 2.5: Input reference noise contribution

Power spectral density of the reference phase noise contribution is given in Figure ??. In thisfigure, loop filter is supposed to have a single pole and a stabilization zero. Reference noiseonly has 1

f2component which is practically not the case. For low frequencies, output power

spectrum has the same slope with the input reference power spectrum, however its magnitudeis multiplied by N2. At cutoff frequency additional slope of 20dB/dec is introduced by theloop filter.

Phase Detector Noise

Phase detector noise is generally much smaller than the reference noise and in most cases it isskipped in calculations. Phase Detector of the PLL loop exhibits the transfer function givenwith Equation 2.3.

Hpfd(s) =out(s)

pfd(s)=

F(s) Kvcos1 + F(s) Kpfd KvcoNs

(2.3)

Disregarding of the loop filter type, for frequencies close to 0, s 0, transfer functionconverges to NKpfd . This result means that for low frequencies phase detectors noise magnitude

appears at the output of PLL with multiplied byN

Kpfd .

For frequencies s , transfer function goes to 0 with 20dB slope meaning that outsidethe loop bandwidth phase detectors noise is not dominant contributer to VCO output noise,which is a sensible result. PLL loop responds to PFD noise in the same way as referenceinput. Only the magnitude of transfer function at low frequencies is now NKpfd .

Noise Injected to Loop by Charge Pump

For a practical PLL system, when the loop is locked the average current transfer to the loopis zero. However, charge pump noise current is injected to the loop filter during the non zeroUP & DN pulse widths. Charge pump noise current can be calculated as in Equation 2.4.



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10 Background

(a) Phase frequency detectornoise

(b) Transfer function of PFD (c) Total phase detector noise ap-pearing at output

Figure 2.6: Phase frequency detector noise contribution

i2ncp = 2 dzTref

I2CP,noise (2.4)

where ICP,noise stands for the total current noise density of the charge pump in A/Hz. dz

is the duration of the UP & DN pulse widths during the lock condition. Factor of 2 refersto the noise contributions of both UP & DN pulses. Tref is the period of the reference inputsignal. The magnitude of charge pump current noise power density i2nCP is proportional to theduty cycle of the charge pump and the frequency of the reference input as seen in Equation2.4. Thus, for high frequencies, switching of the UP & DN current sources becomes morecritical.

Charge pump of the PLL loop exhibits the transfer function given with Equation 2.5.

HCP(s) =out(s)

incp(s)=

2

ICP F(s) Kpfd

Kvcos

1 + F(s) Kpfd KvcoNs(2.5)

Here noise current of charge pump is assumed to be white. For frequencies s 0, transferfunction converges to;

20log(2NICP )

Magnitude of low frequency noise contribution of charge pump current is multiplied by20log(2NICP ). For frequencies higher than the loop bandwidth, transfer function has a 20dBof slope and goes to 0. As a result, it can be concluded that charge pump noise is dominantwithin the loop bandwidth and its contribution is negligible outside the loop bandwidth.

In a practical charge pump circuit, non ideal effects such as leakage currents, magnitudemismatch between UP & DN currents or switching time mismatch between UP & DN currentsare critical in reference spur calculation. However, they are not critical issues in CP noisecontribution as Equation 2.4 adequately includes the parameters that control CP noise.



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(a) Charge pump noise (b) Transfer function of CP

(c) Total charge pump noise ap-pearing at output

Figure 2.7: Charge pump noise contribution

Noise on Control Line

Thermal noise originated from the loop filters resistance, power supply noise coupled tocontrol line or voltage buffer used in control line contributes to total PLL output noise.These contributors are investigated here in details.

Loop Filter NoiseLow pass filter of the PLL loop exhibits the transfer function given with Equation 2.6.

Hlpf(s) =out(s)

lpf(s)=

Kvcos


It is interesting that loop filters noise transfer function is dependent on the type of thelow pass filter. In case the loop is a 1st order, i.e F(s) = 1 the transfer function has alow pass characteristic as seen in Equation 2.7.

For F(s) = 1

Hlpf(s) =out(s)

lpf(s)=

Kvco

s+KpfdKvco

N

(2.7)

However, if the filter has a zero and a pole,i.e.;



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12 Background

F(s) = 1+s1s2

transfer function characteristic becomes band pass. The closed loop noise power densitycontribution of loop filter to output is then given in Figure 2.8;

(a) Loop Filter noise voltage (b) Closed loop transfer function of loop fil-ter

(c) Total loop filter noise appearing at out-put

Figure 2.8: Control line noise contribution

Hlpf(s) is the bode plot of the noise transfer function and only the thermal noise ofloop filter resistance is taken into account. However if loop filter is implemented in anactive configuration, it is likely that active part of the circuit contributes to the outputnoise of the loop filter as well.

Power Supply Noise Transfer through VCO Control Line In a PLL system themagnitude of phase noise, i.e., the amount of jitter is strongly dependent of the powersupply voltage. It is generally assumed that the maximum supply voltage variation is

10% percent.An oscillator under power supply noise interference, can be regarded as a voltage con-trolled oscillator that has power supply as control input. Its dependence on Vdd isconsidered as supply sensitivity or supply gain. This gain is measured easily by observ-ing the output frequency spectrum of VCO while the actual control inputs are zero. Ifthis gain is expressed as Kvdd, phase noise induced by power supply noise can be givenas in Equation 2.8 [6];

Svdd(s) =K2vddf2

SNvdd (s)(2.8)

Oscillator phase noise due to impulsive supply noise;



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Hvdd(s) =

out(s)

vdd(s) =

Kvcos

1 + F(s) Kpfd KvcoNs (2.9)

The resulting supply noise transfer function is pretty similar to the Hlpf and it has abandpass filter characteristic as shown in Figure 2.8. Thus its low frequency componentsare rejected by the loop [3].

VCO Noise

Another noise source, in fact the dominant noise in the band of interest, is VCO phase noiseand can be modeled by transfer function given in Equation 2.10;

Hvco(s) =out(s)

vco(s)=

1


For any type of loop filter, F(s), as s 0, Hvco = 0, and as s , Hvco = 1. When theloop filter has a zero and a pole, i.e. ;

F(s) = 1+s1s2

it can easily be seen that transfer function has two zeros at the origin realizing a high passcharacteristic with +40dB/dec slope for low frequencies. The zeros at the origin acquiresthat for small changes of vco, output phase noise is negligibly small. When the PLL loopis locked, excess phase of VCO is sensed and converted into voltage via PFD, CP and loopfilter path. Thus the voltage variations on the control line compensates for the small phasevariations in VCO performing a negative feedback.

(a) VCO open loop noise (b) Transfer function of VCO (c) Total VCO noise appearingat output

Figure 2.9: VCO noise contribution

For very fast changes of input phase VCO phase noise is transferred to output with a gainof 1. This property reveals an interesting conclusion that phase noise of VCO is subject tointegration.



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14 Background

One basic solution is increasing the loop bandwidth of PLL system i.e. lowering the lock timeof PLL; however this would cause the low pass filter response to higher frequencies leading

more instable VCO control voltage.

The loop bandwidth should be as larger as possible, in order to minimize the output phasenoise due to the VCO intrinsic phase noise. On the other hand, it is essential to keep the loopbandwidth smaller than the reference signal in order to keep the loop stable and suppress thereference spurs.There is a strict trade off on keeping the in-band phase noise minimum andretaining the spurious levels.

Divider Noise

Frequency divider of the PLL loop theoretically converts the high input frequency to lowerfrequencies by a factor of the division ratio. This division ratio may be integer or fractionalbased on the application. Modeling the noise of frequency divider of the PLL is mode criticalthan the other blocks in the loop [14]. This is mainly because the condition that dividers aregenerally followed by blocks that are sensitive to the threshold crossings of the divider outputsignal. This reveals an interesting property that overall noise behavior of the PLL loop isaffected by the divider only during the threshold crossings.

Divider of the PLL loop exhibits the transfer function given with Equation 2.11.

Hdiv =out(s)

div(s)=

F(s) Kpfd Kvcos1 + F(s) Kpfd KvcoNs

(2.11)

It has the same transfer function as the reference signal. This is an expected result, becauseit is one of the two inputs of the phase-detector. For any loop filter F(s), Hdiv(s) = N fors=0, and Hdiv(s) = 0 for s = .

(a) Divider Open Loop Noise (b) Transfer Function of Divider (c) Total divider noise appearingat output

Figure 2.10: Divider noise transfer function

Intrinsic noise contribution of divider generally has a flat spectrum, white noise floor, exceptfrom the 1/f, flicker noise effect [14]. Ignoring the 1/f components, the transfer functionHdiv corresponds to a low pass filtering of the divider noise multiplied by N as given in Figure2.10. As a result, noise from the divider has a low pass characteristic.



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2.4 Time Domain Noise Analysis 15

PLL Total Output Phase Noise

Phase noise contribution of each block to the output in a PLL is already calculated in abovesections. Overall PLL phase noise is achieved by using the Equation 2.12.

Sout(f) = Sref(f) |Href(j2f)|2 + Spfd(f) |Hpfd(j2f)|2 + Sincp (f) |HCP(j2f)|2

+ Slpf(f) |Hlpf(j2f)|2 + Svdd(f) |Hvdd(j2f)|2 + Svco(f) |Hvco(j2f)|2+ Sdiv(f) |Hdiv(j2f)|2 (2.12)

Observation of Equation 2.12 shows that at low frequencies, the reference signal, the phase-detector, the loop filter and the divider are the significant noise contributors within thebandwidth of the PLL. At offset frequencies higher than the PLL bandwidth, the phase noiseof the PLL is approximately dominated by VCO.

Figure 2.11: Total output noise

In order to minimize the reference noise contribution, the loop bandwidth must be set tosmaller values as possible. However, in this case acquisition time increases, acquisition rangedecreases and the stability degrades. To minimize the VCO noise contribution at high fre-quencies, the loop bandwidth must be maximized. In this case, acquisition time is decreased,acquisition range is increased and stability is improved. In applications where the input has

negligible noise, like a crystal oscillator, the loop bandwidth is maximized for an improvedperformance.

2.4 Time Domain Noise Analysis

Noise sources such as thermal noise, frequency modulation (FM), amplitude modulation(AM), phase modulation (PM), and spurious components that are produced by the systemcontribute to total noise that causes jitter in the clock signal and this total noise is acceptedas a general measure in calculation of jitter.

Jitter is the instantaneous variations in the phase of a signal that causes the signal deviatefrom the ideal position. In a PLL system this momentary variations can be observed as the



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16 Background

time variations in zero crossings of the signal. The expected crossings in a signal never occurexactly where desired as given in Figure 2.12. Defining and measuring the timing accuracy of

those crossings (jitter) is a critical measure of the performance of communication systems.

Figure 2.12: Digital waveform with jitter

In a system where the blocks are generally driven by square wave signals, it is more convenientto express the noise in terms of jitter. To draw a complete picture of jitter control mechanism,

jitter metrics have to be well defined.

2.4.1 Jitter Metrics

Transitions of any type of periodic signal can be expressed as the sequence of positive edgethreshold crossings, {i}. Ideally, for a noise-free signal, the following condition should bevalid for all cases ; i = iTwhere T represents the period of the signal. When the clock signalis noisy, i can be given in a statistical form as i = iT+ i.

Figure 2.13: Waveforms illustrating the period cycles

Edge to Edge jitterJee is a measure of jitter as the difference between the threshold crossings of noise freereference trigger and its response [14]. In other words it is the delay variations of inputand output of a driven block under a noise free reference input assumption. Jee is aninput referred jitter metric defined only for the driven systems such as phase frequencydetectors, dividers or clock buffers. Since a fixed noise free reference signal is assumed,



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20 PFD & Charge Pump

3.1.1 Multiplier Phase-Detectors

Multiplier phase-detectors rely on the DC component that results when multiplying twoalternating input signals. The input signals are mostly sinusoidal for this type of phase-detectors and the DC component at the output is dependent on the phase difference betweenthe inputs. The simplest example of a multiplier type phase-detector is the analog multiplierof Figure 3.2. This multiplier block usually consists of a double-balanced mixer or four

Figure 3.2: Analog Multiplier as a Phase Detector

quadrant multiplier that performs the multiplication operation of the input signals. Phasedetection behavior of a simple analog multiplier can easily be understood from consideringtwo input signals x1(t) = A1 cos(1t+1) and x2(t) = A2 cos(2t+2). Multiplication resultfrom these two signals can be given as in Equation 3.2;

VD = K x1(t) x1(t)=

KA1A2

2 {cos [(1

2)t+ (1

2)] + cos [(1 + 2)t+ (1 + 2)]

}(3.2)

When two input signals are equal in frequencies, i.e. 1 = 2 , output component becomesa DC term that is proportional to the phase difference of the input signals. In Figure 3.3,output voltage with respect to the input phase difference is given.

Figure 3.3: Analog Multiplier Output

Gain of such characteristic is given by the derivative of its output voltage with respect to theinput phase difference as below;

KPFD =VDERR =

ERRKA1A2

2 cosERR

=KA1A2

2 sinERR (3.3)



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3.1 Phase Frequency Detectors 21

This function is periodic with the phase error. Phase detectors gain is zero when phase errorzero and it is maximum when the phase error 90o and equal to the maximum output voltage

of multiplier. and phase detector gain varies sinusoidally with the phase difference. Whenthe output voltage is zero, i.e. the phase difference between input signals is 90o, locking inmultiplier type phase detectors can be considered as quadrature phase detector.

Thus the loop locks for a phase difference of 90o producing zero output. This makes the usefulphase detection range to be limited by /1.

As ERR departs from 90o, the slope of cosERR and hence the equivalent KPFDdecreases.

Also KPFD is a function of input signal amplitudes, A1 and A2, which is an undesirableattribute, because a PLL employing such a phase-detector exhibits amplitude dependentstatic and dynamic behavior.

Another disadvantage of multiplier-type phase-detectors is, they produce zero DC out-put when the input signal frequencies are different, 1 = 1. As a result, the ac-quisition performance of the loop depends on how much the difference component at = 1 = 1 is passed by the loop-filter.

3.1.2 XOR Phase Detector

Similar operation principle is useful in explanation of XOR phase detectors. XOR componentmay be considered as an overdriven analog multiplier. However, in this case output voltageis not a function of input signal amplitudes since the output swing is between logic levels,ground and supply voltage, VDD.

Figure 3.4: Output Characteristic of Exor PFD

Output characteristic of XOR gate with respect to its input phase offset is given in Figure3.4. Since the output voltage of an XOR phase-detector varies between the two logic levels, aDC offset equal to the mean of logic 1 and logic 0 levels, V DD/2, needs to be provided at theloop-filter for the detector to function correctly [21]. In other words, XOR phase-detectorsalso lock for a static phase error of 900, at the middle of the linear range, which is /2 rads.The phase-detector gain is;

KPFD =VDD

(3.4)

On the other hand, XOR produces output voltage on both rising and falling edges of theinput signals, thus the output signal has double frequency component as seen in Figure 3.5.



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Figure 3.7: UPDN

Figure 3.8: UPcharacteristic



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thus the delay between the reference input and U signal, i.e., intrinsic flip flop delay becomestINV + tINVC, where tINV is the delay of a single inverter and tINVC is the delay of a clocked

inverter. However main drawbacks of such a phase detector are;

Its output voltages are both active during the lock of the system. This property requiresa perfect matching in sink and source current sources of the charge pump.

Since the output is produced with rising edge of input signal and kept constant duringhigh level of input, deviation from 50 duty cycle degrades the performance.

Linear range is limited within .

Architecture of Figure 3.12, proposed in [17] finds a solution to the improvement of the linearrange by preventing phase detector produce wrong output signals during {tREF R, tREF}.

Figure 3.12: Architecture proposed by Mansuri

This is achieved by making use of two inverter based latch structures. Output signal is madelevel sensitive to the input reference signal, thus even the rising edge is lost, phase detector iscapable of producing correct output signals with improved input phase range. PFD outputbecomes high at the end of reset output signal width stays constant i.e. gain of PFD saturatesfor phase differences greater than

{tREF

R

}.

However in such a circuit input reference pulse is generated through a clock generator circuitwith a certain inverted delay block. This block determines the input pulse width that needs tobe set to a width slightly smaller than the reset delay. Few disadvantages exist originated fromthis delay line such as; This delay line used for pulse generation is expected to set a certainlimitation on operating frequency. Moreover, this delay increases the power consumption ofthe block.

Another type of dynamic flip flop circuit from [10] is given Figure 3.13. Operation principleof this circuit is as follows; at initial state, REF, DIV, reset, UP and DN signals are assumedto be logic low. Thus node X is precharged to VDD. At the rising edge of the reference signalUPN node is discharged to 0, thus producing an UP pulse. The same principle holds for thedivider signal, that rising edge of the divider signal sets DN signal to VDD. When both UP



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Figure 3.13: Architecture proposed by Tak

and DN signals are received, outputs are reset through a NOR gate. For the following periodsof reference signal, same principle holds.

Reference signal is applied to input through a delay block that precharges the node X to

VDD together with reset signal with an AND operation. At the rising edge of reference signaldelayed input should still be logic low. Otherwise the edge information would be lost. On theother hand, inserted delay should be slightly smaller than reset delay to prevent PLL losinglock for 0 phase difference. If the inserted delay is bigger than reset delay, than the inputclock information of previous period activates the outputs after reset.

Figure 3.14: Output characteristic in [10]

A good arrangement of these delay lines result in the characteristic given in Figure 3.14. Here corresponds to the total time delay including reset path, tREF, and gate delays of thetransistors.

3.1.6 Phase Frequency Detector Design

The phase-detector used in this work is similar to the one given in Figure 3.13 with a smalldifference as given in Figure 3.16 where NOR gate is replaced with an AND gate. The reason



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for this can be explained as below;

The goal of PFD design is to minimize delay from the reference or divider to output pulsesin order to satisfy high frequency operation. In this topology this delay equals to total delaythrough one NMOS gate and the output inverters, X1 or X2. In IBM 65nm technology,transition times of a single inverter, tINV, are in the order of 10ps. Driving capability ofthe inverter is also important in order to avoid additional delay in between PFD and chargepump which would be introduced by the additional buffer circuitry. tREF in Figure 3.16 issimply one gate delay and in the order of 10ps.

With the original structure the outputs are reset with a NOR gate. In order to do so, negativeoutputs are applied to the NOR gate. Total reset delay of this structure is tREF and thedelays through the transistors. With the rising-edge of the reference signal, UP output isset high after a transition time equal to the delay of transistors and the inverter, tINV.When the rising-edge of the VCO output arrives, DN output starts to rise. However, whennegative of DN output, DNN, reaches the threshold of the NOR gate, both outputs are resetimmediately as a result of the short reset-path delay, as given in Figure 3.15. If the delayis increased from tot to tot + tex, UP will be high for tex seconds longer and the chargedeposited on charge pump will increase by ICP tex.To solve this phenomenon, it is obvious that the reset-path delay must be more than thetransition delay from reference input to a correct UP output, or similarly the transition delayfrom VCO output to a correct DN signal. This additional delay can be introduced with anAND gate with UP and DN inputs instead of negative ones as in Figure 3.16.

Figure 3.15: Shorter delay problem in reset path

The output frequency of the PLL systems is in 4.9GHz5.9GHz. With a fixed division ratio of6, required operation frequency for phase frequency detector should be 984MHz minimum.This frequency is considered to be minimum since PFD frequency range should also includeparasitic effects from extraction.

Figure 3.17 shows the output waveforms of the extracted PFD, when the reference input andthe divider output are in phase 1GHz square wave signals. Both UP and DOWN signal pathsmust be identical for symmetrical operation. This simulation is included here in order toshow that this property assures the symmetrical operation in charge pump. In Figure 3.18,REF is leading V CO for 300ps.



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Figure 3.16: Phase Frequency Detector used in this work

Figure 3.17: PFD output for in phase 1GHz square wave inputs



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3.2 Charge Pumps 31

Figure 3.20: PFD Output Jitter

area considerably.

3.2 Charge Pumps

3.2.1 Current and Pulsewidth Mismatch

The current sources IUP and IDN when implemented using MOS transistors, charge pumpsuffer from current mismatches. When the UP current source is implemented with PMOSand DN current source with NMOS, for same amount of current sources would have certainswitching speed difference. This mismatch gives rise to a change or ripple in the controlvoltage Vc at each phase comparison. Phase offset due to charge pump mismatches is givenby Equation 3.6;

CTMIS = 2TONTREF II

(3.6)

To minimize phase error originated from current mismatch, turn on time of current sourcesshould be minimized.

3.2.2 Timing Mismatch

For the cases that charge pump is single ended, inverted UP signal is required to switch onthe PMOS current source. This introduces certain amount of timing mismatch between theUP and DN inputs. When there is a certain time delay, between inputs then the phase offsetis given by;



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Figure 3.21: Phase Frequency Detector Layout

TIMEMIS

= 2TON

TREF TD

TREF(3.7)

3.2.3 Leakage Current

One of the basic problems in charge pumps is the leakage current which may be causedby the charge pump itself, loop filter impedance, or the VCO control line. The amount ofleakage current can be as high as 1nA in sub micron CMOS [23] . The loop response forthis DC leakage current is a difference between the UP and DN signals that would producethe same amount of current equal to leakage current over one period. In other words, chargepump outputs a certain phase offset to compensate for this leakage current. This phase offsetmight be negligible for the cases that charge pump current is high however since the loopcompensation current is periodic with fREF, this gives rise to spurious component at theoutput spectrum.

The phase offset originated from leakage current can be calculated as;

LEAK = 2ILEAKICP

(rad) (3.8)

Thus total spurious component at the output is given by the total phase offset caused bythese components;



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3.2 Charge Pumps 33

Figure 3.22: Charge Pump leakage current

TOT = LEAK+ CTMIS + TIMEMIS

= 2(ILEAKICP

+TONTREF

IICP

+TONTREF

TDTREF

) (3.9)

The magnitude of the spurious breakthrough is directly related to the total phase offset andis calculated as [23];

PSPURIOUS = 20logN fBW TOT

2fREF 20logfREFfP1 (3.10)

where N is the division ratio, fBW is the loop bandwidth, fP1is the 1st pole frequency of

the loop filter. It can be concluded that to reduce the amplitude of the reference spurs,division ratio, loop bandwidth and total phase mismatch should be minimized while increasingreference frequency.

3.2.4 Charge Injection

When the switches are ON, finite amount of charge is held in the channel. The charge thatis held during ON time flows partially through both drain and source of the device. The

amount that is injected through the load capacitance gives rise to control voltage even theinputs are OFF. This leads to wrong output signal. However if the MOS transistor is turnedoff while in saturation then all the channel charge flows into the source leaving the drainterminal unaffected. Cgd capacitance of a MOS transistor in triode region is given as;

Cgd = Cgs =Cgg

2=WLCox

2(3.11)

For this condition gate to drain capacitance is larger compared to the capacitance magnitudein saturation. Thus it is always desirable to keep the output transistors in saturation in orderto minimize the glitch current.

In practical applications, this is hardly the case. Switches are generally operated in triode inorder to have small on resistance. There is constant amount of charge in the channel which



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is held when the switches are active and this charge is injected into the output nodes whenthe switches are turned off. When the input voltage of the switches has a transition time of

T while changing from logic low to high, the amount of the glitch current can be given asin Equation 3.12;

Iglitch = Cgd(VH VL)/T = Cgd S (3.12)

where S is the slew rate of the input voltage during the transition. Thus this equation revealsan interesting property that the amount of glitch current gets larger with increasing Cgdcapacitance and fast transitions. The amount of glitch current can be as large as the chargepump current or even larger than it but flowing in the opposite direction.

As a result charge injection in charge pumps is a serious problem that should be carefully

taken care of.

3.2.5 Clock Feedthrough

This is due to the parasitic capacitances Cgd and Cgs. The error occurs when the fast rise andfall edges of a clock signal get coupled into the signal node via the gate to source and gate todrain overlap capacitances. This rise in signal level at times forward biases the junction diodesand leads to an injection error into the substrate leading to wrong operation if conducted by ahigh impedance node. However clock feed through error is signal independent and manifestsitself as an output voltage.

3.2.6 Charge Sharing

This occurs when the output of a switch (for example a PMOS device) is set to high andthen the switch is turned OFF. Than the cascade connected device is activated and its voltagedependent parasitic capacitances, Cgd and Cgs, are maximized. Since the gate of this device isfloating, these parasitic capacitances share the gate charge and conduct it to both source anddrain. This causes glitches at the output of this device, i.e the loop filter. This phenomenonoccurs also in charge pumps causing glitches loop filter voltage. For High frequency highbandwidth applications of PLL, parasitic capacitances become comparable with the loopfilter. This increases the charge sharing effect.

3.2.7 Charge Pump Architectures

Charge pump architectures can be classified into groups by the form of operation; single endedand differential operation.

Single-ended charge pumps

Single-ended charge pumps are widely used since they do not require complex configurations.Moreover with tri-state operation, single ended architectures offer low-power consumptioncompared to differential architectures. Single ended architectures typically have three typesof switching locations; drain, gate and source switching.



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3.2 Charge Pumps 35

Drain switching ; For these architectures, switch is located at the drains of the currentmirror. A very simple configuration for drain switching is given in Figure 3.23 (a). When

the switch is turned OFF, drain of down current mirror is pulled to ground. When theswitch is turned ON, this time drain voltage is increased to voltage level of the loopfilter. During this operation, a high current peak occurs because of the voltage differenceof the two series on resistors of the switch transistor and current mirror transistor, M1.For PMOS side, the same situation also occurs and the amount of these pmos or nmoscurrent peaks vary with the output voltage.

For the cases that switch is located at the drains of current mirror transistors, clockfeed-through arises. Switch is directly connected to the loop filter thus high amplitudecurrent spikes that occur at the very beginning of pump up/down action are injecteddirectly to the loop filter.

Figure 3.23: Single ended charge pumps

Gate switching [27]; In Figure 3.23 (b), a charge pump architecture with gate switch-ing is given. With this topology it is guaranteed that current mirrors are always kept insaturation. Switching time is dependent on the transconductances of the mirror tran-sistors M4 and M3. In order to meet high frequency operation specifications, chargepump current may not be scaled down since switching time is dependent on the gms ofM4 and M3. This may set a limit for high frequency operation.

Source switching ; The switch can also be located at the source of the current mirrorsatisfying that current mirrors are in saturation all the time. In contrast to gate switch-ing, now switching time is not a function of gms ofM4 and M3. This configurationgives faster switching than gate switching since switch is connected to a node with lowparasitic capacitance.

There also exist other variations of single ended charge pump architectures as given in Figure3.24.

In Figure 3.24 (a) a single ended charge pump with current steering technique is proposed[11]. Operation principle is similar to to the one given in Figure 3.23 (a) however the switchingis improved by using the current switch. Thus it provides faster switching.

Another single ended topology with an active amplifier is given in Figure 3.24 (b). With thisunity gain amplifier the voltage at the drain ofM1 and M2 is set to the voltage at the output



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3.2 Charge Pumps 37

currents remain off all the time. However, in practical applications, after the additional reset-delay, the loop locks for a finite phase-error if there is a current-mismatch. The phase-error

in terms of the mismatch ratio is given in Equation 3.9. As long as the reset-delay or themismatch increases, the phase error also increases.

Figure 3.25: CPhigh speed

Figure 3.25 shows a fully differential charge-pump, which uses current steering technique.When the charge pump is not active, i.e. there is no difference between UP and DN currentpulses, charge pump current is directed to a dummy branch. The advantage of this architec-ture is that when the output switches are turned off, the currents in transistors M9 and M11or similarly M10 and M12 remain constant, and is just steered to the other branch. Withthis architecture current sources are always on and in saturation, thus charge sharing effectsdue to the switching are minimized. However the output common mode voltage needs to becontrolled in order to satisfy that full output swing can be used.

Switch Design

Transistors M1 to M8 are simple switches processing the information received from the phasefrequency detector. As to lower the on resistance of these switches, it is desirable to maximizetheir sizes. If the channel resistance is not sufficiently low then there is a certain voltage dropacross the switch which limits the available the output range for control voltage. When theswitches are too large, another limitation reveals that their parasitic capacitances increasesthe slewing and slows down the switching operation. High frequency operation may not beperformed when the switches are too large. Channel resistance of a MOS transistor operating



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in triode is given as in Equation 3.13 [20];

ron = 1iD/vDS

= 1KW

L[(VgsVT)VDS

V2DS2

]

VDS

=L

KW(Vgs VT) VDS

(3.14)

A good switch design is performed with a good compromise of channel resistance and gatedrain capacitance. However channel resistance is proportional to L while the gate drain

capacitance is proportional to WL as given in Equation 3.11. Thus, for a minimum lengthdevice, there exist an optimum device width.

On the other hand, switch size is critical parameter, also in noise contrubition of the chargepump. Noise voltage contribution of a switched transistor can be derived from its thermalequivalent noise resistance as [20];

e2ron = 4KTronV2/Hz =

2KTron

V2/rad/s (3.15)

Noise contribution theory also claims that on resistance of the switches should be minimizedin order to reduce charge pump noise contribution.

Simulations and LayoutIn Figure 3.26 noise voltage at charge pump output is given. Different curves refers toswept switch sizes. If the switch sizes are too small, (i.e. 5u), in band noise contributionof switches can be as high as 5dB additional. However after a certain switch size, noiselevels stay almost same. As a result switch sizes is chosen as 20u and switch layout isgiven in Figure 3.27.

Common Mode Feedback Circuit

With fully differential architectures, output common mode voltage is not well defined. Chargepump architecture used in this design is a fully differential one. When the currents flowingthrough each branch are not balanced, output voltages may increase or decrease. In otherwords, when the output switches are both OFF, output node voltages are not defined. Thusa control mechanism is required to set these voltages to a proper value. The circuit given inFigure 3.28 is used in this work for common mode signal stabilization at output.

Operation of this block can be briefly expressed as follows; For the case that both OUT+ andOUT are equal to each other in magnitude but they have opposite signs, the current in M1and M3 would be equal to each other while the current in M2 and M4 would be equal too.This relation holds as the magnitudes of the input differential voltage stays the same. Aslong as OUT+ and OUT are equal in magnitude but have different polarities, the current



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3.2 Charge Pumps 39

Figure 3.26: Noise voltage at charge pump output

Figure 3.27: Switch layout



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3.2 Charge Pumps 41

M15,M16 12u/0.2u

M17,M18,M19,M20 25u/60n

M21,M22 8u/0.2u

Table 3.1: UGB transistor sizes

Figure 3.29: Transconductance of common mode loop



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3.2 Charge Pumps 43

(a) Unity Gain Buffer (b) UGB Schematic

Figure 3.31: Unity gain buffer used in this work

Unity Gain Buffer Circuit

In single ended charge pump architectures charge injection of the switches can be eliminated

with correct placement of the switches, (i.e. drain, gate, source switching) as mentionedin Section 3.2.4. However, with differential architectures, switches are located at the outputnodes, and the topology suffers from charge injection of both the switches and common sourcenodes X and Y or X and Y, (nodes are shown in Figure 3.25. The charge injection fromnodes X and Y is typically much greater than that of the switches, and modifications has tobe made to reduce these effects.

On the other hand when the dummy branch is inactive, the nodes VDX and VDY in Figure3.25, are not defined. Therefore a buffer is required to hold the voltage of the replica node tothe same voltage as that of the output node.

The advantage of this architecture is that when the output switches are turned off, thecurrents in transistors M

9and M

11or similarly M

10and M

12remain constant, and is just

steered to the other branch. This means that the voltages at nodes X and Y or X and Y

stay approximately constant, minimizing charge sharing. The opamps used in the bufferedcharge pump are in a standard rail to rail input topology [28].

In a simple rail-to-rail input stage, an n-channel differential pair and a p-channel differentialpair are used in parallel as shown in Figure 3.31(b). There are basically three operationregions; when the common mode voltage, VCM is near the negative power supply, Vss, or Gndin this work, only the p-channel pair operates. For VCM, near the positive power supply, Vdd,only the n-channel pair operates. For VCM around mid-rail, both differential pairs operate.As a result, at least one of the two differential pairs will be operating for any VCM betweenthe rails.

Since there are three regions of operation for the input stage of the unity gain buffer, there are



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three different regions for the total transconductance, gmT, which is given, in strong inversion,by;

gmT = gmn + gmp =

2KnIn +

2KpIp

where Kn and Kp are the transconductance parameters of the n and p channel inputtransistors.When the current sources are implemented with a constant current sources, gmTvaries depending on the operation region. This may lead to a complexity in frequency com-pensation, thus the loop may be driven out of stability. In Figure 3.32, AC response of theclosed loop for different common mode input is given. Minimum and maximum bandwidthsare as 285.7MHz and 389.1MHz which is well above the loop bandwidth for a common moderange of 100m 1.1V and stays below the reference input not to respond to input signal.

On the other hand, the noise from the CMFB circuit and unity gain buffer circuit is com-mon mode to the charge pump, so it has little impact on the phase noise of the frequencysynthesizer.

Simulations and LayoutTransistor sizes of the unity gain buffer circuit is given in Table 3.2.

M1,M2 18u/60n

M3,M4 25u/60n

M5 2u/0.2u

M6 4.2u/0.2u

M7,M8 6u/2u

M9,M10,M11,M12, 16u/2u

Table 3.2: UGB transistor sizes

Layout for unity gain buffer circuit is given in Figure 3.30(b).

Bias Block

The complete circuit of the bias block used in charge pump design is shown in Figure 3.33.

The circuit consist of wide swing current mirrors and a start up circuit. Transistors M1 toM2, form the n channel current mirror together with the diode connected bias transistor M12.Transistors M3 to M4 simply act as a current mirror. Gate voltages of these transistors arederived from the diode connected transistor M12. The current for the biasing transistor M12is produced by the current copy transistors M13 and M14. Similar structure holds for thePMOS current mirror components. M11 is used for biasing purposes of gates ofM5 and M6and the current into this diode connected transistor is produced via M9 and M10.

This bias loop has two solutions since it is a modified version of general gm bias circuit. Thereis a possibility for the current into the transistors to be zero. Once this occurs, the circuitstays stable in this condition forever thus it does not start up. To ensure this condition doesnot happen, a start up circuitry that affects the bias loop only when the currents are zero, isrequired. M15, M16, M17 and M18 are included for this purpose. When there is no current



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3.2 Charge Pumps 45

Figure 3.32: AC response for different input levels of UGB

Figure 3.33: CP-Bias Block



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3.2 Charge Pumps 47

Figure 3.35: Transmission gate as a switch

For fully cancellation of charge injection, qN and qP should be equal to each other.

qN = WNLNCox(VCKVIN1

VTHN) = WPLPCox(VCK

VIN1

VTHP) (3.16)

From this result, it can be seen that, cancellation of charge depends on the accuracy in devicesizes, and the threshold voltages of PMOS and NMOS devices as in Equation 3.17. Thustotally cancellation is not possible however reduction in charge injection is expected.

WNLN(VCK VIN1 VTHN) = WPLP(VCK VIN1 VTHP) (3.17)

Charge pump of this work is modified as given in Figure 3.36 in order to have suppressedthe high speed glitches. After adding the modified switches, the high-speed glitches arealmost completely eliminated from the output current since PMOS and NMOS transistors intransmission gates are matched. In practical implementation, however, this performance willbe limited by the resistance in the loop filter and any other parasitic resistance like routing

resistance and gate resistance.

Figure 3.36: Modification for Glitch Suppression

However there is an obvious drawback which is the increased complexity as compared withthe standard architectures, as it is now necessary to generate and route both the primaryinput signals and their inverses.



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3.2 Charge Pumps 49

Figure 3.38: Complete Charge pump layout



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52 VCO & Divider

Transfer Function : This denotes the direction of frequency change versus controlvoltage and sometimes referred to as Slope Polarity. A positive transfer function de-

notes an increase in frequency for an increasing positive control voltage. Conversely, ifthe frequency decreases with a more positive control voltage, the transfer function isnegative.

Phase Stability : The output spectrum of the VCO should approximate as good aspossible the theoretical Dirac-impulse of a single sine wave. It is mostly referred to asSpectral Purity and quantified by phase noise, which is expressed in terms of dBc/Hz.

Frequency pushing : It is the dependency of the center frequency on the power supplyvoltage expressed in MHz/V. In this work, SV DD is used as the sensitivity parameter.

Frequency pulling :It is the dependency of the center frequency on the output loadimpedance.

Tuning Speed :This is the time required for the output frequency to settle to within90% of its final value with the application of a tuning-voltage step.

Output Amplitude : It is desirable to achieve large output oscillation amplitude,thus making the waveform less sensitive to noise. The amplitude trades with powerdissipation, supply voltage, and even the tuning range. Also the amplitude may varyacross the tuning range, which is an undesirable effect.

Output Characteristics : This defines the output waveform of the VCO. In PLLapplications, sine or square-waves are used mostly.

Power Dissipation : As with other analog circuits, oscillators suffer from trade-offsbetween speed, power dissipation, and noise.

In literature many types of oscillators can be found [19]. Depending on the application, thesetypes are beneficial or undesirable. In current application, oscillator types are discussed bytheir phase noise, i.e jitter, performance and their supply sensitivity. CMOS voltage controlledoscillators, VCOs, are customary designed either by using ring oscillator architectures or LCresonant circuits. Although amongst these applications, LC designs has better phase noiseperformance, they are undesirable due to the increased complexity and cost by addition ofhigh quality integrated inductors. In spite of LC oscillators, ring oscillators can be built inany standard CMOS technology with much less die area. Moreover, they offer multiple outputphases and wide tuning ranges. In this work, main focus is on ring oscillators due to ease inintegration.

4.1 Ring Oscillator VCOs

Ring oscillators are often used in PLL applications due to their simplicity and ease in ICintegration. Basic oscillation principle is based on the ring of inverters in a chain. However,with single ended structures it is not possible to achieve oscillation with less then three stagesand odd number of inverter stages is required [21]. In a certain technology, total delay ofthree inverter stages puts a limit to the maximum achievable frequency.



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4.1 Ring Oscillator VCOs 53

4.1.1 Single Loop Ring Oscillator Design

Figure 4.1: Three-stage ring oscillator

Figure 4.1 shows a typical single-stage inverter placed in a unity-gain loop where R and Care the output equivalent node resistance and capacitance of the inverter stage, respectively.

Under the assumption that all stages are identical, system has three poles located at p inEquation 4.1 which is the 3dB bandwidth of a single stage inverter.

p =1

RC(4.1)

For three stage inverter, total phase shift of the system at p equals to 135o (each stagecontributes 45o) and as = total phase shift becomes 270o. Therefore, a certainfrequency exists for the system that total phase shift equals to 180o, i.e. each stage has aphase shift of 60o. Each stage also contribute a DC phase shift of 180o thus waveform ateach node is

240o out of phase with respect to the previous node.

Nevertheless, to meet the Berkhausen criteria, loop gain must be equal to unity at the oscil-lation frequency. Transfer function of each stage is given as;

G(s) = A1 + sp

(4.2)

Thus, transfer function for the open loop three stage oscillator is given as;

H(s) = A3

(1 + sp )3

(4.3)

To meet the phase shift criteria of 180o in three stage design, single stage should have a phaseshift of 60o at oscillation frequency ;

G(s) = arctanop

= 60o o =

3p (4.4)

From 4.1 and 4.3 general oscillation frequency can be given as;

O =tan

RC(4.5)

where is the total phase shift of each stage individually.



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56 VCO & Divider

Figure 4.4: 3 stage ring oscillator 1st order model

Prior to small signal behavior study, it should be strictly stated that ring oscillators arehighly nonlinear, large signal systems. Their operating parameters greatly deviate from theones obtained from small signal analysis. Since rail to rail switching is the main design goal inorder to minimize phase noise requirements, it is likely that transconductance of transistorsdecreases with increasing signal swing. However small signal analysis is still essential to attainan insight about the circuit parameters that control frequency.

In multi loop architectures main loop is intentionally designed to be stronger than the auxiliaryloop, thus phase relation is determined by the main loop.

For a three stage design following condition holds;

Vn+1 = Vnej (4.12)

Vn+1 = Vk+1ej (4.13)

where the output of a single stage can be given as;

Vn+1 =R

1 +jRC(VnGM Vk+1gm) (4.14)

Output Vk+1

can be rewritten as Vn+1ej. Thus;

Vn+1 =RGM

1 +jRCVn +

Rgm1 +jRC

Vn+1ej (4.15)

Rearranging the Vn and Vn+1 terms, transfer function can be written as given in Equation4.16.

H(j) =VnVn+1

=RGM

1 +jRCRgmej (4.16)

or in other form, the term ej can be expressed in terms of its imaginary and real parts;

H(j) =VnVn+1 =

RGM1 gmR cos+j(RCRgm sin) (4.17)



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4.1 Ring Oscillator VCOs 57

Phase shift of each stage can be calculated from the phase of its transfer function.

H(j) = tan1RCRgm sin

1 gmR cos

(4.18)

As previously mentioned, phase relation between the stages is determined by the main loop.Thus, obtained result in Equation 4.18 should be equal to the phase difference between Vnand Vn+1, . Thus phase shift of single stage in terms of circuit parameters can be given as;

tan( ) = tan = RC gmR sin1 Rgm cos (4.19)

From Equation 4.19 oscillation frequency can easily be given as;

o =tan

RC gmC

[tan cos+ sin] (4.20)

For the case gm = 0, oscillation frequency equals to the one given for single loop architectures.It is clearly stated in Equation 4.20 that frequency improvement in multiple pass architectureshould be possible under the condition that tan cos+sin 0 is satisfied. Since for a fixednumber of inverter stages, available phases in loop is determined, connection scheme shouldbe done to satisfy this condition. For a three stage system, total open loop gain is given asin Equation 4.21;

G(j) = H(j)3 = RGM

1 gmR cos+j(RCRgm sin)3

(4.21)

According to the Berkhausen criteria, the magnitude of the loop gain at the oscillation fre-quency should be equal to unity. For a three stage ring oscillator, condition in Equation 4.23should hold.

G(j) = |H(j)|3 = RGM(1 gmR cos)2 + (RCRgm sin

Documents

Donmez a. - Wideband PLL System as a Clock Multiplier (2009)