Upload
elijah
View
30
Download
0
Embed Size (px)
DESCRIPTION
Documentation Standards. Circuit specification. Description of what the system is supposed to do, including a description of all inputs and outputs and the functions that are to be performed (page 312). Block diagram. Informal pictorial description of the system’s major functional modules. - PowerPoint PPT Presentation
Citation preview
Documentation Standards
• Circuit specification.– Description of what the system
is supposed to do, including a description of all inputs and outputs and the functions that are to be performed (page 312).
• Block diagram.– Informal pictorial description
of the system’s major functional modules.
• Schematic or logic diagram.– Formal specification of the
electrical components of the system, their interconnections, and all details needed to construct it (IC type, pin numbers, etc.).
Documentation Standards
• Timing diagram.– Shows the values of various
logic signals as a function of time, including cause and effect delays between critical signals.
• Structured logic device description.– Describes the internal function
of a programmable logic device (PLD), a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).
Block Diagrams
Block Diagrams
Gate Symbols
SSI
Active Levels For Pins• Each signal should have an
active level associated with it.• A signal is active high if it
performs the named action or denotes the named condition when it is HIGH or 1.
• A signal is active low if it performs the named action or denotes the named condition when it is LOW or 0.
• A signal is said to be asserted when it is at its active level.
Active Levels For Pins
Buses• Collection of two or more
related signal lines.
Timing Diagrams• Illustrate the logical behavior
of the signals in a digital circuit as a function of time.
• Causality: which input transition causes which output transition.
• Propagation delay: the time it takes for a change at the input to produce a change at the output.– Note that propagation delays
when outputs change from LOW to HIGH may differ from when they change from HIGH to LOW.
Timing Diagrams
Decoders• A decoder is a multiple-input
multiple-output logic circuit that converts coded inputs into coded outputs, where the inputs and outputs codes are different.
Decoders• Generally the input code has
fewer bits than the output codes.
• In a one-to-one mapping each input code word produces a different output code word.
• Most commonly used codes:– For input:
• The n-bit binary code.– For output:
• The 1-out-of-m code.
Binary Decoder• Binary decoder:
– The most common decoder.– n-to-2n.– The input code is the n-bit
binary code.– The output code is the 1-out-of-
m code.
Binary Decoder
Binary Decoder
Binary Decoder
Cascading Binary Decoders
Cascading Binary Decoders
Seven Segment Decoders
Seven Segment Decoders
Encoders• Reverses what a decoder does.• If a device’s output code word
has fewer bits than the input code word then the device is usually called an encoder.
• The simplest encoder is the binary encoder or the 2n-to-n encoder.
Encoders
I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y01 0 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 1 10 0 0 0 1 0 0 0 1 0 00 0 0 0 0 1 0 0 1 0 10 0 0 0 0 0 1 0 1 1 00 0 0 0 0 0 0 1 1 1 1
Inputs Outputs
Priority Encoders• Priority encoders assigns
priority to the input lines, so that when multiple lines are asserted at the same time, the encoder will produce the highest priority requestor.
I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y01 0 0 0 0 0 0 0 0 0 0X 1 0 0 0 0 0 0 0 0 1X X 1 0 0 0 0 0 0 1 0X X X 1 0 0 0 0 0 1 1X X X X 1 0 0 0 1 0 0X X X X X 1 0 0 1 0 1X X X X X X 1 0 1 1 0X X X X X X X 1 1 1 1
Inputs Outputs
Priority Encoders
Cascading Binary Encoders
Tri-State Devices• Devices whose outputs may be
in one of three states, 0, 1, or Hi-Z (high impedance).
• These devices have an extra input which is used to control if the output is floating (Hi-Z) or if it is behaving normally (page 385).
OutputEN A Y0 0 00 1 11 X Hi-Z
Inputs
Tri-State Devices
Tri-State Devices
Tri-State Devices
Tri-State Devices
Multiplexers
• Digital switch (page 398).• A multiplexer with n data
sources requires s = log2 n select lines.
• Commercially available MUX have n= 1, 2, 4, 8 or 16.
• EN enables the output.
Multiplexers
• Y = EN S’ D0 + EN S D1
OutputEN S D0 D1 Y0 X X X 01 0 0 0 01 0 0 1 01 0 1 0 11 0 1 1 11 1 0 0 01 1 0 1 11 1 1 0 01 1 1 1 1
Inputs
OutputEN S Y0 X 01 0 D01 1 D1
Inputs
Multiplexers
• General logic equation for a multiplexer is show above.
1
0
iDMENiYn
jjj
Multiplexers
Multiplexers
Multiplexers
Multiplexers
Demultiplexers
• Digital switch (page 405).• A demultiplexer with n data
outputs requires s = log2 n select lines.
Demultiplexers
Exclusive-Or Gates• An exclusive-or (XOR) gate is
a 2 input device whose output is 1 if exactly one of its inputs is 1 (page 410).
• An exclusive-nor (XNOR) or equivalence is just the opposite.
Exclusive-Or Gates
Parity Circuits• Parity detectors are circuits
that detects if the numbers of ones at its input is odd or even.
• Used to detect errors during the transmission of binary information, by using a parity bit.
• Parity bit is an extra bit included with the binary message to make the number of ones in the message either even or odd.
Parity Circuits
Parity Circuits
Parity Circuits
Comparators
• Comparators are circuits that compare two binary words and indicates whether they are equal or not equal.
Comparators
Comparators
Comparators
Adders
• Half adder adds two one bit operands and produces a two bit sum (page 431).
• HS = X Y• CO = XY
X Y CO HS0 0 0 00 1 0 11 0 0 11 1 1 0
Adders• Full adder adds three one bit
operands and produces a two bit sum.
• S = X Y CIN• COUT = XY + X CIN + Y
CIN
CIN X Y COUT S0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1
Adders
PLDs
PLDs
PLDs
PAL16L8
GAL16V8C