Document for Verification TB of RAM_OVM

7/28/2019 Document for Verification TB of RAM_OVM

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Document for Verification TB

of RAM SOC

Overview:

This document demonstrates the complete test bench architecture of 4096

RAM SOC.

Description of DUT:

The Design under Test(DUT) for this verification test bench is RAM SOC.It includes four instances of 4096 x 64 RAM chips.

Verification Plan:

The features that are to be verified thoroughly to ensure that the

functionality of RAM SOC is correct.

1. Writing to all the memory locations sequentially.

2. Reading from all the memory locations.3. Making sure that for every respective memory location which has

been selected sequentially , write data matches with the read data.

4. Writing to all the memory locations randomly.

5. Reading from all the memory locations randomly.6. Making sure that for every respective memory location which has

been selected randomly, write data matches with the read data.

7. Writing to all the even memory locations sequentially .8. Reading from all the even memory locations sequentially.

9. Making sure that for every respective even memory location, write

data matches with the read data.10.Writing to all the odd memory locations sequentially.

11.Reading from all the odd memory locations sequentially.12.Making sure that for every respective memory location which has

been selected randomly, write data matches with the read data.



13.Complete regression testing for the all above test

cases.

Fig: Test bench architecture of RAM SOC

Ram TB:

This is the top level test bench, which include objects of the following

components:

1. Configurable four Write OVC.→ To write data into RAM SOC (DUT).2. Configurable four Read OVC.

→ To read data from RAM SOC (DUT).

3. Configurable four Score Board.→ To compare write data and read data.

4. Virtual Sequencer

RAM SOC

4096x64

RAM

4096x64RAM

4096x64RAM

4096x64RAM

ram_rd_ovc[1]

ram_rd_ovc[2]

ram_rd_ovc[0]

ram_rd_ovc[3]

ram_wr_ovc[1]

ram_wr_ovc[2]

ram_wr_ovc[0]

ram_wr_ovc[3]

ram_scoreboard[0]

ram_scoreboard[1]

ram_scoreboard[2]

ram_scoreboard[3]

virtual_sequencer



→ To control each OVC's sequencer.

5. Configuration object class

→ To control the No. of OVCs and Scoreboards.

Fig: OVC (Environment) architecture of all RAM SOC

OVCs:

1. Write OVC:

Write OVC instantiates Write Agent.

Write Agent:

It includes agent configuration object to get the virtual interface instance

from OVM Config db and assigns to the virtual interface instances of driverand monitor in the connect phase.

It includes objects of the following classes.

1. Write Sequencer.

2. Write Driver.

OVCram_*_sequencer ram_*_driver

ram_*_monitor



3. Write Monitor.

4. Write agent config object.

Also, it includes ovm_enum variable is_active.

If is_active==OVM_ACTIVE, objects are created for sequencer, driver and

monitor.If is_active==OVM_PASSIVE, object is created for monitor only.

Write Sequencer:

It sends the sequences to driver.

Write Sequences:

It has a base sequence named ram_wbase_seq.

This base sequence is extended to create 4 more sequence class named:

1. ram_full_write_xtns.

→ In its body task, address of the sequence items is sequentiallyincremented from 0 to 4095 to write to all memory locations and also

produces randomized data.

2. ram_rand_write_xtns.

→ In its body task, address of the sequence items is randomized from

addresses 0 to 4095 and covered all memory locations and also producesrandomized data.

3. ram_even_write_xtns.

→ In its body task, all even address of the sequence items is sequentiallycovered from 0 to 4094 to write to all even memory locations and also


4. ram_odd_write_xtns.



→ In its body task, all odd address of the sequence

items is sequentially covered from 0 to 4094 to write to all even memory

locations and also produces randomized data.

Write Driver:

It gets the data (sequence item) from sequencer and passes it to the DUT

pins via virtual interface.

It sends data_in, write and write address from sequence to the DUT pins.

Write Monitor:

It has an analysis port to pass the monitored information from monitor toscoreboard.

An instance of sequence item is created and then data_in, write and write

addresses are assigned from interface.

2. Read OVC:

Read OVC instantiates Read Agent.

It includes ovm_enum variable is_active.

If is_active==OVM_ACTIVE, objects are created for sequencer, driver and

monitor.

If is_active==OVM_PASSIVE, object is created for monitor only.

Read Agent:



It includes agent configuration object to get the virtual

interface instance from OVM Config db and assigns to the virtual interface

instances of driver and monitor in the connect phase.

It includes objects of the following classes.

1. Read Sequencer.

2. Read Driver.3. Read Monitor.

4. Read agent config object.

Read Sequencer:

It sends the sequences to driver.

Read Sequcences:

It has a base sequence named ram_rbase_seq.

This base sequence is extended to create 4 more sequence class named :

1. ram_full_read_xtns.→ In its body task, address of the sequence items is sequentially

incremented from 0 to 4095 to read to all memory locations and also


2. ram_rand_read_xtns.

→ In its body task, address of the sequence items is randomized fromaddresses 0 to 4095 and covered all memory locations and also produces

randomized data.

3. ram_even_read_xtns.→ In its body task, all even address of the sequence items is sequentially

covered from 0 to 4094 to read to all even memory locations and alsoproduces randomized data.

4. ram_odd_read_xtns.



→ In its body task, all odd address of the sequence

items is sequentially covered from 0 to 4094 to read to all even memory

locations and also produces randomized data.

Read Driver:

It gets the randomized data from sequencer and passes it to the DUT pins via

virtual interface instance.

It sends read and read address from sequence to the DUT pins.

Read Monitor:

It has an analysis port to pass the monitored read information from monitorto scoreboard.

An instance of sequence item is created here and then data_out, read andread addresses are assigned from interface to the object variables.

Scoreboard:

It has implementation ports to implement the write functions for writemonitor and read monitor.

It has a memory model named, ref_data, which is used to store write dataand then this model is used to compare the read data.

It has some scoreboard statistics to calculate number of read, write

transactions and number of successfully compare data.

Also, it includes the functional coverage cover group for all the OVCs'transactions.

Cover point includes:



1. Write data.

2. Write address.

3. Write enable.

4. Read data.5. Write address.

6. Read enable.

At least, 10 bins have created including the extreme values of address anddata.

Overall Coverage obtained : 96.50% to 100%

Test Cases:

This RAM verification has 4 test cases (excluding base test).

We create a base_test class which includes an object of ram_tb and also

here we get the virtual interface instance from OVM Config db and weassign it to the virtual interface instances of write and read configuration

objects.

Then, base_test is extended to create 4 test cases.

test_full - Performs write and read operations in all the locations

sequentially.

test_random - Performs write and read operation in all the locations

randomly. test_even - Perform write and read operations in all even locations.

test_odd - Performs write and read operation in all the odd locations.

Top Block:



Here we define the physical interface instances and

connect it with DUT instantiated.

We set these physical interface instances in OVM Config db.

Using run_test(“”) or +OVM_TESTNAME option, we run all the test cases.

Documents

Document for Verification TB of RAM_OVM